检索结果-内蒙古大学图书馆

A Fast Hardware Architecture for Integer to τNAF Conversion for Koblitz Curves

IEEE TRANSACTIONS ON COMPUTERS 2012年第5期61卷 732-737页

作者： Adikari, Jithra Dimitrov, Vassil S. Jarvinen, Kimmo U. Univ Waterloo Dept Elect & Comp Engn Waterloo ON N2L 3G1 Canada Univ Calgary Dept Elect & Comp Engn Calgary AB T2N 1N4 Canada Aalto Univ Dept Informat & Comp Sci Sch Sci & Technol FI-00076 Aalto Finland

Scalar multiplication in elliptic curve cryptography is the most computational intensive operation. Efficiency of this operation can be significantly improved in hardware implementations by using Frobenius endomorphisms which require integer to tau-adic nonadjacent form conversion. Because conversion is one of the limiting factors in some of Koblitz curve-based cryptosystems, it has become an interesting problem. In this paper, we propose two algorithms and a novel hardware architecture to double the speed of integer to tau-adic nonadjacent form conversion.

关键词： Elliptic curve cryptography Koblitz curves integer to tau NAF conversion field programmable gate array application specific integrated circuit

来源：评论

学校读者我要写书评

暂无评论

FPGA based Fuzzy Logic Controller for plasma position control in ADITYA Tokamak

引用

FUSION ENGINEERING AND DESIGN 2012年第11期87卷 1866-1871页

作者： Suratia, Pooja Patel, Jigneshkumar Rajpal, Rachana Kotia, Sorum Govindarajan, J. Maharaja Sayajirao Univ Baroda Fac Engn & Technol Dept Elect Engn Vadodara 390001 Gujarat India Inst Plasma Res Gandhinagar 382428 Gujarat India

Tokamaks are the most promising devices for obtaining nuclear fusion energy from high-temperature, ionized gas termed as Plasma. The successful operation of tokamak depends on its ability to confine plasma at the geometric center of vacuum vessel with sufficient stability. The quality of plasma discharge in ADITYA Tokamak is strongly related to the radial position of the plasma column in the vacuum vessel. If the plasma column approaches too near to the wall of vacuum vessel, it leads to minor or complete disruption of plasma. Hence the control of plasma position throughout the entire plasma discharge duration is a fundamental requirement. This paper describes Fuzzy Logic Controller (FLC) which is designed for radial plasma position control. This controller is tested and evaluated on the ADITYA RZIP control model. The performance of this FLC was compared with that of Proportional-Integral-Derivative (PID) Controller and the response was found to be faster and smoother. FLC was implemented on a field programmable gate array (FPGA) chip with the use of a Very High-Speed Integrated-Circuits Hardware Description-Language (VHDL). (C) 2012 Elsevier B.V. All rights reserved.

关键词： Fuzzy Logic Controller field programmable gate array Tokamak Plasma control

来源：评论

学校读者我要写书评

暂无评论

Analytic Model Predictive Controller for Collision-Free Relative Motion Reconfiguration

引用

JOURNAL OF GUIDANCE CONTROL AND DYNAMICS 2012年第4期35卷 1069-1079页

作者： Sauter, Luke Palmer, P. Univ Surrey Surrey Space Ctr Surrey GU2 7XH England

Large formations of satellites currently require extensive ground-based planning to enable formation-wide collision-free reconfiguration. Allowing satellite formations the flexibility to execute collision-free reconfiguration operations onboard each spacecraft can significantly reduce the ground operations burden and increase the responsiveness of the formation to reconfiguration events. An analytic model predictive controller for fuel-minimized, collision-free trajectory following is developed. The controller exploits the natural dynamics for relative-motion path-following using minimal fuel and requires a minimal computational burden. Constraints are handled implicitly and performance provides 423 times the fuel savings compared with traditional proportional-integral-derivative-type control at the same computational speed. Through hardware testing and comparison with other approaches, results also show that constraints can also be handled explicitly while still performing significantly faster than similar forms of model predictive control for formation reconfiguration.

关键词： Proportional Integral Derivative Monolithic Satellite Quadratic Programming Time Optimal Control Defense Advanced Research Projects Agencies Formation Flying Path Planning Central Processing Unit Fractionated Satellite Systems field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

VLSI-based Real-time Signal Processing Solution Employing Four-phase Codes for Spread-spectrum Applications

引用

IETE JOURNAL OF RESEARCH 2012年第1期58卷 57-64页

作者： Balaji, N. Rao, Kakarla Subba VNRVJIET Dept ECE Hyderabad Andhra Pradesh India Osmania Univ Univ Coll Engn Hyderabad 500007 Andhra Pradesh India

Spread-Spectrum applications require a set of sequences with individually peaky autocorrelation and pair-wise cross correlation. Obtaining such sequences is a combinatorial problem. If the autocorrelation and cross correlation are taken in the aperiodic sense, then there are hardly any theoretical aids available. Thus, the problem of signal design referred to above is a challenging problem for which many global optimization algorithms like genetic algorithm, simulated annealing, and tunneling algorithm were reported in the literature. The paper aims at implementation of an efficient VLSI System for the design of an optimal pulse compression codes useful for Spread-Spectrum applications. The proposed VLSI system implements the modified genetic algorithm for identifying and generating the optimal pulse compression codes. The VLSI System is implemented on the field programmable gate array as it provides the flexibility of reconfigurability and reprogramability and it is a real-time signal-processing solution which identifies and generates optimal sequences.

关键词： field programmable gate array Four-phase codes Genetic algorithm Hamming scan Spread-spectrum applications VLSI

来源：评论

学校读者我要写书评

暂无评论

Face detection system for SVGA source with hecto-scale frame rate on FPGA board

引用

MICROPROCESSORS AND MICROSYSTEMS 2012年第4期36卷 315-323页

作者： Ding, Zheng Zhao, Feng Shu, Wei Wu, Min-You Shanghai Jiao Tong Univ Dept Comp Sci & Engn Shanghai 200240 Peoples R China Digilent Elect Technol Co Ltd Shanghai Peoples R China Univ New Mexico Dept Elect & Comp Engn Albuquerque NM 87131 USA

This paper proposes techniques for face detection using Haar-like features as weak classifiers and gives the implementation details for an FPGA development board. We analyze and discuss the relation between the system computation cost and selection of the image scaling factor. Based on the empirical results of our previous work, we give a new method to select the stop threshold for the image reduction process, which reduces the total computation by half. We present and implement an improved integral image pipeline calculation design. We also provide a color image output mode to let our system enjoy more human-oriented design. Test results show that the system achieves real-time face detection speed (100fps) and a high face detection rate (87.2%) for an SVGA (600 x 800) video source. The low power consumption (3.5 W) is another advantage over previous work. (C) 2012 Elsevier B.V. All rights reserved.

关键词： Face detection system field programmable gate array Haar feature

来源：评论

学校读者我要写书评

暂无评论

An area efficient LDPC decoder using a reduced complexity min-sum algorithm

引用

INTEGRATION-THE VLSI JOURNAL 2012年第2期45卷 141-148页

作者： Chandrasetty, Vikram Arkalgud Aziz, Syed Mahfuzul Univ S Australia Sch Elect & Informat Engn Mawson Lakes SA 5095 Australia

Hardware implementation of Low-Density Parity-Check (LDPC) decoders using conventional algorithms such as Sum-Product or Min-Sum requires large amount of hardware resources. A rather simplistic way to reduce hardware resources is to reduce the intrinsic message quantization. However this adversely affects the bit error rate (BER) performance significantly. In this paper, a resource efficient LDPC decoder based on a reduced complexity Min-Sum algorithm is presented. It reduces the inter-connect complexity by restricting the extrinsic message length to 2 bits and also simplifies the check node operation. Simulation at the algorithmic level shows that the proposed decoder achieves BER performance better than that of a 3-bit Min-Sum decoder, and therefore addresses the problem of massive BER performance degradation of a 2-bit Min-Sum decoder. The reduction in algorithmic complexity and further hardware optimization of the variable node leads to significant savings in hardware resources compared to 3-bit Min-Sum. An LDPC decoder with a code length of 1152 bits has been implemented on a Xilinx FPGA using the proposed algorithmic and hardware enhancements. With a 0.1 dB BER performance gain to that of 3-bit Min-Sum decoder, the proposed decoder saves about 18% of FPGA slices and provides a higher throughput. (C) 2011 Elsevier B.V. All rights reserved.

关键词： Digital communication Error correction coding Iterative decoding field programmable gate array Logic design

来源：评论

学校读者我要写书评

暂无评论

Autonomous indoor ultrasonic positioning system based on a low-cost conditioning circuit

引用

MEASUREMENT 2012年第3期45卷 276-283页

作者： Sanchez, Alberto de Castro, Angel Elvira, Santiago Glez-de-Rivera, Guillermo Garrido, Javier Univ Autonoma Madrid HCTLab Madrid Spain

This work presents a low cost 3-D location system based on ultrasonics and implemented with low-cost FPGAs. The mobile nodes of the system use distance estimation to several anchor points in order to trilaterate their positions with an accuracy of few centimeters. The ultrasonic transducers are handled with an ad hoc conditioning circuit based on instrumental amplifiers which provides high amplification keeping low noise. The proposed system is autonomous so there is no need of an external PC or other devices. A prototype of the system has been attached to a mobile robot to check the viability of the location system in a real scenario. (C) 2011 Elsevier Ltd. All rights reserved.

关键词： Location Ultrasonics Instrumental amplifiers Trilateration field programmable gate array Wireless sensor network

来源：评论

学校读者我要写书评

暂无评论

An FPGA implementation of the SMG-SLAM algorithm

引用

MICROPROCESSORS AND MICROSYSTEMS 2012年第3期36卷 190-204页

作者： Mingas, Grigorios Tsardoulias, Emmanouil Petrou, Loukas Aristotle Univ Thessaloniki Fac Engn Dept Elect & Comp Engn Div Elect & Comp Engn GR-54006 Thessaloniki Greece

One of the main tasks of a mobile robot in an unknown environment is to build and update a map of the environment and simultaneously determine its location within this map. This problem is referred to as the simultaneous localization and mapping (SLAM) problem. The article introduces scan-matching genetic SLAM (SMG-SLAM), a novel SLAM algorithm. It is based on a genetic algorithm that uses scan-matching for gene fitness evaluation. The main scope of the article is to present a hardware implementation of SMG-SLAM using an field programmable gate array (FPGA). The architecture of the system is described and it is shown that it is up to 14.83 times faster compared to the software algorithm without significant loss in accuracy. The proposed implementation can be used as part of a larger system, providing efficient SLAM for autonomous robotic applications. (C) 2011 Elsevier B.V. All rights reserved.

关键词： field programmable gate array Simultaneous localization and mapping Genetic algorithm Scan-matching Co-design

来源：评论

学校读者我要写书评

暂无评论

A hardware-software system for coordinated multi-axis control based on a non uniform rational B-splines interpolator applied to industrial computer numerically controlled machines

引用

PROCEEDINGS OF THE INSTITUTION OF MECHANICAL ENGINEERS PART I-JOURNAL OF SYSTEMS AND CONTROL ENGINEERING 2012年第I6期226卷 831-840页

作者： Jaen-Cuellar, Arturo Y. De Santiago-Perez, Jesus J. Romero-Troncoso, Rene J. Morales-Velazquez, Luis Benitez-Rangel, Juan P. Osornio-Rios, Roque A. Univ Autonoma Queretaro HSPdigital Res Grp Col San Cayetano 76807 San Juan Del Ri Mexico

Motion controllers are widely used in many mechatronic applications such as computer numerically controlled machine tools and robots. These applications demand the use of high performance controllers. Some desirable characteristics in motion controllers are coordinated multi-axis control, smooth movements, and advanced interpolation methods. An important manufacturing aspect involves the production of a workpiece in a free form or using the parametric surfaces in modern computer aided design/computer aided manufacturing systems. The use of parametric curves and surfaces has become standard due to their ability to represent objects having complex surfaces with less data. Another mandatory characteristic of motion controllers is the real-time operation. The contribution of the present work is the design and implementation of a hardware-software system for multi-axis motion control featuring non uniform rational B-splines interpolation. Advantages over other reported works are the hardware implementation which allows the application to real computer numerically controlled machines;also the parallel processing permits the incorporation of additional modules to form an integral system without dependence on external devices. Two experiments were carried out in a retrofitted-to-computer numeric control milling machine in order to show the efficiency of the developed system.

关键词： Computer numeric control field programmable gate array non uniform rational B-splines hardware-software motion control computer aided design/computer aided manufacturing

来源：评论

学校读者我要写书评

暂无评论

Floorplanning for High Utilization of Heterogeneous FPGAs

引用

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2012年第9期E95A卷 1529-1537页

作者： Liu, Nan Chen, Song Yoshimura, Takeshi Waseda Univ Grad Sch IPS Kitakyushu Fukuoka 8080135 Japan

Heterogeneous resources such as configurable logic blocks (CLBs), multiplier blocks (MULs) and RAM blocks (RAMs) where millions of logic gates are included have been added to field programmable gate arrays (FPGAs). The fixed-outline floorplanning used by the existing methods always has a big penalty item in the objective function to ensure all the modules are placed in the specified chip region, which maybe greatly degrade the wirelength. This paper presents a three-phase floorplanning method for heterogeneous FPGAs. First, a non-slicing free-outline floorplanning method is used to optimize the wirelength, however, in this phase, the satisfaction of resource requirements from functional modules might fail. Second, a min-cost-max-flow algorithm is used to tune the assignment of CLBs to functional modules, and assign contiguous regions to each module so that all the functional modules satisfy CLB requirements. Finally, the MULs and RAMs are allocated to modules by a network flow model. CLBs hold the maximum quantity among all the resources. Therefore, making a high utilization of them means an enhancement of the FPGA densities. The proposed method can improve the utilization of CLBs, hence, much larger circuits could be mapped to the same FPGA chip. The results show that about 7-85% wirelength reduction is obtained, and CLB utilization is improved by about 25%.

关键词： field programmable gate array floorplanning high utilization

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：