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Low memory visual saliency architecture for data reduction in wireless sensor networks

IET WIRELESS SENSOR SYSTEMS 2012年第2期2卷 115-127页

作者： Ngau, C. W. H. Ang, L. -M. Seng, K. P. Univ Nottingham Dept Elect & Elect Engn Selangor 43500 Malaysia Edith Cowan Univ Sch Engn Joondalup WA 6027 Australia Sunway Univ Fac Sci & Technol Selangor 46150 Malaysia

Traditionally, to reduce communication overheads because of bandwidth limitations in wireless sensor networks (WSNs), image compression techniques are used on high-resolution captures. Higher data reduction rates can be achieved by first removing redundant parts of the capture prior to the application of image compression. To locate these redundant parts, biologically plausible visual saliency processing is used to isolate parts that seemed important based on visual perception. Although visual saliency proves to be an effective method in providing a distinctive difference between important and unimportant regions, computational complexity and memory requirements often impair implementation. This study presents an implementation of a low-memory visual saliency architecture with reduced computation complexity for data reduction in WSNs through salient patch transmission. A custom softcore microprocessor-based hardware implementation on a field programmable gate array is then used to verify the architecture. Real-time processing demonstrated that data reductions of more than 50% are achievable for simple to medium scenes without the application of image compression techniques.

关键词： Computer vision and image processing techniques visual perception data compression Image and video coding field programmable gate array Logic and switching circuits biologically plausible visual saliency processing salient patch transmission Logic circuits image coding Wireless sensor networks Microprocessors and microcomputers data reduction field programmable gate arrays microprocessor chips Microprocessor chips custom softcore microprocessor image compression wireless sensor networks Computational complexity redundant parts computational complexity communication overheads memory visual saliency architecture

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A Low-level rf Control System for a Quarter-wave Resonator

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JOURNAL OF THE KOREAN PHYSICAL SOCIETY 2012年第11期60卷 1953-1956页

作者： Kim, Jongwon Hwang, Churlkew Natl Canc Ctr Dept Biomed Engn Goyang 410769 South Korea Korea Atom Energy Res Inst Dept Nucl Engn Taejon 151742 South Korea

A low-level rf control system was designed and built for an rf deflector, which is a quarter wave resonator, and was designed to deflect a secondary electron beam to measure the bunch length of an ion beam. The deflector has a resonance frequency near 88 MHz, its required phase stability is approximately +/- 1 degrees and its amplitude stability is less than +/- 1%. The control system consists of analog input and output components and a digital system based on a field-programmable gate array for signal processing. The system is cost effective, while meeting the stability requirements. Some basic properties of the control system were measured. Then, the capability of the rf control was tested using a mechanical vibrator made of a dielectric rod attached to an audio speaker system, which could induce regulated perturbations in the electric fields of the resonator. The control system was flexible so that its parameters could be easily configured to compensate for the disturbance induced in the resonator.

关键词： Low-level RF IQ modulator field programmable gate array Rf deflector

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Implementation of a field programmable gate array based transcranial Doppler ultrasound system using pulse compression techniques

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BIOMEDICAL SIGNAL PROCESSING AND CONTROL 2007年第1期2卷 51-58页

作者： Gittins, John Cowe, Joanne Evans, David H. Univ Hosp Leicester Dept Med Phys Leicester LE1 5WW Leics England Univ Leicester Dept Cardiovasc Sci Leicester Leics England

A field programmable gate array (FPGA) based hardware platform that is used to implement a digital, multi-gate pulsed Doppler ultrasound system for transcranial Doppler (TCD) use is described. The Doppler audio signal is extracted from the digitised radio-frequency signal by matched filtering and suitable sampling. The system was configured to acquire Doppler signals from 16 depth locations and to display Doppler signal power versus depth as well as a sonogram from a user specified depth. The signal-to-noise performance of the system was comparable with that of a commercially available TCD unit for equivalent pulse repetition frequency and sample volume settings. The flexibility of the platform was used to demonstrate the feasibility of using coded transducer excitation and pulse compression techniques to improve axial resolution compared to a non-coded implementation. The axial resolution improvement was demonstrated using a flow phantom and measured using a vibrating wire phantom. The measured resolutions were 9.1 and 2.4 mm for the conventional and coded implementations, respectively. The reduction in signal-to-noise ratio of approximately 5 dB associated with the configuration using coded excitation was attributable to the frequency response characteristics of the transducer rather than the processing/technique used. This work demonstrates both the flexibility associated with an FPGA implementation of a Doppler ultrasound system and the potential for coded excitation to improve axial resolution in TCD systems. (c) 2007 Elsevier Ltd. All rights reserved.

关键词： Coded excitation Chirp TCD Axial resolution field programmable gate array

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160-fold acceleration of the Smith-Waterman algorithm using a field programmable gate array (FPGA)

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BMC BIOINFORMATICS 2007年第1期8卷 1-7页

作者： Li, Isaac T. S. Shum, Warren Truong, Kevin Univ Toronto Inst Biomat & Biomed Engn Toronto ON M5S 3G9 Canada Univ Toronto Edward S Rogers Sr Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada

Background: To infer homology and subsequently gene function, the Smith-Waterman (SW) algorithm is used to find the optimal local alignment between two sequences. When searching sequence databases that may contain hundreds of millions of sequences, this algorithm becomes computationally expensive. Results: In this paper, we focused on accelerating the Smith-Waterman algorithm by using FPGA-based hardware that implemented a module for computing the score of a single cell of the SW matrix. Then using a grid of this module, the entire SW matrix was computed at the speed of field propagation through the FPGA circuit. These modifications dramatically accelerated the algorithm's computation time by up to 160 folds compared to a pure software implementation running on the same FPGA with an Altera Nios II softprocessor. Conclusion: This design of FPGA accelerated hardware offers a new promising direction to seeking computation improvement of genomic database searching.

关键词： field programmable gate array Logic Element Custom Instruction Static Random Access Memory Hardware Description Language

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Supporting a Wide Variety of Communication Protocols Using Partial Dynamic Reconfiguration

Supporting a Wide Variety of Communication Protocols Using P...

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IEEE Autotestcon Conference

作者： Dunkley, Richard Common Aircraft Portable Reprogramming Equipment Software Maintenance Grp 309 Hill AFB UT 84056 USA

ISBN: (纸本)9781467306997;9781467307000

supporting a variety of communication protocols for test support equipment has typically required extensive hardware and Input/Output (I/O) interfaces targeting each protocol specifically. Recent advanced designs in the past ten years have created more dynamic approaches by using field programmable gate arrays (FPGAs) and embedded hardware to implement or simulate previous hardware I/O designs. The dynamic possibilities of FPGAs have recently been expanded with the introduction of Dynamic Partial Reconfiguration (DPR), which allows part of the FPGA to be reconfigured while the rest of the logic remains static. This paper evaluates the advantages and disadvantages of using DPR to interface with various communication protocols in test equipment.

关键词： Dynamic Partial Reconfiguration field programmable gate array Communication Protocols Embedded Design Test and Evaluation Framework

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Design of Reconfigurable FIR Filter System Based on FPGA

Design of Reconfigurable FIR Filter System Based on FPGA

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International Conference on Materials Science and Information Technology (MSIT 2011)

作者： Xu Guo-sheng Weifang Univ Informat & Control Engn Coll Weifang 261061 Peoples R China

ISBN: (纸本)9783037853191

In order to improve the real-time and flexible of FIR digital filter, a reconfigurable FIR filter system based on FPGA is designed. According to the filter specialties, the filter coefficients are calculated by the computer. And the configured coefficients of the multistage FIR filter are downloaded to the chip. The filtering computing is completed by the FPGA. The filtered data is transmitted to the computer through the USB2.0 interface for further processing, such as displaying, analyzing and storing. The states conversion between coefficients configuring mode and filtering mode is finished by FSM (Finite State Machine), which ensures the system to work orderly. The experimental results demonstrated that the coefficients configuring of the system is easy, which can adjust the filter coefficients flexibly according to the actual demand, and the filter is effective, that it can effectively filter out the noise signals.

关键词： finite impulse response digital filter reconfigurable coefficient field programmable gate array USB2.0

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Design of the 16-bit ADC Using FPGA

Design of the 16-bit ADC Using FPGA

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International Conference on Electrical Information and Mechatronics (ICEIM)

作者： Sun, JiangFeng Xu, XiuZhen Henan Polytech Univ Comp Sci & Technol Coll Jiaozuo Peoples R China

ISBN: (纸本)9783037853115

There are many kinds of ADC chips which are analog or analog-digital mixed at home and abroad. It can not be integrated into a pure digital chip, in this paper, a way to realize quasi-digital 16- bit ADC based on stochastic logic was given. Except few analog elements, all are digital circuits. The paper describes the design principle and presents the simulation and hardware test results based on FPGA chips produced by Altera show that the shortest conversion time can reach 0.8ms. The hardware test shows that the design is successful.

关键词： field programmable gate array Analog to Digital Converter Randonn Logic programmable Logic Device

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Design of a High-Speed Digital FIR Filter Based on FPGA

Design of a High-Speed Digital FIR Filter Based on FPGA

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International Conference on Materials Science and Information Technology (MSIT 2011)

作者： Xu, Guosheng Weifang Univ Informat & Control Engn Coll Weifang 261061 Peoples R China

ISBN: (纸本)9783037853191

To realize filtering of high-speed input data, and aiming at the design method of systolic FIR digital filter, this paper proposes a design method of high-speed FIR filter based on FPGA. The states conversion between coefficients configuring mode and filtering mode is finished by FSM (Finite State Machine), which ensures the system to work orderly. The experimental results demonstrated, it can reduce the input dimension and eliminate linear and nonlinear interference effectively. In addition, it is very suitable for hardware implementation due to its simple structure.

关键词： finite impulse response digital filter field programmable gate array High-Speed image processing

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The Study Processing based on CCD Scanning and Detecting Device on FPGA

The Study Processing based on CCD Scanning and Detecting Dev...

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International Conference on Materials Science and Information Technology (MSIT 2011)

作者： Li Chang-Ming Xu Guo-Sheng Weifang Univ Informat & Control Engn Coll Weifang 261061 Peoples R China

ISBN: (纸本)9783037853191

To solve the crossing-linkable polyethylene (XLPE) insulation compound purity evaluation problem, a high speed scanning measurement system was designed according to FPGA. With the updated information technology and advanced electronic devices, it is possible to develop a new inspecting technology for sorting, checking and evaluating material quality, by which defects microscopic images can be real-time recorded, processed and displayed. The result shows that this system can measure the size of impurity particles of XLPE cable materials correctly, it also can find out the accurate location and numbers of impurity particles. The resolving power of this method can reach 20 m and the error is less than 10%. The possibility that the impurity particles can be checked out is up to 100%.

关键词： Data processing Defects inspection field programmable gate array Signal processing Charge coupled device

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Transducer Interface Module for Smart Control of DC/DC Converter System

Transducer Interface Module for Smart Control of DC/DC Conve...

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World Congress on Engineering and Computer Science

作者： Umamaheswari, B. Kamala, J. Anna Univ Coll Engn Guindy Elect & Elect Engn Dept Madras 25 Tamil Nadu India Anna Univ Coll Engn Guindy Elect & Commun Engn Dept Madras 25 Tamil Nadu India

ISBN: (纸本)9789881925244

This paper presents an effective use of User Transducer Electronic Data Sheet (TEDS) of IEEE 1451.0-2007 standard in obtaining an integrated architecture for sensing / actuation and control of DC/DC converter module. Modularity is the major advantage of the proposed architecture, which allows application of the proposed concept to any system with new sensors / actuators. Implementation of the proposed integrated Transducer Interface Module (TIM) architecture is achieved in field programmable gate array (FPGA).

关键词： DC/DC Converter field programmable gate array IEEE 1451.0-2007 Standard Smart readout Transducer Electronic Data Sheet (TEDS) Transducer Interface Module (TIM)

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