The purpose of this paper is to analyze and design the controllers of power factor corrector for universal applications. And present its implementation using field programmable gate array. For the controller design, t...
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ISBN:
(纸本)9781467303422
The purpose of this paper is to analyze and design the controllers of power factor corrector for universal applications. And present its implementation using field programmable gate array. For the controller design, the bandwidth of voltage loop as the input voltage changes for PFC with and without input voltage feedforward will be analyzed. It will be shown that for the PFC without input voltage feedforward, the bandwidth of voltage loop varies as the input voltage changes. And the bandwidth of voltage loop for low line input is significantly reduced as it is designed based upon the high line input model. In contrast, the bandwidth of voltage loop of PFC for high line input is increased as it is designed based upon the low line input model. For the PFC with feedforward input voltage, the bandwidth of voltage loop retains constant for both low line and high line inputs and therefore no additional gains are required for universal input applications. This analysis provides a guideline for the design of PFC for universal input applications. Moreover, to fully take the advantages of digital control, an FPGA is used for the realization of digital-controlled PFC for universal input applications. Experimental results derived from an FPGA-based digital-controlled universal PFC are presented to fully support the presented PFC.
Possible scenarios for future manufacturing technologies increase the desirable features of fault tolerance techniques, such as coping with multiple faults and reducing error latency. On the other hand, current high-e...
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ISBN:
(纸本)9780769546995
Possible scenarios for future manufacturing technologies increase the desirable features of fault tolerance techniques, such as coping with multiple faults and reducing error latency. On the other hand, current high-end FPGAs present, besides lookup tables and flip-flops, several dedicated components that perform the most commonly required functions. In this paper, we propose an approach to use such resources to efficiently provide fault detection capabilities. We further extend the technique with placement constraints to enhance the detection of faults affecting the routing resources, which is a critical demand for such devices.
With the advent of the great challenge brought by increasing complexity of modern large circuit, a pressing and necessary problem, that is, improving the routability and timing performance, is proposed in front of us....
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ISBN:
(纸本)9781467324755;9781467324724
With the advent of the great challenge brought by increasing complexity of modern large circuit, a pressing and necessary problem, that is, improving the routability and timing performance, is proposed in front of us. A novel packing algorithm called repack based on enhanced packing attraction function is presented while at the same time an iterative CAD flow tool could provide decreased interconnection resources requirement by applying CLB depopulation at given routing channel width limitation and local congested situations. Experimental results show that, for non-iterative flow, compared to the T-VPack and iRAC, repack can achieve 6.4% and 8.1% improvement respectively in timing performance. However, for iterative flow, when compared to T-VPack, repack has 12.6% and 37.6% improvement in area and routing path width respectively. When compared to iRAC, repack has a 0.9% decrease in area, but it has an improvement of 16.2% in routing path width instead.
In order to improve the precision, speed, integration and reliability of the linear CCD system, A method of data acquisition for high resolution output signal of linear array CCD using FPGA is introduced. The CCD sign...
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ISBN:
(纸本)9783037852866
In order to improve the precision, speed, integration and reliability of the linear CCD system, A method of data acquisition for high resolution output signal of linear array CCD using FPGA is introduced. The CCD signal acquisition circuit with high speed and high sensitivity is designed based on the combination of FPGA with high-speed A/D conversion chipset to gather the signals of high-speed. The experimental results demonstrated that defects within 50 mu m similar to 1000 mu m were inspected effectively by the CCD scanning defects inspection instrument, that this method has a repetition error no more than 2.24 pixels, with high precision and good anti-noise ability.
This paper presents a PCI Express based system dedicated for communication with FPGA in data acquisition systems. The system consisted of FPGA IP core containing PCIE endpoint tightly coupled with with the user core (...
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ISBN:
(纸本)9780819491718
This paper presents a PCI Express based system dedicated for communication with FPGA in data acquisition systems. The system consisted of FPGA IP core containing PCIE endpoint tightly coupled with with the user core (further denoted as "USR core") and the DDR3 memory controller, together with Linux device driver. The Linux OS was running on top of typical x86-64 system.
Radiative transfer modelling of high resolution infrared (or microwave) spectra still represents a major challenge for the processing of atmospheric remote sensing data despite significant advances in the numerical te...
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Radiative transfer modelling of high resolution infrared (or microwave) spectra still represents a major challenge for the processing of atmospheric remote sensing data despite significant advances in the numerical techniques utilized in line-by-line modelling by, e. g., optimized Voigt function algorithms or multigrid approaches. Special purpose computing hardware such as field programmable gate arrays (FPGAs) can be used to cope with the dramatic increase of data quality and quantity. Utilizing a highly optimized implementation of an uniform rational function approximation of the Voigt function, the molecular absorption cross section computation-representing the most compute intensive part of radiative transfer codes-has been realized on FPGA. Design and implementation of the FPGA coprocessor is presented along with first performance tests and an outlook for the ongoing further development.
ERT(electrical resistance tomography) is effective method for visualization of multiphase flows,offering some advantages of rapid response and low cost,so as to explore the transient *** at this target,a fully program...
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ERT(electrical resistance tomography) is effective method for visualization of multiphase flows,offering some advantages of rapid response and low cost,so as to explore the transient *** at this target,a fully programmable and reconfigurable FPGA(field programmable gate array)-based Compact PCI(peripheral component interconnect) bus linked sixteen-channel ERT system has been *** data acquisition system is carefully designed with function modules of signal generator module;Compact PCI transmission module and data processing module(including data sampling,filtering and demodulating).The processing module incorporates a powerful FPGA with Compact PCI bus for communication,and the measurement process management is conducted in *** reconstruction algorithms with different speed and accuracy are also coded for this *** system has been demonstrated in real time(1400 frames per second for 50 kHz excitation) with signal-noise-ratio above 62 dB and repeatability error below 0.7%.Static experiments have been conducted and the images manifested good resolution relative to the actual object *** parallel ERT system has provided alternative experimental platform for the multiphase flow measurements by the dynamic experiments in terms of concentration and velocity.
We present a test methodology for estimating system error rates of field programmable gate arrays (FPGAs) mitigated with Triple Modular Redundancy (TMR). The test methodology is founded in a mathematical model, which ...
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We present a test methodology for estimating system error rates of field programmable gate arrays (FPGAs) mitigated with Triple Modular Redundancy (TMR). The test methodology is founded in a mathematical model, which is also presented. Accelerator data from 90 nm Xilinx Military/Aerospace grade FPGA are shown to fit the model. Fault injection (FI) results are discussed and related to the test data. Design implementation and the corresponding impact of multiple bit upset (MBU) are also discussed.
A novel fuzzy cerebellar-model-articulation-controller (CMAC), which is a generalization of a fuzzy neural-network, is developed in this study. Moreover, this paper proposes a robust adaptive control (RAC) system for ...
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A novel fuzzy cerebellar-model-articulation-controller (CMAC), which is a generalization of a fuzzy neural-network, is developed in this study. Moreover, this paper proposes a robust adaptive control (RAC) system for brushless DC (BLDC) motors using a fuzzy CMAC (FCMAC). The proposed RAC system is composed of an FCMAC and a robust controller. The FCMAC is developed to serve as the main controller and the robust controller is designed to attenuate the effect of the approximation error between the FCMAC and an ideal controller. The developed RAC system is implemented in a field programmable gate array (FPGA) chip to control a BLDC motor in a real-time mode. Using an FPGA to implement an FCMAC for real-time control systems is also a novel approach. For comparison, an adaptive CMAC-based supervisory control, a robust adaptive fuzzy control and the proposed RAC are employed to control a BLDC motor. The experimental results verify that the proposed RAC can achieve better tracking performance than the other control methods.
This paper describes a robust algorithm for haptic-based teleoperation. The robust control algorithm was derived by sliding mode control design approach. Such control assures robustness to the disturbances and model u...
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This paper describes a robust algorithm for haptic-based teleoperation. The robust control algorithm was derived by sliding mode control design approach. Such control assures robustness to the disturbances and model uncertainties. Furthermore, the presented design approach guaranties chattering-free performance. Moreover, it is also easy to implement, since the detailed knowledge of the model is not required. The control has been implemented by FPGA in order to realize high control rate which is strongly required for haptic teleoperation. The control algorithm was validated by the 2-DoF laboratory haptic experimental system with linear motors with built-in Hall sensors; therefore no external sensor is required. The experiments validated the proposed control algorithm regarding the robustness and haptic performance.
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