This paper introduces the first fully digital implementation of 1-D, 2-D and 3-D multiscroll chaos using the sawtooth nonlinearity in a 3rd order ODE with the Euler approximation. Systems indicate chaotic behaviour th...
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(纸本)9781467325264
This paper introduces the first fully digital implementation of 1-D, 2-D and 3-D multiscroll chaos using the sawtooth nonlinearity in a 3rd order ODE with the Euler approximation. Systems indicate chaotic behaviour through phase space boundedness and positive Lyapunov exponent. Low-significance bits form a PRNG and pass all tests in the NIST SP. 800-22 suite without post-processing. Real-time control of the number of scrolls allows distinct output streams with 2-D and 3-D multiscroll chaos enabling greater controllability. The proposed PRNGs are experimentally verified on a Xilinx Virtex 4 FPGA with logic utilization less than 1.25%, throughput up to 5.25 Gbits/s and up to 512 distinct output streams with low cross-correlation.
A novel super resolution time-of-arrival (TOA) estimation technique applicable to multipath wireless channels is proposed. Here, it is assumed that the line-of-sight signal is available. This technique applies the con...
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A novel super resolution time-of-arrival (TOA) estimation technique applicable to multipath wireless channels is proposed. Here, it is assumed that the line-of-sight signal is available. This technique applies the concept of independent component analysis (ICA) to the received signal in the frequency domain. The proposed ICA algorithm solves an optimisation problem for TOA estimation. The selection of a proper cost function for this optimisation is investigated. The objective is to improve the estimation performance in multipath environments. The proposed technique extracts the TOA estimation iteratively. An optimum initialisation constraint is incorporated to detect the desired (shortest) TOA as the first estimated time delay. This reduces the complexity of the proposed approach. Compared with the traditional super-resolution techniques such as MUSIC, this algorithm represents a lower sensitivity to signal-to-noise ratio (SNR) for positive SNRs, and bandwidth. The proposed method is a good candidate for high-resolution TOA estimation in rich scattering wireless environments. It possesses a low complexity implementation over many high-speed fixed-point platforms such as digital signal processor (DSP) and field programmable gate array (FPGA). The proposed technique has applications in radar, sonar, wireless local positioning systems, and, localisation in mobile ad hoc networks.
Most of actual real time simulation platforms have practically about ten microseconds as minimum calculation time step, mainly due to computation limits such as processing speed, architecture adequacy and modeling com...
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Most of actual real time simulation platforms have practically about ten microseconds as minimum calculation time step, mainly due to computation limits such as processing speed, architecture adequacy and modeling complexities. Therefore, simulation of fast switching converters' instantaneous models requires smaller computing time step. The approach presented in this paper proposes an answer to such limited modeling accuracies and computational bandwidth of the currently available digital *** an example, the authors present a low cost, flexible and high performance FPGA-based real-time digital simulator for a complete complex power system with Neutral Point Piloted (NPP) three-level inverter. The proposed real-time simulator can model accurately and efficiently the complete power system, reducing costs, physical space and avoiding any damage to the actual equipment in the case of any dysfunction of the digital controller prototype. The converter model is computed at a small fixed time step as low as 100 ns. Such a computation time step allows high precision account of the gating signals and thus avoids averaging methods and event compensations. Moreover, a novel high performance model of the NPP three-level inverter has also been proposed for FPGA implementation. The proposed FPGA-based simulator models the environment of the NPP converter: the dc link, the RLE load and the digital controller and gating signals. FPGA-based real time simulation results are presented and compared with offline results obtained using PLECS software. They validate the efficiency and accuracy of the modeling for the proposed high performance FPGA-based real-time simulation approach. This paper also introduces new potential FPGA-based applications such as low cost real time simulator for power systems by developing a library of flexible and portable models for power converters, electrical machines and drives. (C) 2010 Elsevier B.V. All rights reserved.
There has been increased interest in the exploration of the Moon in recent years. Pinpoint precision landing is highly desirable for future lunar missions. This paper is concerned with the design of the on-board data ...
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There has been increased interest in the exploration of the Moon in recent years. Pinpoint precision landing is highly desirable for future lunar missions. This paper is concerned with the design of the on-board data handling (OBDH) subsystem for the pinpoint lunar lander of the Magnolia-1 project, funded by NASA. Four proposed on-board data handling architectures are outlined and compared in terms of power consumption, performance and reliability. Implementation results are presented, which are obtained from prototyping of the flight computer for the optimal OBDH architecture option on a Xilinx Virtex-5 field programmable gate array. (C) 2010 Elsevier Ltd. All rights reserved.
This article presents a digital integrated circuit for digital scalar space-vector pulse width modulation in a vector-controlled induction motor drive. All of the blocks, including input stage, calculation, read-only ...
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This article presents a digital integrated circuit for digital scalar space-vector pulse width modulation in a vector-controlled induction motor drive. All of the blocks, including input stage, calculation, read-only memory, sector decide, sector change, triangular estimation, voltage generator, and voltage transformation vector, are realized in a digital scalar space-vector pulse width modulation integrated circuit as a simple, convenient, high-speed, high-integration and low-cost solution. In the proposed digital scalar space-vector pulse width modulation chip, a feedback trigger signal is utilized to mitigate the problem of asynchronicity, and a four-bit fine tuner is employed to alleviate oscillation at low frequency.
We report on the implementation and hardware platform of a real time Statistics-Based Positioning (SBP) method with depth of interaction processing for a positron emission tomography detector. The processing method wo...
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We report on the implementation and hardware platform of a real time Statistics-Based Positioning (SBP) method with depth of interaction processing for a positron emission tomography detector. The processing method works in conjunction with continuous miniature crystal element (cMiCE) detectors using a sensor on the entrance surface design. Our group previously reported on a field programmable gate array (FPGA) SBP implementation that provided a two dimensional (2D) detector positioning solution [1]. This new implementation extends that work to take advantage of three dimensional (3D) look up tables to provide a 3D positioning solution that improves intrinsic spatial resolution. Resolution is most improved along the edges of the crystal, an area where the 2D algorithm's performance suffers. The algorithm allows an intrinsic spatial resolution of similar to 0.90 mm FWHM in X and Y and a resolution of similar to 1.90 mm FWHM in Z (i.e., the depth of the crystal) based upon DETECT2000 simulation results that include the effects of Compton scatter in the crystal. A pipelined FPGA implementation is able to process events in excess of 220 K events per second, which is greater than the maximum expected coincidence rate for an individual detector. In contrast to all detectors being processed at a centralized host (as in the current system) a separate FPGA is available at each detector, thus dividing the computational load. A prototype design has been implemented and tested on an Altera Stratix II FPGA using a reduced word size due to memory limitations of our commercial prototyping board.
A novel rotate-and-fire digital spiking neuron is presented. The digital neuron is a wired system of shift registers and thus it is suited to on-chip learning unlike many other analog spiking neuron models. By adjusti...
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A novel rotate-and-fire digital spiking neuron is presented. The digital neuron is a wired system of shift registers and thus it is suited to on-chip learning unlike many other analog spiking neuron models. By adjusting the wiring pattern among the registers, the digital neuron can generate spike trains with various spike patterns and can exhibit related bifurcations. A discrete-continuous hybrid map, which describes the neuron dynamics without any approximation, is derived analytically. Using the hybrid map, it is shown that the digital spiking neuron can mimic typical bifurcation phenomena and various nonlinear responses of biological neurons.
A field programmable gate array (FPGA) implementation of a highly configurable complex divider is presented, based on an iterative gradient algorithm. The proposed architecture allows to configure both the accuracy an...
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A field programmable gate array (FPGA) implementation of a highly configurable complex divider is presented, based on an iterative gradient algorithm. The proposed architecture allows to configure both the accuracy and the throughput of the division operation, which makes it suitable for diverse applications with different requirements. Results show how various throughputs can be achieved under different maximum error and iteration limit configurations. Besides, the resource occupation is considerably small, compared with previous solutions.
In this study, the authors discuss the implementation of a low latency decoding algorithm for turbo codes and repeat accumulate codes and compare the implementation results in terms of maximum available clock speed, r...
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In this study, the authors discuss the implementation of a low latency decoding algorithm for turbo codes and repeat accumulate codes and compare the implementation results in terms of maximum available clock speed, resource consumption, error correction performance and the data (information bit) rate. In order to decrease the latency a parallellised decoder structure is introduced for these mentioned codes and the results are obtained by implementing the decoders on a field programmable gate array. The memory collision problem is avoided by using collision-free interleavers. Through a proposed quantisation scheme and normalisation in forward/backward recursions, computational issues are handled for overcoming the overflow and underflow issues in a fixed point arithmetic. Also, the effect of different implementation styles are observed.
Multilevel inverter is used in applications that need high voltage and high current. The topologies of multilevel inverter have several advantages such as lower total harmonic distortion (THD), lower electro magnetic ...
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Multilevel inverter is used in applications that need high voltage and high current. The topologies of multilevel inverter have several advantages such as lower total harmonic distortion (THD), lower electro magnetic interference (EMI) generation, high output voltage. The main feature of multilevel inverter is the ability to reduce the voltage stress on each power device due to the utilisation of multilevel on the DC bus. The advent of multilevel inverter topologies has caused variety of pulse width modulation strategies. In this paper, various carrier pulse width modulation techniques are proposed, which can minimise the total harmonic distortion and enhances the output voltages from five level inverter. Three methodologies adopting the constant switching frequency (CSF), variable switching frequency (VSF), and phase shifted pulse width modulation (PSPWM) concepts are proposed in this paper. The above methodologies divided into two techniques like subharmonic pulse width modulation which minimises total harmonic distortion and switching frequency optimal pulse width modulation which enhances the output voltages. field programmable gate array (FPGA) has been chosen to implement the pulse width modulation due its fast proto typing, simple hardware and software design. The simulation and experimental results are presented.
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