Modern embedded systems are rapidly becoming a driving factor of the explosive growth of e-industry due to their increasingly sophisticated functionalities and complex features. At the same time, the advances of micro...
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Modern embedded systems are rapidly becoming a driving factor of the explosive growth of e-industry due to their increasingly sophisticated functionalities and complex features. At the same time, the advances of microelectronics and semiconductor technologies have enabled to increase the capacity-level integration of digital circuits like field programmable gate array (FPGA). The design of their systems is based on the challenge of increasing their performance by an abstraction of their implementation details to manage complexity. Designers need a more direct path between the specification and implementation. Different approaches to high-level synthesis design methodologies are currently used for high description language code generation. This paper examining a case study of the model-based design (MBD) approach using Xilinx System Generator, validated on two control drive applications such as direct current motor and alternative current motor. Results indicate that MBD approach enables designers to implement advanced algorithm including complex computing with good data precision and limited FPGA resources.
Sequential Monte Carlo particle filters (PFs) are useful for estimating nonlinear non-Gaussian dynamic system parameters. As these algorithms are recursive, their real-time implementation can be computationally comple...
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Sequential Monte Carlo particle filters (PFs) are useful for estimating nonlinear non-Gaussian dynamic system parameters. As these algorithms are recursive, their real-time implementation can be computationally complex. In this paper, we analyze the bottlenecks in existing parallel PF algorithms, and propose a new approach that integrates parallel PFs with independent Metropolis-Hastings (PPF-IMH) resampling algorithms to improve root mean-squared estimation error (RMSE) performance. We implement the new PPF-IMH algorithm on a Xilinx Virtex-5 field programmable gate array (FPGA) platform. For a one-dimensional problem with 1,000 particles, the PPF-IMH architecture with four processing elements uses less than 5% of a Virtex-5 FPGA's resource and takes 5.85 mu s for one iteration. We also incorporate waveform-agile tracking techniques into the PPF-IMH algorithm. We demonstrate a significant performance improvement when the waveform is adaptively designed at each time step with 6.84 mu s FPGA processing time per iteration.
Visual sensor networks (VSNs) have emerged as a new paradigm by giving sensors the capability to perceive and analyze their surroundings. Robust and fault-tolerant operations are crucial for non-contact plant monitori...
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Visual sensor networks (VSNs) have emerged as a new paradigm by giving sensors the capability to perceive and analyze their surroundings. Robust and fault-tolerant operations are crucial for non-contact plant monitoring systems in a greenhouse environment equipped with a VSN. Achieving such capabilities requires new methods to monitor system status and crop health, and automatically reconfigure for new functionalities due to dynamic changes in the greenhouse environment. New technologies, such as field-programmablegatearrays (FPGAs), provide hardware designers with the ability to create high-performance and adaptive solutions. In this study, a distributed wireless sensor architecture with self-recovery capability was designed and constructed. The experimental results showed that the test bed comprised of wirelessly connected FPGAs (Xilinx Virtex 5) was able to achieve node-level fault detection and recovery within 2.16 s and network level recovery in 5.39 s. The application of the proposed architecture in greenhouse-based plant production is a significant step toward building a robust system for monitoring plant status.
Although a programmable logic controller (PLC) has been widely adopted for the sequence control of industrial machinery, its performance does not always satisfy the recent requirements in large and highly responsive s...
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Although a programmable logic controller (PLC) has been widely adopted for the sequence control of industrial machinery, its performance does not always satisfy the recent requirements in large and highly responsive systems. With the state-of-the-art field programmable gate array (FPGA) technology, it is possible to implement a control program with hard-wired logic for higher response and reduced implementation cost/space. This approach is also worthwhile for transmigration of legacy PLC software into forthcoming FPGA-based control hardware. This study presents a systematic method to implement a hard-wired sequence control from PLC software. PLC instructions are converted into VHDL codes, and then implemented as logic circuit with various peripheral functions. Productive PLC programs were examined with Mitsubishi Electric FX2N PLC and Altera Stratix II FPGA, and were shown to fit into a common FPGA chip. A straightforward Sequential design was estimated to be 184 times faster than PLC, while a performance-oriented Flat design was estimated to be 44 times faster than Sequential design (i.e., 8050 times faster than PLC). A practical perfect layer winder system was actually built and successfully operated with our FPGA control board, whose logic design was implemented with our tools. (C) 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.
A linear heating system has been developed using field programmable gate array (FPGA) for the measurement of thermoluminescence (TL) in alkali halides and other related compounds. Thermoluminescence plays an essential...
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A linear heating system has been developed using field programmable gate array (FPGA) for the measurement of thermoluminescence (TL) in alkali halides and other related compounds. Thermoluminescence plays an essential part in radiation dosimetry. This system measures the temperature and the amount of light emitted by the sample for TL studies. This work proposed an architectural framework, verilog HDL code for protocols for reading temperature from Thermocouple through ADC, processing of data (amount of light energy) in FPGA, sending control signal to the heater and displaying the temperature in LCD. This work shows performance improvement 3 times in comparison with conventional embedded system. The power consumption is also comparatively lower.
Bit-stream is a new technique for controlling power electronics applications by interconnecting appropriate control elements inside an field programmable gate array (FPGA). This paper presents a bit-stream-based phase...
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Bit-stream is a new technique for controlling power electronics applications by interconnecting appropriate control elements inside an field programmable gate array (FPGA). This paper presents a bit-stream-based phase locked loop (PLL), which is essential for the implementation of sophisticated power electronics control systems using bit-streams. The proposed PLL consists of a phase detector, loop filter and numerically controlled oscillator, each of which is designed using standard analogue methods and converted to equivalent bit-stream elements. The bit-stream-based PLL is modelled using Matlab/Simulink and Model Sim, and results show that the PLL successfully locks onto a 50 Hz three-phase voltage source. Experimental results of a prototype, constructed using an Altera Cyclone II FPGA and controlled using a bit-stream-based PLL, are presented and compared to a similar, microprocessor-based, PLL to demonstrate that the bit-stream-based PLL successfully locks onto the line voltage waveform. The practical viability of the proposed bit-stream PLL is investigated using a prototype three-phase, 3 kW, controlled rectifier. The experimental implementation of the PLL requires approximately 350 logic elements.
The new Editor in Chief of IEEE Micro introduces himself and the first issue of 2011. He thanks the outgoing Editor in Chief, David Albonesi, for his outstanding work during his tenure. He discusses developments to th...
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The new Editor in Chief of IEEE Micro introduces himself and the first issue of 2011. He thanks the outgoing Editor in Chief, David Albonesi, for his outstanding work during his tenure. He discusses developments to the magazine and future issues, and asks readers for their suggestions on topics the magazine should cover in coming issues.
The purpose of this paper is to analyze and design the controllers of power factor corrector for universal applications. And present its implementation using field programmable gate array. For the controller design, t...
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ISBN:
(纸本)9781467303408;9781467303422
The purpose of this paper is to analyze and design the controllers of power factor corrector for universal applications. And present its implementation using field programmable gate array. For the controller design, the bandwidth of voltage loop as the input voltage changes for PFC with and without input voltage feedforward will be analyzed. It will be shown that for the PFC without input voltage feedforward, the bandwidth of voltage loop varies as the input voltage changes. And the bandwidth of voltage loop for low line input is significantly reduced as it is designed based upon the high line input model. In contrast, the bandwidth of voltage loop of PFC for high line input is increased as it is designed based upon the low line input model. For the PFC with feedforward input voltage, the bandwidth of voltage loop retains constant for both low line and high line inputs and therefore no additional gains are required for universal input applications. This analysis provides a guideline for the design of PFC for universal input applications. Moreover, to fully take the advantages of digital control, an FPGA is used for the realization of digital-controlled PFC for universal input applications. Experimental results derived from an FPGA-based digital-controlled universal PFC are presented to fully support the presented PFC.
A new versatile and modular hardware platform for distributed real-time simulation is presented in this paper. The system is aimed at large-scale simulation on system level but with the ability to include simulation o...
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ISBN:
(纸本)9781467319706
A new versatile and modular hardware platform for distributed real-time simulation is presented in this paper. The system is aimed at large-scale simulation on system level but with the ability to include simulation of switched power electronics for hardware-in-the-loop components connected to single nodes of the simulated system. High complexity is possible through parallelization on the system level to account for large numbers of simulated components. Low time-steps are possible through parallelization on chip-level to offer parallel computation aided by field-programmablegatearray devices. Processor boards handle the simulation of subcomponents and are interconnected to build the large-scale systems. Hardware-in-the-loop connection is provided in a flexible yet powerful way by dedicated interface boards connected to a controlling processor board. A backplane with active routing capability is used to handle low-latency communication throughout the simulation platform. A small-scale system simulating an example buck converter with a time-step of 1 μs is presented to show the functionality of the simulation platform.
In this work, a low-noise, high-dynamic time-domain EMI measurement system that allows for measurements from 9 kHz - 26 GHz is presented. It combines ultra-fast analog-to-digital-conversion and real-time digital signa...
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ISBN:
(纸本)9781457708121
In this work, a low-noise, high-dynamic time-domain EMI measurement system that allows for measurements from 9 kHz - 26 GHz is presented. It combines ultra-fast analog-to-digital-conversion and real-time digital signal processing on a field-programmable-gate-array (FPGA) with ultra-broadband multi-stage down-conversion. The system IF dynamic range is shown to exceed the requirements of CISPR 16-1-1 by over 20 dB and allows for the measurement of high-dynamic range signals like radar pulses. The system sensitivity is increased by the use of low-loss components and integrated, broadband low-noise amplifiers (LNA). This yields an ultra-low noise floor power spectral density of typically below -150 dBm/Hz over the complete frequency range. The high system sensitivity allows for the characterization of broadband, low-level signals near the noise floor, like ultra-wideband (UWB) communication. Scan time is decreased by several orders of magnitude compared to heterodyne EMI receivers. A scan from 9 kHz to 26 GHz with a 9 kHz IF filter and a dwell-time of 100 ms is completed in under 200 s, while over 5.10(6) frequency points are calculated.
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