Discrete wavelet transform (DWT) has shown great performance in digital image compression and denoising applications. It is the transformation used for source encoding in JPEG2000 still image compression standard and ...
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ISBN:
(纸本)9781467311564
Discrete wavelet transform (DWT) has shown great performance in digital image compression and denoising applications. It is the transformation used for source encoding in JPEG2000 still image compression standard and FBI wavelet scalar quantization. DWT is capable of fast image compression at less area and low power consumption. This paper presents 4-tap orthogonal DWT based on the residue number system. Hardware complexity reduction and design improvement are achieved by employing RNS for arithmetic operations and LUT sharing between low pass and high pass filters. The RNS based DWT is simulated and implemented on the Xilinx FPGA to verify the functionality and efficiency of the design.
A gradient pulse generator for magnetic resonance imaging is presented. It has the ability to yield arbitrary gradient pulses on the fly and provide reconfigurable calculations including scaling, axis rotation, pre-em...
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A gradient pulse generator for magnetic resonance imaging is presented. It has the ability to yield arbitrary gradient pulses on the fly and provide reconfigurable calculations including scaling, axis rotation, pre-emphasis, and gradient offsetting in real time along X, Y, and Z gradient channels. The versatility has been obtained by incorporating all required digital functions into a single field programmable gate array chip. The development of the hardware is eased by employing a high-level tool-the System Generator-using the MathWorks model-based Simulink environment. In addition, an easy-to-use method is developed for pre-emphasis calibration. As expected, the described device is highly integrated, low cost, simple to use and interface, and has been demonstrated successfully in conjunction with a home-built magnetic resonance system to perform imaging experiments. (C) 2011 Wiley Periodicals, Inc. Concepts Magn Reson Part B ( Magn Reson Engineering) 39B: 59-63, 2011
This paper describes digital circuit which produce sigma-delta modulated sine waveform. The circuit should be used for measurements, calibrations and reference purposes. The sine waveform is generated using a novel al...
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ISBN:
(纸本)9781457714115
This paper describes digital circuit which produce sigma-delta modulated sine waveform. The circuit should be used for measurements, calibrations and reference purposes. The sine waveform is generated using a novel algorithm which results from simple method used to generate sine signal in analogue circuits. The circuit is designed as fully digital and described in VHDL language. The structure of the circuit was implemented and tested in an FPGA chip. Presently the design is being transferred into ASIC utilizing AMIS CMOS 07 technology. After fabrication and testing, some changes and improvements will be done to expand functions and utilization of the generator.
A novel technique for constructing a multi-level Hierarchical Quasi-Cyclic (HQC) matrix for Low-Density Parity-Check (LDPC) decoder is presented in this paper. A unique multilevel structure of the proposed matrix prov...
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ISBN:
(纸本)9781612843490
A novel technique for constructing a multi-level Hierarchical Quasi-Cyclic (HQC) matrix for Low-Density Parity-Check (LDPC) decoder is presented in this paper. A unique multilevel structure of the proposed matrix provides flexibility in generating different code lengths and code rates for various applications such as WiMax, WLAN and DVB-S2. In addition, different combinations of permuted random sub-matrices are embedded in layers, to provide virtual randomness in the LDPC matrix. Simulation results show that the HQC matrices generated by using the proposed technique has bit error rate (BER) performance very close to that of unstructured random matrices. A prototype model of partially-parallel decoder architecture has been designed by using the various matrix configurations available in the proposed technique. FPGA design results show that the proposed decoder is resource efficient and the power requirements are comparable to that of ASIC based decoders.
The present-day research on direct digital frequency synthesizer (DDFS) lays emphasis on ROM-less architecture, which is endowed with high speed, low power and high spurious free dynamic range (SFDR) features. The DDF...
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ISBN:
(纸本)9783642178801
The present-day research on direct digital frequency synthesizer (DDFS) lays emphasis on ROM-less architecture, which is endowed with high speed, low power and high spurious free dynamic range (SFDR) features. The DDFS has a wide application in signal processing and telecommunication area, which generates the sine or cosine waveforms within a broad frequency range. In this paper, one high-speed, low-power, and low-latency pipelined ROM-less DDFS architecture has been proposed, implemented and tested using Xilinx Virtex-II Pro University FPGA board. The proposed ROM-less DDFS design has 32 bit phase input and 16 bit amplitude resolution with a maximum amplitude error of 1.5x10(-4). FPGA implementation of the proposed design has exhibited an SFDR of -94.3 dBc and a maximum operating frequency of 276 MHz while consuming only 22 K gates and 1.05 mW/MHz power. The high speed of operation and the low power make the proposed design suitable for use in communication transceiver for up and down conversion.
A new generation fault processor is in development which is intended to increase fault handling flexibility and reduce the number of incomplete DIII-D shots due to gyrotron faults. The processor, which is based upon a...
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A new generation fault processor is in development which is intended to increase fault handling flexibility and reduce the number of incomplete DIII-D shots due to gyrotron faults. The processor, which is based upon a field programmable gate array device, will analyze signals for aberrant operation and ramp down high voltage to try to avoid hard faults. The processor will then attempt to ramp back up to an attainable operating point. The new generation fault processor will be developed during an expansion of the electron cyclotron heating (ECH) areas that will include the installation of a depressed collector gyrotron and associated equipment. Existing systems will also be upgraded. Testing of real-time control of the ECH launcher poloidal drives by the DIII-D plasma control system will be completed. The ECH control system software will be upgraded for increased scalability and to increase operator productivity. Resources permitting, all systems will receive an extra layer of interlocks for the filament and magnet power supplies, added shielding for the tank electronics, programmable filament boost shape for long pulses, and electronics upgrades for the installation of the advanced fault processor. (C) 2011 Elsevier B.V. All rights reserved.
Real-time simulation is proving very useful in simulating complex and expensive systems using the high performance multi-processors. It has many applications in the area of testing of controllers and protection system...
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ISBN:
(纸本)9781457711091
Real-time simulation is proving very useful in simulating complex and expensive systems using the high performance multi-processors. It has many applications in the area of testing of controllers and protection systems under real-field like situations. In this project, an effort has been made to prepare a low-cost system to carry out real-time simulation in an educational laboratory setting. The system is useful in explaining and demonstration of the dynamics and control of complex real-life systems that cannot be set up in an academic institute in any practical way. Examples of such systems include complex electric power systems, wind mills, automobiles and locomotives. The simulation system implements the system model, and its control system, in real-time. The generalized software for real-time simulation has been developed in assembly language. The testing and validation of the software and hardware tools has been accomplished.
For high-frequency radar, ship targets detection is seriously affected by the strong sea clutter. To solve the problem, a design of multi-frequency radar receiver system is presented, which completes digital mixer and...
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ISBN:
(纸本)9781424462520
For high-frequency radar, ship targets detection is seriously affected by the strong sea clutter. To solve the problem, a design of multi-frequency radar receiver system is presented, which completes digital mixer and digital down converter for multi-channel digital receivers based on FPGA and carries out system controls and data transmission by USB2.0 interface. The system closed-loop test shows that the scheme can work in multi-frequency mode which meets the requirements of HF radar application.
A field programmable gate array (FPGA) based digital coincidence system has been developed to use with Nal scintillators for field applications. The analog output signal from the photomultiplier anode is directly tran...
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A field programmable gate array (FPGA) based digital coincidence system has been developed to use with Nal scintillators for field applications. The analog output signal from the photomultiplier anode is directly transferred into digital signals by pulse height for pulse width conversion. The digital signal contains the energy and timing information of the radiation events. The pulse width is then measured by a vernier type of time-to-digital converter (TDC). The timing information of radiation events is recorded and analyzed by a coincidence unit. Both the TDC unit and the coincidence unit are implemented using a commercial available FPGA board. The measured data is then sent to a personal computer for spectrum display. Efficiency as well as energy calibration has been performed. The system showed a timing resolution about 13 ns and an energy resolution of 12% for 0.511 MeV annihilation gammas;it also successfully demonstrated the background rejection ability through coincidence measurement. (C) 2011 Elsevier B.V. All rights reserved.
It has been shown that FPGAs could outperform high-end microprocessors even on floating-point computations, thanks to massive parallelism. Too often, however, such studies re-implement in the FPGA the operators presen...
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ISBN:
(纸本)9780769543185
It has been shown that FPGAs could outperform high-end microprocessors even on floating-point computations, thanks to massive parallelism. Too often, however, such studies re-implement in the FPGA the operators present in a processor. An FPGA can do much better: it can accomodate hardware operators that would make no economical sense in a general-purpose processor, and it can taylor them just right to the needs of the application. This talk tries to survey this idea systematically, discussing its potential, exhibiting some exotic (but useful) operators developed in the FloPoCo project, and listing some of the challenges ahead.
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