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检索条件"主题词=Field Programmable Gate array"

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Programming Safety Requirements in the REFLECT Design Flow

Programming Safety Requirements in the REFLECT Design Flow

引用

9th IEEE International Conference on Industrial Informatics (INDIN)

作者： Petrov, Zlatko Kratky, Kamil Cardoso, Joao M. P. Diniz, Pedro C. Honeywell International s.r.o. Czech Republic

ISBN: (纸本)9781457704345

The common approach to include non-functional requirements in tool chains for hardware/software embedded systems requires developers to manually change the software code and/or the hardware, in an error-prone and tedious process. In the REFLECT research project we explore a novel approach where safety requirements are described using an aspect-and strategy-oriented programming language, named LARA, currently under development. The approach considers that the weavers in the tool chain use those safety requirements specified as aspects and strategies to produce final implementations according to specific design patterns. This paper presents our approach including LARA-based examples using an avionics application targeting the FPGA-based embedded systems consisting of a general purpose processor (GPP) coupled to custom computing units.

关键词： FPGA-based embedded systems Fault tolerant systems Hardware LARA programming language REFLECT design flow Redundancy Safety Software Weaving aerospace computing aspect-oriented programming aspect-oriented programming language avionics avionics application custom computing unit embedded systems field programmable gate array field programmable gate arrays general purpose processor hardware-software embedded systems multiprocessing systems programming languages rendering FPGA to multicore embedded computing safety requirement programming safety-critical software software code strategy-oriented programming language

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Evolutionary hardware design

Evolutionary hardware design

引用

Conference on VLSI Circuits and Systems V

作者： Sekanina, Lukas Brno Univ Technol Fac Informat Technol Brno 61266 Czech Republic

ISBN: (纸本)9780819486561

Since the early 1990's researchers have begun to apply evolutionary algorithms to synthesize electronic circuits. Nowadays it is evident that the evolutionary design approach can automatically create efficient electronic circuits in many domains. This paper surveys fundamental concepts of evolutionary hardware design. It introduces relevant search algorithms such as Cartesian genetic programming (CGP). Several case studies are presented demonstrating strength and weakness of the method. Target domains are combinational circuit synthesis where the goal is to minimize the number of gates, image filter design intended for field programmable gate arrays (FPGAs) where the goal is to obtain the quality of filtering of conventional methods for a significantly lower cost on a chip and evolution of benchmark circuits for evaluation of testability analysis methods. Evolved circuits are compared with the best-known conventional designs. FPGAs are presented as accelerators for evolutionary circuit design and circuit adaptation.

关键词： evolvable hardware genetic programming field programmable gate array logic design image filter

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Development of a built-in Analog-to-Digital Converter for a X-ray Astronomy Detector with the SOI CMOS Technology

Development of a built-in Analog-to-Digital Converter for a ...

引用

IEEE Nuclear Science Symposium/Medical Imaging Conference (NSS/MIC)/18th International Workshop on Room-Temperature Semiconductor X-Ray and Gamma-Ray Detectors

作者： Nakashima, Shinya Ryu, Syukyo G. Tsuru, Takeshi G. Arai, Yasuo Takeda, Ayaki Nakajima, Hiroshi Tsunemi, Hiroshi Doty, John P. Imamura, Toshifumi Ohmoto, Takafumi Maeda, Tomoaki Iwata, Atsushi Kyoto Univ Grad Sch Sci Dept Phys Sakyo Ku Kitashirakawa Oiwake Cho Kyoto 6068502 Japan High Energy Accelerator Org KEK 1-1 Oho Tsukuba Ibaraki 3050801 Japan Osaka Univ Grad Sch Sci Dept Earth & Space Sci Osaka 5600043 Japan Noqsi Aerosp Ltd Colorado Springs CO 80470 USA AR Tec Corp Hiroshima 7390046 Japan

ISBN: (纸本)9781467301206

We have been developing a novel X-ray astronomy detector combined with a CMOS readout circuit on a monolithic chip using the SOI CMOS technology. As a part of the development, we have fabricated a prototype of an analog-to-digital converter (ADC) component aiming for building it into the detector itself. We used the OKI 0.2 mu m CMOS fully depleted Silicon-On-Insulator process. The prototype ADC consists of a pre-amplifier and two delta-sigma (Delta Sigma) modulators. The two modulators process a series of analog input signal alternately to improve the readout speed (similar to 100 kHz), and output the digital bit-stream signal. An external field programmable gate array works as a decimation filter and converts the bit-stream signal into a 12-bit digital signal. We evaluated the prototype ADC and obtained the first results as follows: the power consumption of 40 mW, the equivalent input noise of similar to 80 mu V rms, and the integral non-linearity of less than 0.8%.

关键词： CMOS integrated circuits CMOS integrated circuits CMOS readout circuit Digital filters Ear MONOS devices Modulation Optical filters Physics SOI CMOS technology X-ray astronomy X-ray astronomy detector X-ray detection analog input signal analog-to-digital converter analogue-digital conversion bit-stream signal decimation filter delta-sigma modulation delta-sigma modulator digital bit-stream signal digital signal digital signals field programmable gate array field programmable gate arrays high energy physics instrumentation computing monolithic chip nuclear electronics power consumption power consumption preamplifier preamplifiers readout electronics readout speed silicon radiation detectors silicon-on-insulator silicon-on-insulator process

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Behavioral Model of TRNG Based on Oscillator Rings Implemented in FPGA

Behavioral Model of TRNG Based on Oscillator Rings Implement...

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14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)

作者： Wold, Knut Petrovic, Slobodan Gjovik Univ Coll Dept Comp Sci & Media Technol NISlab Gjovik Norway

ISBN: (纸本)9781424497560

Understanding the behavior of a true random number generator (TRNG) is important in order to determine the security of such a design. In this paper, an investigation of a TRNG design based on several oscillator rings implemented in a field programmable gate array (FPGA) is performed in order to determine the amount of true randomness or entropy in this design. A model of the TRNG based on the number of hits in the transition regions generating entropy is proposed. This model takes into account the fact that the jitter of an oscillator ring is not constant, but increases or accumulates if the ring is not sampled in a region close to a transition point where the oscillator ring output changes from logic 0 to logic 1 or vice versa. The model of the TRNG is implemented in MatLab and simulations are performed showing the influence of different design parameters and also the influence of properties of the FPGA device on quality of randomness.

关键词： Dispersion Entropy FPGA field programmable gate arrays Inverters Jitter MatLab Mathematical model Oscillators behavioral model cryptography entropy entropy field programmable gate array field programmable gate arrays jitter jitter oscillator ring oscillators random number generation security true random number generator design

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Reconfigurable MPSoC versus GPU: Performance, Power and Energy Evaluation

Reconfigurable MPSoC versus GPU: Performance, Power and Ener...

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9th IEEE International Conference on Industrial Informatics (INDIN)

作者： Goehringer, Diana Birk, Matthias Dasse-Tiyo, Yves Ruiter, Nicole Huebner, Michael Becker, Juergen Fraunhofer IOSB Ettlingen Germany Karlsruhe Inst Technol Karlsruhe Germany

ISBN: (纸本)9781457704345

Different characteristics of algorithms, perform better or worse on various target hardware. The consequent of this is, that the selection of one suitable hardware, such as Graphic Processing Units (GPU), field programmable gate arrays (FPGAs) or traditional processor cores is a challenging task for developers. The challenge is to choose the most suitable platform satisfying the requirements of the given application, such as real-time and power- / energy consumption constraints. Due to short time to market pressure, a fast development cycle is also a very important characteristic in industrial applications. This work evaluates the performance, power- / energy consumption and the development effort for three processor-based systems: an FPGA-based multiprocessor platform called RAMPSoC, a GPU and a CPU. Two real-world applications have been selected for this evaluation: 3D Ultrasound Computer Tomography and Object Recognition. The paper presents the realization of the applications on the different target hardware and discusses the results of the power and performance evaluation.

关键词： 3D ultrasound computer tomography CPU FPGA-based multiprocessor platform field programmable gate arrays Finite impulse response filter GPU Graphics processing unit Hardware Instruction sets Kernel Object recognition RAMPSoC computer graphic equipment computerised tomography coprocessors development cycle energy consumption constraint field programmable gate array field programmable gate arrays graphic processing units multiprocessing systems object recognition object recognition performance evaluation power consumption constraint processor core processor-based system real-time constraint reconfigurable MPSoC reconfigurable architectures system-on-chip ultrasonic imaging

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INSTRUCTION SET CUSTOMIZATION FOR AREA-CONSTRAINED FPGA DESIGNS

INSTRUCTION SET CUSTOMIZATION FOR AREA-CONSTRAINED FPGA DESI...

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24th IEEE International System-on-Chip Conference (SOCC)

作者： Prakash, Alok Lam, Siew-Kei Clarke, Christopher T. Srikanthan, Thambipillai Nanyang Technol Univ Sch Comp Engn Singapore Singapore Univ Bath Dept Elect & Elect Engn Bath Avon England

ISBN: (纸本)9781457716171

Custom instructions are commonly used to meet the strict design constraints in high performance systems. This paper extends the application space of our previously proposed FPGA-aware custom instruction enumeration and selection technique for area-constrained designs that maximizes the logic utilization of the available FPGA space. Results indicate a factor of 4 improvement in cycle savings over conventional selection techniques and an average runtime reduction of over 31% and 50% in the enumeration and selection phases respectively.

关键词： FPGA-aware custom instruction enumeration FPGA-aware selection technique field programmable gate arrays Runtime area-constrained FPGA design enumeration phase field programmable gate array field programmable gate arrays instruction set customization instr

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Radiation Characterization of Microsemi ProASIC3 Flash FPGA Family

Radiation Characterization of Microsemi ProASIC3 Flash FPGA ...

引用

IEEE Radiation Effects Data Workshop (REDW)/48th IEEE International Nuclear and Space Radiation Effects Conference (NSREC)

作者： Poivey, C. Grandjean, M. Guerre, F. X. ESA ESTEC Noordwijk Netherlands HIREX Engn Ramonville St Agne France

We present radiation data, Heavy ion and proton induced Single Event Effects (SEE) and Total Ionizing Dose (TID), on the Microsemi ProASIC3 Flash field programmable gate array (FPGA) A3PE3000L. These tests have been p... 详细信息

ISBN: (纸本)9781457712838

关键词： Clocks Degradation Flip-flops Inverters Phase locked loops Radiation effects Random access memory application specific integrated circuits field programmable gate array field programmable gate arrays microsemi ProASIC3 flash FPGA family radiation characte

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Hecto-Scale Frame Rate Face Detection System for SVGA Source on FPGA Board

Hecto-Scale Frame Rate Face Detection System for SVGA Source...

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IEEE 19th Annual International Symposium on field-programmable Custom Computing Machines (FCCM)

作者： Ding, Zheng Zhao, Feng Wang, Tinghui Shu, Wei Wu, Min-You Shanghai Jiao Tong Univ Dept Comp Sci & Engn Shanghai 200030 Peoples R China Digilent Elect Technol Co Ltd Shanghai Peoples R China Univ New Mexico Dept Elect & Comp Engn Albuquerque NM 87131 USA

ISBN: (纸本)9780769543017

This paper proposes techniques for face detection and gives the implementation details for an FPGA development board. We analyze and discuss the relation between the system computation cost and selection of the image scaling factor. We give a new method to select the stop threshold for the image reduction process, which reduces the total computation by half. We also provide a color image output mode to let our system enjoy more human-oriented design. Test results show that the system achieves real-time face detection speed (100fps) and a high face detection rate (87.2%) for an SVGA (600 x 800) video source. The low power consumption (3.5W) is another advantage over previous work.

关键词： Face Detection System field programmable gate array Haar Feature

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DENSE STEREO DISPARITY MAPS BY DYNAMIC TIME WARP WITH SPARSE FEATURES AND FPGA ACCELERATION

DENSE STEREO DISPARITY MAPS BY DYNAMIC TIME WARP WITH SPARSE...

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24th Canadian Conference on Electrical and Computer Engineering (CCECE)

作者： Qian, Zheng Takaya, Kunio Univ Saskatchewan Saskatoon SK S7N 5A9 Canada

ISBN: (纸本)9781424497898

Dense stereo disparity map provides a robust method on distance measurements in a 3D scene. Due to its computational complexity in nature, it has been a challenge to achieve real-time processing. In the past years, various algorithms have been studied in order to reach the goal of real-time processing. In this paper, a Dynamic Time Warp (DTW) algorithm is proposed. The DTW algorithm provides excellent results of dense stereo disparity maps in accuracy. Furthermore, an improvement on the DTW algorithm, which is the DTW with coarse quantization, is suggested to reduce the computational expense so as to meet the requirement of real-time processing. A hardware acceleration approach on an FPGA is also discussed to realize processing at a video rate.

关键词： Dense stereo disparity map dynamic time warp field programmable gate array

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Hardware Implementation of MUSIC Algorithm for Airborne Digital Direction Finding System

Hardware Implementation of MUSIC Algorithm for Airborne Digi...

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7th International Conference on Wireless Communications, Networking and Mobile Computing (WiCOM)

作者： Wang Fan Gao Huo-tao Zhou Lin Sun Yu-xiang Wuhan Univ Elect Informat Dept Wuhan 430072 Peoples R China

ISBN: (纸本)9781424462520

To solve the issue of high complexity and poor real time in conventional array direction finding system of multiple signal classification algorithms, a digital solution based on field programmable gate array (FPGA) is presented. The solution includes real time quadrate demodulation and pretreatment, coordinate rotation digital computing (CORDIC) algorithm in rotation mode to realize singular value decomposition in order to reduce computation, and finally achieves the real time array direction finding. Hardware simulation and tests show that the system works stably and can ensure the deviation is less than 0.5 degree with over 64 snapshots, which can be used in precise positioning and measurement.

关键词： direction finding multiple signal classification field programmable gate array direction of arrival estimation coordinate rotation digital computing

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