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检索条件"主题词=Field Programmable Gate array"

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INTEGRATION AND CONTROL OF A BATTERY BALANCING SYSTEM

INTEGRATION AND CONTROL OF A BATTERY BALANCING SYSTEM

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作者： Peter L. Norgaard Naval Postgraduate School

学位级别：硕士

The primary focus of this research was the integration of series-loaded resonant (SLR) converters into a field- programmable gate array controlled power converter for use in balancing a series-connected battery bank. As the limits of the power grid are continually extended, the market demand for alternate power sources and energy storage systems will continue to grow. The goal of this research was to build and integrate a bank of SLR converters for use in balancing a series-connected battery bank that is part of a broader system used for power storage and conversion. Voltage and temperature sensors were used to monitor individual cell state-of-charge and rate-of-charge and discharge. Voltage-to-frequency conversion was used to read sensor parameters. A battery balancing algorithm was designed, integrated and demonstrated with experimental results.

关键词： power storage series loaded resonant converter voltage calibration temperature sensing battery balancing field programmable gate array

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Enhancing Trust In Autonomous Systems Without Verifying Software

Enhancing Trust In Autonomous Systems Without Verifying Soft...

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作者： Joseph Allan Stamenkovich Virginia Polytechnic Institute and State University

学位级别：硕士

The complexity of the software behind autonomous systems is rapidly growing, as are the applications of what they can do. It is not unusual for the lines of code to reach the millions, which adds to the verification challenge. The machine learning algorithms involved are often "black boxes" where the precise workings are not known by the developer applying them, and their behavior is undefined when encountering an untrained scenario. With so much code, the possibility of bugs or malicious code is considerable. An approach is developed to monitor and possibly override the behavior of autonomous systems independent of the software controlling them. Application-isolated safety monitors are implemented in configurable hardware to ensure that the behavior of an autonomous system is limited to what is intended. The sensor inputs may be shared with the software, but the output from the monitors is only engaged when the system violates its prescribed behavior. For each specific rule the system is expected to follow, a monitor is present processing the relevant sensor information. The behavior is defined in linear temporal logic (LTL) and the associated monitors are implemented in a field programmable gate array (FPGA). An off-the-shelf drone is used to demonstrate the effectiveness of the monitors without any physical modifications to the drone. Upon detection of a violation, appropriate corrective actions are persistently enforced on the autonomous system.

关键词： Autonomy Runtime Verification FPGA field programmable gate array Monitor Formal Methods UAS UAV Security Linear Temporal Logic LTL High-Level Synthesis HLS monitor model checking drone malware assurance robotics firmware hardware

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A Simplified Design of Fast Error Correction Module Using Reed-Solomon Code 1

A Simplified Design of Fast Error Correction Module Using Re...

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1st IEEE International Conference on Ambient Intelligence, Knowledge Informatics and Industrial Electronics, AIKIIE 2023

作者： Parthasarathy, V. Kulkarni, Shreeram V Anand, S. Nagaraj, M.J. Nitte Meenakshi Institute of Technology Dept. of Electrical and Electronics Engineering Bengaluru India

ISBN: (纸本)9798350316469

A Forward Error Correction (FEC) module realized in hardware on field programmable gate array (FPGA) is having more significance in the practical control applications. This is due to its ability to process the data (encoding and decoding) much faster through FPGA and able to overcome the limitations of data transfer. But the real challenge in such a design is the run time reconfiguration. Lot of researches happening on this issue and there is no standard reference available. Also, there is no flexibility in the existing software solutions. Considering this, in this work, the authors were tried to perform a basic software implementation of FEC module using Reed Solomon (RS) code on a custom made system-on-chip with a soft core processor followed by the RTL level implementation of RS code which can be dynamically controlled. To achieve faithful data transfer between two terminals, two NIOS II SOCs (System on Chip) were built on FPGAs. For the implementation, Altera Cyclone III FPGA starter board was used. Quartus II 10.1 Design Software with NIOS II Embedded Design Suite adopted for configuring the FPGA. The performance of the developed model is verified by monitoring the content message bits before and after corruption of data at the receiver terminal. A comparative study was carried out between hardware and software implementations. © 2023 IEEE.

关键词： field programmable gate array forward error correction reed Solomon code run time configuration

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ENHANCED TECHNOLOGY MAPPING FOR FPGAs WITH EXPLORATION OF CELL CONFIGURATIONS

ENHANCED TECHNOLOGY MAPPING FOR FPGAs WITH EXPLORATION OF CE...

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作者： GRACE JOSEPH ZGHEIB Lebanese American University

学位级别：硕士

In the state of the art field-programmable gate arrays (FPGAs), logic circuits are synthesized and mapped on clusters of look-up tables. However, when additions need to be performed, an adder along with a carry-chain is used to ensure a fast execution of such an arithmetic operation. This carry-chain is a dedicated wire available in the architecture of the FPGA and is as such independent of the external programmable routing resources. The proposed idea introduces variable-structure Boolean matching as well as decomposition of mapped functions in order to take advantage of the carry-chains when they are not used for addition operations. Previously synthesized and mapped logic functions are adapted so that their outputs are routed using the dedicated carry-chains instead of the external programmable interconnects. Mapping onto these chains yields a reduction in the overall external routing resources as well as the general routing congestion. Moreover, a generic software platform was developed allowing users to identify and test various basic-unit structures and compare their performances on particular logic circuits depending on criteria specified by the user. Such structures may vary from currently available FPGA architectures to customized theoretical structures well-suited for a specific design(s). This tool can also propose particular cell structures to map logic circuits while respecting the user's constraints and insuring the optimization of specific parameters.

关键词： field programmable gate array Technology Mapping Boolean Matching Decomposition Carry Chain Cell Configuration

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ALU and Dependency Manager Using FPGA

ALU and Dependency Manager Using FPGA

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作者： Hashem, Amjad Qusay University of Michigan

学位级别：硕士

In this project, we have researched the design of high-speed processing units through parallel processing scheme. Our design will be used for Real – Time applications such as Data Acquisition, DSP, Real – Time Controllers, etc. This project is introducing a new method to handle the parallel processing, this method will process instructions with respect to the dependencies among all instructions. Having a parallel processing capability allows this design to have extremely fast processing speed. In this project we will review every part of the system, and how it contributes to the performance of the system. Currently FPGAs are used as specialty processing units of systems to boost up the throughput of those systems. Using FPGA to speed up special operations, such as database sorting [1, p. 53], data buffering, and many other function that require either high throughput processing, or low latency processing [2, p. 213], can increase the performance of the system. In addition, the normal design for a processing unit that can be part of a system is pipelining processing scheme. In this project, we present a new processing scheme capable of parallel processing, as well as dependency management, both built in the internal design of the unit. This design will eliminate the need for a dependency management software, which can take extra processing time or force the processor to have to process instruction sequentially. Instead, this design will allow parallel processing and dependency management built in a single integrated processing unit.

关键词： ALU Arithmetic logic unit Dependency manager FPGA field programmable gate array Parallel processing

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FPGA based ANN classifier for Bengali Handwritten Digit Recognition 26

FPGA based ANN classifier for Bengali Handwritten Digit Reco...

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26th International Conference on Computer and Information Technology, ICCIT 2023

作者： Hossain, S M Riad Zinnurine, Khaled Sadad, Nahin Ul Mondal, Md. Nazrul Islam Rajshahi University of Engineering & Technology Department of Computer Science and Engineering Rajshahi Bangladesh

ISBN: (纸本)9798350359015

In order to accurately and quickly recognize Bengali handwritten digits and characters, this paper suggests an FPGA-based hardware accelerator design of ANN for handwritten Bengali character recognition applications. To discover the best FPGA design for the various categorization rates, a study of network designs is first undertaken. Sigmoid as well as ReLU neurons integrated by Xilinx Vivado workspace and an axi DMA controller created in Verilog Hardware Description Language (HDL) make up the majority of its components. It is clear that sigmoid-based function implementation exceeds ReLU-based implementation for very tiny data widths (such as 4 and 8 bits). The maximum detection accuracy for Sigmoid implementation is 94.00%, and the maximum for ReLU is 87.00%. Finally, this hardware upgrade considerably increased processing speed by 4 times compared to software implementation and about 27 times faster in terms of existing CPU-based hardware implementation, in addition to maintaining recognition accuracy the same as software equivalence. Also, the power consumption is reduced by more than half of its existing solution as discussed before. As a result, the fast and accurate recognition of Bengali handwritten numbers with low power consumption was made possible by our specialized ANN models with FPGA capabilities. © 2023 IEEE.

关键词： and ReLU Artificial Neural Network (ANN) Bengali Digit field programmable gate array Hardware Accelerator HDL Recognition Sigmoid

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Using a model-based systems engineering (Mbse) variant approach for architecting signal processing in a space-based sensor

Using a model-based systems engineering (Mbse) variant appro...

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Accelerating Space Commerce, Exploration, and New Discovery Conference, ASCEND 2020

作者： Gans, Howard D. Cuellar, Robert L3Harris Technologies MelbourneFL32902 United States

ISBN: (数字)9781624106088

ISBN: (纸本)9781624106088

Model-Based Systems Engineering (MBSE) can be used to develop the architecture of a space-based sensor. The process begins with the development of use cases (UCs) of a general system model for a sensor processor which is composed of both hardware and software-based elements. Domain-specific UC’s can then be created and linked to the general level. This process continues through the modeling of variances in system behavior, including activity, sequence and state diagrams. This is done in parallel with the development of structural model instances that represent the configuration of the system for the specific domain being considered. The result is an end-to-end extensible sensor model that can then be applied to analyze the end-to-end signal processing chain. © 2020 The MITRE Corporation. All Rights Reserved.

关键词： Signal Processing Sensor Systems Model Based System Engineering Structural Modeling Structural Analysis field programmable gate array Graphics Processing Unit Small Satellites Data Products

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Preliminary Implementation of Toeplitz Hashing on Processor, Co-Processor and SoC 16

Preliminary Implementation of Toeplitz Hashing on Processor,...

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16th International Conference on COMmunication Systems and NETworkS, COMSNETS 2024

作者： Pandeeti, Guru Satya Dattatreya Dixit, Janhvi Hussain, Asif Behera, Dibya Prakash Dubey, Umang Banerjee, Anindita Maity, Samrit Kumar Modani, Manish Centre for Development of Advanced Computing C-DAC Innovation Park Maharashtra Pune India Nvidia Commerce Zone IT Park Pune Maharashtra Pune India

ISBN: (纸本)9798350383119

Toeplitz Hashing is a class of functions in the 2-universal hash function family, that is widely adopted in quantum secure applications, particularly for the privacy amplification in quantum key distribution to generate secret keys, and as a strong randomness extractor for the quantum random number generators. In this work, we have investigated the preliminary implementation of Toepltiz hashing on processors, co-processors, and system-on-chip (SoC). We have implemented the fast-Fourier transform (FFT)-based Toepltiz hashing on Intel Xeon Cascade-lake 8268 processor and NVIDIA Tesla V100 GPU compute hardware. We have also implemented the binary multiplication-based Toeplitz hashing on the AMD Xilinx ZCU102 FPGA evaluation kit. Further, we present an example of heterogenous computing, by combining an Intel Core i7 CPU with the VEGA ET1031-based Aries v2.0 development board. Finally, we report, for the first time, an implementation of convolution of two matrices on an indigenously designed RISC-V VEGA SoC. Further, we have compared the implementation results following two approaches, i.e. normal matrix multiplication and the number theoretic transform (NTT) method. We report that there is a tenfold reduction in the computational time using the NTT method over the conventional method. © 2024 IEEE.

关键词： Cryptography field programmable gate array Graphics Processing Unit Number Theoretic Transform Quantum Key Distribution Quantum Random Number Generator RISC-V-based processor Toeplitz Hashing

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AN EXPLORATION OF ERROR-CORRECTING CODES FOR USE IN NOISE-PRONE SATELLITE ENVIRONMENTS

AN EXPLORATION OF ERROR-CORRECTING CODES FOR USE IN NOISE-PR...

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作者： Min W. Kang Air Force Institute of Technology

学位级别：硕士

Satellites are crucial for the modern world to function properly as they provide Global Navigation Satellite System (GNSS) and global communication. However, the data that is stored on these satellites can be corrupted by the radiation found in space, and its bits can be improperly flipped. In the past, Forward Error Correction (FEC) algorithms were selected based on their strength and implemented to correct these bit flips back to their original values. This thesis seeks to determine if the strength of the FEC algorithms Reed Solomon (RS) code and Reed Solomon Product Code (RSPC) directly translates to their effectiveness. These algorithms were coded and tested in Matrix Laboratory (MATLAB) and on a field programmable gate array (FPGA) under controlled parameters, including the data set sizes, number of bit flips introduced, and the distribution of the bit flips within the data set. From the experiment's results, these other factors significantly influenced the effectiveness of the algorithms as well. Knowing what factors influence the algorithm's effectiveness enable better decision making as to which FEC algorithm to use for a given set of circumstances. The RS codes should be used if the size of the data set is small enough for a single-instance RS code and the range of expected bit flips is narrow and lower than the code's correctable limit. If the data set is large or the range of expected bit flips varies widely and surpasses the RS code's correctable limit, the RSPC should be used for a higher overall success rate in exchange for a lower number of bit flips with a 100% correction rate.

关键词： Forward Error Correction Reed Solomon Codes Reed Solomon Product Codes MATLAB field programmable gate array

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DETECTION AND INTERPRETATION OF TRANSPLANTED POSITIONS ON FULL-COLOR IMAGE FOR RICE PADDIES WITH FPGA 44

DETECTION AND INTERPRETATION OF TRANSPLANTED POSITIONS ON FU...

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44th Asian Conference on Remote Sensing, ACRS 2023

作者： Wang, Yi-Syun Tsai, Yu-Che Chiou, Yih-Shyh Shih, Mu-Jan Chen, You-Cheng Department of Electronic Engineering Chung Yuan Christian University Taoyuan320314 Taiwan Miin Wu School of Computing National Cheng Kung University Tainan701401 Taiwan

ISBN: (纸本)9781713893646

In recent years, the satellite industry has undergone rapid development, with the emergence of "Starlink", which has played a significant role in driving this progress. Among various types of satellites, Low Earth Orbit (LEO) satellites have garnered substantial attention. These satellites are primarily employed for communication and remote sensing purposes. Remote sensing utilizes imaging techniques for environmental monitoring, weather observation, ocean current analysis, and more. With the continuous increase in the number of satellites, the applications of remote sensing technology have also expanded. This article employs deep learning and appropriate algorithms to investigate the developmental status of rice plants using full-color images captured by unmanned aerial vehicles (UAV). A Convolutional Neural Network (CNN) model is established to locate and label the positions of rice plants. Validation is conducted using an 80/20 training/testing data split ratio, and the developed model is optimized using field-programmable gate array (FPGA) technology. The efficiency is further verified using a known dataset of rice plant coordinates. The model achieves an accuracy of around 94% in terms of the F1-measure value when using desktop computers. With the assistance of PYNQ-Z1, we successfully reduced power consumption to 1.66 watts while accepting a slight decrease in accuracy of approximately 1%. On the PYNQ-Z1, the computation speed increased by 120 times when utilizing programmable Logic (PL) in addition to the Processing System (PS), compared to using only the Processing System (PS). © 2023 ACRS. All Rights Reserved.

关键词： Aerial Photographs Convolutional Neural Network Deep Learning field programmable gate array

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