检索结果-内蒙古大学图书馆

A HARDWARE-BASED MULTI-DISCIPLINARY DESIGN OPTIMISATION METHOD FOR AERONAUTICAL APPLICATIONS

A HARDWARE-BASED MULTI-DISCIPLINARY DESIGN OPTIMISATION METH...

4th International Conference on Computational Methods for Coupled Problems in Science and Engineering (COUPLED PROBLEMS)

作者： Kok, J. Gonzalez, F. Kelson, N. Gurnett, T. QUT ARCAA Eagle Farm Qld 4009 Australia Queensland Univ Technol QUT High Performance Comp HPC & Res Support Grp Brisbane Qld 4000 Australia

ISBN: (纸本)9788489925786

There are many applications in aeronautics where there exist strong couplings between disciplines. One practical example is within the context of Unmanned Aerial Vehicle (UAV) automation where there exists strong coupling between operation constraints, aerodynamics, vehicle dynamics, mission and path planning. UAV path planning can be done either online or offline. The current state of path planning optimisation online UAVs with high performance computation is not at the same level as its ground-based offline optimizer's counterpart, this is mainly due to the volume, power and weight limitations on the UAV;some small UAVs do not have the computational power needed for some optimisation and path planning task. In this paper, we describe an optimisation method which can be applied to Multi-disciplinary Design Optimisation problems and UAV path planning problems. Hardware-based design optimisation techniques are used. The power and physical limitations of UAV, which may not be a problem in PC-based solutions, can be approached by utilizing a field programmable gate array (FPGA) as an algorithm accelerator. The inevitable latency produced by the iterative process of an Evolutionary Algorithm (EA) is concealed by exploiting the parallelism component within the dataflow paradigm of the EA on an FPGA architecture. Results compare software PC-based solutions and the hardware-based solutions for benchmark mathematical problems as well as a simple real world engineering problem. Results also indicate the practicality of the method which can be used for more complex single and multi-objective coupled problems in aeronautical applications.

关键词： Aeronautics field programmable gate array Multi-disciplinary Design Optimisation Unmanned Aerial Vehicle

来源：评论

学校读者我要写书评

暂无评论

Area efficient System-on-programmable-Chip Design for a Wireless Touch-Triggered Machining Probe

Area efficient System-on-Programmable-Chip Design for a Wire...

引用

6th IEEE Conference on Industrial Electronics and Applications (ICIEA)

作者： Mimis, Konstantinos Kocak, Taskin Univ Bristol Dept Elect & Elect Engn Bristol BS8 1UH Avon England Bahcesehir Univ Dept Comp Engn Istanbul 34353 Turkey

ISBN: (纸本)9781424487554

In this paper, we present the design and implementation details of a System-on-programmable-Chip (SoPC), which replaces the circuitry that controls the operation of a touch-triggered machining probe with radio transmission capability. The probe is used to get precise measurements of three dimensional geometric parts. The goal is to achieve size reduction of an existing circuitry inside the probe, that consists of two microcontrollers and a reconfigurable hardware device such as a field programmable gate array (FPGA), that implements some custom functions. In order to reduce the printed circuit board (PCB) area occupied by these three chips and the associated routing area, we combine them on a single SoPC. An overall 6 fold reduction in PCB area occupied, corresponding to nearly 15cm(2) is achieved.

关键词： FPGA field programmable gate arrays IP networks Microcontrollers Probes Program processors field programmable gate array field programmable gate arrays microcontrollers microcontrollers printed circuit board printed circuits radio transmission capability reconfigurable hardware device system-on-chip system-on-programmable-chip design three dimensional geometric parts wireless touch-triggered machining probe

来源：评论

学校读者我要写书评

暂无评论

Memory-Efficient IPv4/v6 Lookup on FPGAs Using Distance-Bounded Path Compression

Memory-Efficient IPv4/v6 Lookup on FPGAs Using Distance-Boun...

引用

IEEE 19th Annual International Symposium on field-programmable Custom Computing Machines (FCCM)

作者： Le, Hoang Jiang, Weirong Prasanna, Viktor K. Univ So Calif Ming Hsieh Dept Elect Eng Los Angeles CA 90089 USA Juniper Networks Inc Sunnyvale CA 94089 USA

ISBN: (纸本)9780769543017

Memory efficiency with compact data structures for Internet Protocol (IP) lookup has recently regained much interest in the research community. In this paper, we revisit the classic trie-based approach for solving the longest prefix matching (LPM) problem used in IP lookup. In particular, we target our solutions for a class of large and sparsely-distributed routing tables, such as those potentially arising in the next-generation IPv6 routing protocol. Due to longer prefix and much larger address space, straight-forward implementation of trie-based LPM can significantly increase the number of nodes and/or memory required for IP lookup. Additionally, due to the available on-chip memory and the number of I/O pins of in the state-of-theart field programmable gate arrays (FPGAs), existing designs cannot support large IPv6 routing tables consisting of over 300K prefixes. We propose two algorithms to compress the uni-bit-trie representation of a given routing table: (1) single-prefix distance-bounded path compression and (2) multiple-prefix distance-bounded path compression. These algorithms determine the optimal maximum skip distance at each node of the trie to minimize the total memory requirement. Our algorithms demonstrate substantial reduction in the memory footprint compared with the uni-bit-trie algorithm (1.86x for IPv4 and 6.16x for IPv6), and with the original path compression algorithm (1.77x for IPv4 and 1.53x for IPv6). Furthermore, implementation on a state-of-the-art FPGA shows that our algorithms achieve 466 million lookups per second and are well suited for 100Gbps lookup. The implementation also scales to support larger routing tables and longer prefix length when we go from IPv4 to IPv6.

关键词： Algorithm design and analysis FPGA FPGA field programmable gate arrays Hardware I/O pins IP Lookup IP networks IP networks IPv4 IPv6 IPv6 routing protocol Internet protocol LPM problem Memory management Path Compression Pipeline Routing Routing Table Throughput Trie compact data structure field programmable gate array field programmable gate arrays longest prefix matching memory-efficient IPv4/v6 lookup multiple-prefix distance bounded path compression on-chip memory optimal maximum slap distance routing protocols routing table lookup single-prefix distance bounded path compression table lookup transport protocols trie-based approach uni-bit-trie algorithm

来源：评论

学校读者我要写书评

暂无评论

ENHANCED TECHNOLOGY MAPPING FOR FPGAs WITH EXPLORATION OF CELL CONFIGURATIONS

ENHANCED TECHNOLOGY MAPPING FOR FPGAs WITH EXPLORATION OF CE...

引用

作者： GRACE JOSEPH ZGHEIB Lebanese American University

学位级别：硕士

In the state of the art field-programmable gate arrays (FPGAs), logic circuits are synthesized and mapped on clusters of look-up tables. However, when additions need to be performed, an adder along with a carry-chain is used to ensure a fast execution of such an arithmetic operation. This carry-chain is a dedicated wire available in the architecture of the FPGA and is as such independent of the external programmable routing resources. The proposed idea introduces variable-structure Boolean matching as well as decomposition of mapped functions in order to take advantage of the carry-chains when they are not used for addition operations. Previously synthesized and mapped logic functions are adapted so that their outputs are routed using the dedicated carry-chains instead of the external programmable interconnects. Mapping onto these chains yields a reduction in the overall external routing resources as well as the general routing congestion. Moreover, a generic software platform was developed allowing users to identify and test various basic-unit structures and compare their performances on particular logic circuits depending on criteria specified by the user. Such structures may vary from currently available FPGA architectures to customized theoretical structures well-suited for a specific design(s). This tool can also propose particular cell structures to map logic circuits while respecting the user's constraints and insuring the optimization of specific parameters.

关键词： field programmable gate array Technology Mapping Boolean Matching Decomposition Carry Chain Cell Configuration

来源：评论

学校读者我要写书评

暂无评论

Net-Length-Based Routability-Driven Power-Aware Clustering

引用

ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2011年第4期4卷 38-38页

作者： Easwaran, Lakshmi Akoglu, Ali Univ Arizona Dept Elect & Comp Engn Tucson AZ 85721 USA

The state-of-the-art power-aware clustering tool, P-T-VPack, achieves energy reduction by localizing nets with high switching activity at the expense of channel width and area. In this study, we employ predicted individual postplacement net length information during clustering and prioritize longer nets. This approach targets the capacitance factor for energy reduction, and prioritizes longer nets for channel width and area reduction. We first introduce a new clustering strategy, W-T-VPack, which replaces the switching activity in P-T-VPack with a net length factor. We obtain a 9.87% energy reduction over T-VPack (3.78% increase over P-T-VPack), while at the same time completely eliminating P-T-VPack's channel width and area overhead. We then introduce W-P-T-VPack, which combines switching activity and net length factors. W-P-T-VPack achieves 14.26% energy reduction (0.31% increase over P-T-VPack), while further improving channel width by up to 12.87% for different cluster sizes. We investigate the energy performance of routability (channel width)-driven clustering algorithms, and show that W-T-VPack consistently outperforms T-RPack and iRAC by at least 11.23% and 9.07%, respectively. We conclude that net-length-based clustering is an effective method to concurrently target energy and channel width.

关键词： Design Performance Channel width clustering field programmable gate array net length prediction power

来源：评论

学校读者我要写书评

暂无评论

DESIGN OF MICROPROGRAMMED CONTROLLERS TO BE IMPLEMENTED IN FPGAs

引用

INTERNATIONAL JOURNAL OF APPLIED MATHEMATICS AND COMPUTER SCIENCE 2011年第2期21卷 401-412页

作者： Wisniewski, Remigiusz Barkalov, Alexander Titarenko, Larisa Halang, Wolfgang A. Univ Zielona Gora Fac Elect Engn Comp Sci & Telecommun PL-65246 Zielona Gora Poland Univ Hagen Fac Math & Comp Sci D-58084 Hagen Germany

In the article we propose a new design method for microprogrammed controllers. The traditional structure is improved by modifying internal modules and connections. Such a solution allows reducing the total number of logic elements needed for implementation in programmable structures, especially field programmable gate arrays (FPGAs). Detailed results of experiments show that on the average the application of the proposed methods yields up to 30% savings as far as the destination device is considered.

关键词： control unit microprogrammed controller field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Fault Tolerant Reconfigurable System with Dual-Module Redundancy and Dynamic Reconfiguration

引用

Journal of Electronic Science and Technology 2011年第2期9卷 167-173页

作者： Qi-Zhong Zhou Xuan Xie Jing-Chen Nan Yong-Le Xie Shu-Yan Jiang School of Automation Engineering University of Electronic Science and Technology of ChinaChengdu 611731China Intel Corporation Chengdu 611731China School of Physics and Electronic Engineering Yibin UniversityYibin 644000China

To handle the effects of single event upsets（SEU）,which are common to computers in space radiation environment,a new fault-tolerant system with dual-module redundancy is proposed using dynamic reconfigurable technique of field programmable gate array（FPGA）. This system contains detection and backup alternative functions,that is,the self-detection and self-healing functions can be completed,and consequently a system design with low hardware redundancy and high resource utilization can be achieved successfully. So it can not only detect fault but also repair the fault effectively after failure. Hence,this method is especially practical to the dynamically reconfigurable computers based on FPGAs. Design methodology has been verified by Virtex-4 FPGA on Xilinx Ml403 development platform.

关键词： Dependable computers fault-tolerant field programmable gate array self-detection single event upsets

来源：评论

学校读者我要写书评

暂无评论

Fast explicit MPC with multiway trees

引用

IFAC Proceedings Volumes 2011年第1期44卷 1356-1361页

作者： M. Mönnigmann M. Kastsian Automatic Control and Systems Theory Ruhr-Universität Bochum 44801 Bochum Germany

Abstract We show that explicit model predictive control (EMPC) laws, or more generally continuous piecewise affine control (PWA) laws on polyhedra, can be represented by multiway trees with two important features: (i) Their height can be reduced arbitrarily by increasing their order m (i.e. the number of binary tree nodes hidden in each multiway node). (ii) A multiway node can be evaluated as fast as a binary node with a simple but massively concurrent (or “parallel”) procedure for m ≫ 1. As a result the control law evaluation can be evaluated considerably faster than with a binary tree. Furthermore, we show that a multiway tree representation of an EMPC control law can be derived from the corresponding binary tree representation with a simple algorithm. Finally, we demonstrate that programmable logic devices are ideally suited for an implementation. First tests show that EMPC control laws with several thousand hyperplanes can be evaluated in a few clock cycles on compact, low-cost, low-power programmable logic devices.

关键词： predictive control explicit field programmable gate array piecewise affine

来源：评论

学校读者我要写书评

暂无评论

Research on Key Technologies of FPGA based Power Quality Monitoring System

Research on Key Technologies of FPGA based Power Quality Mon...

引用

2011 IEEE International Conference on Computer Science and Automation Engineering(CSAE 2011)

作者： Wang Liang Computer Science Department Xiamen University Xiamen,China Lu Da Computer Science Department Xiamen University Xiamen,China

For the advantages of high integration,low power consumption,flexible configuration programming and short development cycle,FPGA is more and more used in the embedded system design.A power quality monitoring system based on FPGA is *** system uses FPGA and Linux as the hardware and software platform,and the FTP protocol to get the sampled *** is controlled by the *** core of the system is the Fast Fourier Transform (FFT) that uses the non-recursive complex sequence *** results show that the test design based on the Spartan 3E500 platform is reliable and ***,the influence of Cache and multi-thread in the computation time is also analyzed.

关键词： Power Quality field programmable gate array Embedded computing Harmonic Analysis

来源：评论

学校读者我要写书评

暂无评论

Implementation of Digital PID controller in field programmable gate array (FPGA)

Implementation of Digital PID controller in Field Programmab...

引用

3rd India International Conference on Power Electronics

作者： Subasri, V. Lavanya, K. Umamaheswari, B. Anna Univ Coll Engn Guindy Tamil Nadu India

ISBN: (纸本)9781424434503

Proportional Integral Derivative (PID) controller is the most preferable controller in industries that does not require precise analytical model of the system to be controlled. Implementation of PID controllers has gone through several stages of evolution from the early mechanical and pneumatic designs to the microprocessor based systems. Recently "field programmable gate array" has become an alternative solution for the realization of Digital PID controllers. This work is aimed at the implementation of serial, parallel and mixed PID controller architectures using FPGA. The digital PID so designed is based essentially in architectures including multipliers, adders and some other logic circuits.

关键词： field programmable gate array Digital PID Architecture

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：