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2023 IEEE Global Conference on Information Technologies and Communications, GCITC 2023

作者： Devi, V. Rama Sreedhar, Jadapalli Cvr College of Engineering Ece Department Hyderabad India Vignana Bharathi Institute of Technology Hyderabad India

ISBN: (纸本)9798350308167

A watchdog timer is a type of electrical timer that detects and recovers from computer errors. In embedded systems and other computer-controlled equipment where individuals are unable to immediately access the equipment or react to faults in a timely way, watchdog timers are often employed. Limiting the amount of CPU time accessible to untrusted programmes in a sandbox can assist avoid denial-of-service attacks. The computer automatically refreshes the watchdog timer during normal operation avoid the timeout. The timeout signal is used to stop a programme from running indicate whether or not a corrective action should be taken. The architecture and design of an improved adjustable windowed watchdog timer for memory applications are described. The watchdog has several defect detection algorithms built in, this makes it more durable. In terms of capabilities and operations, it may be used to monitor any real-time processor-based system. architecture may be modified to a variety of situations may be readily tailored to different applications while keeping the overall system cost low, and owing to the processor reliance the recommended watchdog has less time limitations than the present watchdog. The simulation results are used to investigate the effectiveness of the proposed watchdog timer in detecting and responding to errors. Verilog is used to code the design. Xilinx Vivado 20.1 was used to implement the design. By injecting flaws into the programme while the processor is running, the design is evaluated in real-time hardware. © 2023 IEEE.

关键词： field programmable gate array Frame Window Memory Applications Service Window Windowed Watchdog Timer

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DEVELOPMENT OF A SOFTWARE-DEFINED GNSS SIMULATION PROTOTYPE FOR ADVANCED SIGNALS RESEARCH

DEVELOPMENT OF A SOFTWARE-DEFINED GNSS SIMULATION PROTOTYPE ...

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作者： Michael J. Ledford Air Force Institute of Technology

学位级别：硕士

Global Positioning System (GPS) has become the de-facto standard for precision time transfer. By definition, all signal structure details of the open civilian GPS signals are known and published. This makes them vulnerable to a growing array of threats. One possible solution is to incorporate signal authentication features for future GPS. However, there lacks a hardware platform to verify these features. This thesis proposes a field programmable gate array (FPGA)-based GPS Waveform Prototyping Platform (GWPP) that features a software-defined all-digital signal syn- thesis architecture in conjunction with a high-speed Digital-to-Analog Converter as a solution. GWPP is designed to synthesize GPS waveforms based on the emerging and ma- turing signal generation technology known as Direct Digital Synthesis (DDS). DDS adds dimensions not possible with analog designs in the sense that the fundamen- tal nature of the waveform and its features are generated digitally; hence, providing precise control over the amplitude, frequency, phase, and modulation scheme of the output waveform. The goal of this research is to design, implement, and integrate the GWPP ar- chitecture into the Virtex R? -6 FPGA framework. The limited resources in the FPGA presents a trade-off between signal quality and FPGA resource utilization. This work not only explores the feasibility of the DDS-based architecture to synthesize GPS waveforms, namely the Link-1 Course Acquisition (L1 C/A) signal, but also assesses the spectral performance with consideration in FPGA resource utilization. Currently, the architecture achieves a spurious free dynamic range (SFDR) of -46 decibels rela- tive to the carrier (dBc) consuming only 10% of FPGA logic slices.

关键词： Global Positioning System GPS Global Navigation Satellite System GNSS field programmable gate array FPGA Software-Defined Direct Digital Synthesis DDS

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GF-3 data real-time processing method based on multi-satellite distributed data processing system

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Journal of Central South University 2020年第3期27卷 842-852页

作者： YANG Jun CAO Yan-dong SUN Guang-cai XING Meng-dao GUO Liang College of Geomatics Xi’an University of Science and TechnologyXi’an 710000China National Laboratory of Radar Signal Processing Xidian UniversityXi’an 710071China School of Physics and Optoelectronic Engineering Xidian UniversityXi’an 710071China

Due to the limited scenes that synthetic aperture radar(SAR)satellites can detect,the full-track utilization rate is not *** of the computing and storage limitation of one satellite,it is difficult to process large amounts of data of spaceborne synthetic aperture *** is proposed to use a new method of networked satellite data processing for improving the efficiency of data processing.A multi-satellite distributed SAR real-time processing method based on Chirp Scaling(CS)imaging algorithm is studied in this paper,and a distributed data processing system is built with field programmable gate array(FPGA)chips as the *** from the traditional CS algorithm processing,the system divides data processing into three *** computing tasks are reasonably allocated to different data processing units(i.e.,satellites)in each *** method effectively saves computing and storage resources of satellites,improves the utilization rate of a single satellite,and shortens the data processing ***-3(GF-3)satellite SAR raw data is processed by the system,with the performance of the method verified.

关键词： synthetic aperture radar full-track utilization rate distributed data processing CS imaging algorithm field programmable gate array Gaofen-3

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Compact Low-Cost Ultra-Wideband Pulsed-Radar System

Compact Low-Cost Ultra-Wideband Pulsed-Radar System

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作者： Aaron D. Pitcher McMaster University

学位级别：硕士

Recently, the advent of the integrated circuits (ICs), the monolithic microwave integrated circuits (MMICs) and the multiprocessing computer technology have provided numerous opportunities to make the radar technology compact and affordable. The ultra-wideband (UWB) technology gives many advantages over the traditional narrowband radar systems due to its high spatial resolution, low susceptibility to interference, superior penetration depths, and increased peak power. However, the ability to digitize and reconstruct the full UWB signal spectrum comes at a considerable cost and size. Ultimately, high-speed sampling rates above 10 giga-samples per second (GSPS) are beyond the abilities of conventional analog-to-digital converters (ADCs). The UWB technology is inaccessible to the end-user for various advanced applications in microwave imaging and detection. The purpose of this work is to provide a low-cost, dual-channel UWB pulsed-radar system that is readily available with a 1:10 system bandwidth. The advancements in low-cost alternatives for compact and portable designs empower many promising UWB applications. Here, the desired bandwidth is from 500 MHz to 5 GHz, which utilizes a fast pulse repetition frequency (PRF) in short-range applications. The preliminary results from the novel Equivalent-Time Sampling Receiver are promising with an equivalent-time sampling rate up to 20 GSPS. Nevertheless, the system design is versatile for bandwidth tuning in order to meet the needs of different applications. This versatility is enabled by: i) selection of the effective sampling rate through the field-programmable gate array (FPGA) programming environment, ii) choice of the receivers' front-end track and hold (T & H) amplifier bandwidth, iii) a collection of different PRFs from the low kilohertz up to 20 MHz, iv) tuning of the pulse generator bandwidth, and v) simultaneous multi-channel capabilities enabling antenna beam-forming, polarization diversity and spatial diversity.

关键词： Radar Ultra Wideband Radar field programmable gate array Microwave Circuits Microwave Sensors Sampling Methods

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Methodologies for FPGA Implementation of Finite Control Set Model Predictive Control for Electric Motor Drives

Methodologies for FPGA Implementation of Finite Control Set ...

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作者： Lao, Alex McMaster University

学位级别：硕士

Model predictive control is a popular research focus in electric motor control as it allows designers to specify optimization goals and exhibits fast transient response. Availability of faster and more affordable computers makes it possible to implement these algorithms in real-time. Real-time implementation is not without challenges however as these algorithms exhibit high computational complexity. field-programmable gate arrays are a potential solution to the high computational requirements. However, they can be time-consuming to develop for. In this thesis, we present a methodology that reduces the size and development time of field-programmable gate array based fixed-point model predictive motor controllers using automated numerical analysis, optimization and code generation. The methods can be applied to other domains where model predictive control is used. Here, we demonstrate the benefits of our methodology by using it to build a motor controller at various sampling rates for an interior permanent magnet synchronous motor, tested in simulation at up to 125 kHz. Performance is then evaluated on a physical test bench with sampling rates up to 35 kHz, limited by the inverter. Our results show that the low latency achievable in our design allows for the exclusion of delay compensation common in other implementations and that automated reduction of numerical precision can allow the controller design to be compacted.

关键词： fpga field programmable gate array fcs finite control set hdl hardware description language rtl register transfer level numerical precision satisfiability modulo theories mpc model predictive control word length optimization electric drive electric motor permanent magnet synchronous motor interval arithmetic control system digital control inverter fixed point real time

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The Synthesis Method of High-Speed Finite State Machines in FPGA 1

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19th International Conference on Computer Information Systems and Industrial Management

作者： Salauyou, Valery Borecki, Damian Grzes, Tomasz Bialystok Tech Univ Wiejska 45A PL-15351 Bialystok Poland

ISBN: (数字)9783030476793

ISBN: (纸本)9783030476786;9783030476793

The synthesis method of high-speed finite state machines (FSMs) in field programmable gate arrays (FPGAs) based on LUT (Look Up Table) by internal state splitting is offered. Estimations of the number of LUT levels are presented for an implementation of FSM transition functions in the case of sequential and parallel decomposition. Split algorithms of FSM internal states for the synthesis of high-speed FSMs are described. The method can be easily included in designing the flow of digital systems in FPGA. The experimental results showed a high efficiency of the offered method. FSM performance increased by 1.73 times. In conclusion, the experimental results were considered, and prospective directions for designing high-speed FSMs are specified.

关键词： Synthesis Finite state machine High-speed High performance State splitting field programmable gate array Look up table

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Flexible FPGA based hardware in the loop simulator for control, fault-tolerant and cyber-physical systems 55

Flexible FPGA based hardware in the loop simulator for contr...

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55th AIAA Aerospace Sciences Meeting

作者： Bakker, Tim Leccadito, Matthew T. Klenke, Robert H. Virginia Commonwealth University Electrical and Computer Engineering RichmondVA23220 United States

ISBN: (数字)9781624104473

ISBN: (纸本)9781624104473

Hardware In the Loop Simulation (HILS) is a development platform wherein the real hardware/software system is thoroughly tested and verified for proper working within a simulation environment. The use of HILS can significantly reduce the cost of developing and testing a complex control system where the physical environment cannot be easily reproduced or where a failure could have a costly or even catastrophic effect (ie. aerospace or automotive industries). This paper describes a field programmable gate array (FPGA) based modular HILS platform for unmanned systems with the ability to inject sensor failures and deploy Cyber-Physical System (CPS) attacks. The proposed platform is ideally suited for the development and testing of fault-tolerant cyber-secure control systems. The implemented HILS platform is demonstrated using an existing Flight Control System (FCS) for small Unmanned Aerial Systems (sUAS). © 2017 by the American Institute of Aeronautics and Astronautics, Inc. All rights reserved.

关键词： field programmable gate array Cyber Physical System Barometric Pressure Sensor Flight Control System Control Systems Hardware in the Loop Simulation Unmanned System Unmanned Aerial Systems Ground Control Station Ground Communication System

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Synthesizable Assertion in Hardware and Software Development 2017

Synthesizable Assertion in Hardware and Software Development

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Proceedings of the International Conference on Imaging, Signal Processing and Communication

作者： Ooi Ruey Hock Zulfiqar Ali Bin Abd.Aziz J-Wing Teh University Sains Malaysia Intel Corporation(M) Sdn.Bhd.

ISBN: (纸本)9781450352895

Assertion Based Validation(ABV) is an approach in which the design intent is captured in an executable form where all the out of range and missing intent intents will trigger an error which indicates the fall-outs. By using these assertions can enable early detection of very basic software and hardware bugs in the design. System Verilog is a hardware description language that combine with verification and commonly used as assertion language with its powerful assertion function embedded in the language itself. However not all system verilog language can be synthesize into hardware component and because of the limitation, it only use in software simulation phase of a design cycle. The approach to enable the ABV module in system verilog format to be synthesized into a portion of the hardware is the intent of this paper. It defines the synthesizable building blocks of the assertion modules. This can utilized by both hardware and software development in pre-silicon stage through reconfigurable hardware or field programmable gate array(FPGA). In hardware debug, the synthesized assertions will point to the area of failure, reducing the scope of debug. In software development, the synthesized assertions will point to invalid configurations of hardware registers. The assertions will be synthesized into a separate hardware block which is programmed into a reconfigurable hardware or FPGA together with the Design-Under-Test(DUT). The assertion validation hardware block consists of a ‘Detection and Distribution' block and a series of ‘Property Tracking' block to track the multiple events separately. If all separate events are met but the expected scenario is not met, a register bit will be set for this assertion point to signify failure. Final assertion results will be written to memory on the reconfigurable hardware or FGPA. The purpose of this paper is to identify the common assertion function that widely use in hardware design and synthesis of these assertion properties from

关键词： Assertion Based Validation, ABV System Verilog field programmable gate array FPGA

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Moving Lean Instant Slope Constant Estimator for Fast Online Measurement of Derivative and Absolute Value of Oversampled Signals 8

Moving Lean Instant Slope Constant Estimator for Fast Online...

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8th Southern Power Electronics Conference and the 17th Brazilian Power Electronics Conference, SPEC / COBEP 2023

作者： Liske, Andreas Bachowsky, Benjamin Brodbeck, Matthias Hiller, Marc Karlsruhe Germany

ISBN: (纸本)9798350321128

In this paper an improved moving, non-recursive Least Squares Estimator is presented that is very lean in its implementation, requires very low computational effort and has very low latency after the last sample of a measurement interval. It is very well suited for fast online measurement of the first derivative and the absolute value of measurement signals in power electronics and drives applications such as current slopes, which can then be used for online parameter identification of electrical machines, adaptive control, fast HIL and PHIL control, condition monitoring or fault detection. © 2023 IEEE.

关键词： adaptive control estimation techniques field programmable gate array least squares measurement online parameter identification

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Design of Parallel Electrical Resistance Tomography System for Measuring Multiphase Flow

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Chinese Journal of Chemical Engineering 2012年第2期20卷 368-379页

作者：董峰许聪张志强任尚杰 Tianjin Key Laboratory of Process Measurement and Control School of Electrical Engineering and AutomationTianjin University

ERT(electrical resistance tomography) is effective method for visualization of multiphase flows,offering some advantages of rapid response and low cost,so as to explore the transient *** at this target,a fully programmable and reconfigurable FPGA(field programmable gate array)-based Compact PCI(peripheral component interconnect) bus linked sixteen-channel ERT system has been *** data acquisition system is carefully designed with function modules of signal generator module;Compact PCI transmission module and data processing module(including data sampling,filtering and demodulating).The processing module incorporates a powerful FPGA with Compact PCI bus for communication,and the measurement process management is conducted in *** reconstruction algorithms with different speed and accuracy are also coded for this *** system has been demonstrated in real time(1400 frames per second for 50 kHz excitation) with signal-noise-ratio above 62 dB and repeatability error below 0.7%.Static experiments have been conducted and the images manifested good resolution relative to the actual object *** parallel ERT system has provided alternative experimental platform for the multiphase flow measurements by the dynamic experiments in terms of concentration and velocity.

关键词： electrical resistance tomography data acquisition compact peripheral component interconnect field programmable gate array digital filter digital demodulation

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