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Proceedings of the International Conference on Imaging, Signal Processing and Communication

作者： Ooi Ruey Hock Zulfiqar Ali Bin Abd.Aziz J-Wing Teh University Sains Malaysia Intel Corporation(M) Sdn.Bhd.

ISBN: (纸本)9781450352895

Assertion Based Validation(ABV) is an approach in which the design intent is captured in an executable form where all the out of range and missing intent intents will trigger an error which indicates the fall-outs. By using these assertions can enable early detection of very basic software and hardware bugs in the design. System Verilog is a hardware description language that combine with verification and commonly used as assertion language with its powerful assertion function embedded in the language itself. However not all system verilog language can be synthesize into hardware component and because of the limitation, it only use in software simulation phase of a design cycle. The approach to enable the ABV module in system verilog format to be synthesized into a portion of the hardware is the intent of this paper. It defines the synthesizable building blocks of the assertion modules. This can utilized by both hardware and software development in pre-silicon stage through reconfigurable hardware or field programmable gate array(FPGA). In hardware debug, the synthesized assertions will point to the area of failure, reducing the scope of debug. In software development, the synthesized assertions will point to invalid configurations of hardware registers. The assertions will be synthesized into a separate hardware block which is programmed into a reconfigurable hardware or FPGA together with the Design-Under-Test(DUT). The assertion validation hardware block consists of a ‘Detection and Distribution' block and a series of ‘Property Tracking' block to track the multiple events separately. If all separate events are met but the expected scenario is not met, a register bit will be set for this assertion point to signify failure. Final assertion results will be written to memory on the reconfigurable hardware or FGPA. The purpose of this paper is to identify the common assertion function that widely use in hardware design and synthesis of these assertion properties from

关键词： Assertion Based Validation, ABV System Verilog field programmable gate array FPGA

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Moving Lean Instant Slope Constant Estimator for Fast Online Measurement of Derivative and Absolute Value of Oversampled Signals 8

Moving Lean Instant Slope Constant Estimator for Fast Online...

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8th Southern Power Electronics Conference and the 17th Brazilian Power Electronics Conference, SPEC / COBEP 2023

作者： Liske, Andreas Bachowsky, Benjamin Brodbeck, Matthias Hiller, Marc Karlsruhe Germany

ISBN: (纸本)9798350321128

In this paper an improved moving, non-recursive Least Squares Estimator is presented that is very lean in its implementation, requires very low computational effort and has very low latency after the last sample of a measurement interval. It is very well suited for fast online measurement of the first derivative and the absolute value of measurement signals in power electronics and drives applications such as current slopes, which can then be used for online parameter identification of electrical machines, adaptive control, fast HIL and PHIL control, condition monitoring or fault detection. © 2023 IEEE.

关键词： adaptive control estimation techniques field programmable gate array least squares measurement online parameter identification

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Design of Parallel Electrical Resistance Tomography System for Measuring Multiphase Flow

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Chinese Journal of Chemical Engineering 2012年第2期20卷 368-379页

作者：董峰许聪张志强任尚杰 Tianjin Key Laboratory of Process Measurement and Control School of Electrical Engineering and AutomationTianjin University

ERT(electrical resistance tomography) is effective method for visualization of multiphase flows,offering some advantages of rapid response and low cost,so as to explore the transient *** at this target,a fully programmable and reconfigurable FPGA(field programmable gate array)-based Compact PCI(peripheral component interconnect) bus linked sixteen-channel ERT system has been *** data acquisition system is carefully designed with function modules of signal generator module;Compact PCI transmission module and data processing module(including data sampling,filtering and demodulating).The processing module incorporates a powerful FPGA with Compact PCI bus for communication,and the measurement process management is conducted in *** reconstruction algorithms with different speed and accuracy are also coded for this *** system has been demonstrated in real time(1400 frames per second for 50 kHz excitation) with signal-noise-ratio above 62 dB and repeatability error below 0.7%.Static experiments have been conducted and the images manifested good resolution relative to the actual object *** parallel ERT system has provided alternative experimental platform for the multiphase flow measurements by the dynamic experiments in terms of concentration and velocity.

关键词： electrical resistance tomography data acquisition compact peripheral component interconnect field programmable gate array digital filter digital demodulation

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An Energy-Efficient Design-Time Scheduler for FPGAs Leveraging Dynamic Frequency Scaling Emulation 17

An Energy-Efficient Design-Time Scheduler for FPGAs Leveragi...

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ACM/SIGDA International Symposium on field-programmable gate arrays

作者： Loke, Wei Ting Koay, Chin Yang Natl Univ Singapore Singapore Singapore Xilinx San Jose CA USA

ISBN: (纸本)9781450343541

We present a design-time tool, EASTA, that combines the feature of reconfigurability in FPGAs and Dynamic Frequency Scaling to realize an efficient multiprocessing scheduler on a single-FPGA system. Multiple deadlines, reconvergent nodes, flow dependency and processor constraints of the multiprocessor problem on general task graphs are rigorously taken into consideration. EASTA is able to determine the minimum number of processing elements required to create a feasible schedule and dynamically adjust the clock speed of each processing element to reclaim slack. The schedule is represented by an efficient tree-based lookup table. We evaluate the EASTA tool using randomly generated task graphs and demonstrate that our framework is able to produce energy savings of 39.41% and 33% for task graphs of size 9.

关键词： field programmable gate array Low Power Dynamic Frequency Scaling Design-Time Scheduling

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Root Cause Analysis and Classification of Single Point Failures in Designs Applying Triple Modular Redundancy in SRAM FPGAs

Root Cause Analysis and Classification of Single Point Failu...

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作者： Swift, James D. Brigham Young University

学位级别：M.Sc.

Radiation effects encountered in space or aviation environments can affect the configuration bits in field programmable gate arrays (FPGA) causing errors in FPGA output. One method of increasing FPGA reliability in radiation environments includes adding redundant logic to mask errors and allow time for repair. Despite the redundancy added with triple modular redundancy (TMR) and configuration scrubbing there exist some configuration bits that individually affect multiple TMR domains causing errors in FPGA output. A new tool called DeBit is introduced that identifies hardware resources associated with a single bit failure. This tool identifies a novel failure mode involving global routing resources and the failure mode is verified through a series of directed tests on global routing resources. Lastly, a mitigation strategy is proposed and tested on a single error in a triple modular redundancy (TMR) design.

关键词： Single Event Upset field programmable gate array Triple Modular Redundancy Reliability SEU FPGA TMR James D. Swift Thesis

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Electromagnetic emanation exploration in FPGA-based digital design

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Journal of Central South University 2019年第1期26卷 158-167页

作者： Van Toan NGUYEN Minh Tung DAM Jeong-Gun LEE E-SoC Laboratory/Smart Computing Laboratory Department of Computer Engineering Hallym University

As semiconductor technologies have been shrinking,the speed of circuits,integration density,and the number of I/O interfaces have been significantly *** a consequence,electromagnetic emanation(EME)becomes a critical issue in digital system *** devices must meet electromagnetic compatibility(EMC)requirements to ensure that they operate properly,and safely without interference.I/O buffers consume high currents when they *** bonding wires,and lead frames are long enough to play as efficient antennas to radiate electromagnetic interference(EMI).Therefore,I/O switching activities significantly contribute to the *** this paper,we evaluate and analyze the impact of I/O switching activities on the *** will change the circuit configurations such as the supply voltage for I/O banks,their switching frequency,driving current,and slew ***,a trade-off between the switching frequencies and the number of simultaneous switching outputs(SSOs)is also considered in terms of ***,we evaluate the electromagnetic emissions that are associated with the different I/O switching *** results show that the electromagnetic emissions associated I/O switching activities depend strongly on their operating parameters and *** the circuit implementations and measurements are carried out on a Xilinx Spartan-3 FPGA.

关键词： electromagnetic interference electromagnetic emanation near field emissions field programmable gate array slew rate

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ADAPTATION OF A FAULT–TOLERANT FPGA–BASED LAUNCH SEQUENCER AS A CUBESAT PAYLOAD PROCESSOR

ADAPTATION OF A FAULT–TOLERANT FPGA–BASED LAUNCH SEQUENCER...

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作者： Jordan K. Goff Naval Postgraduate School

学位级别：硕士

The purpose of this thesis is to design and test a fault–tolerant reduced instruction set computer processor running a subset of the multiprocessor without interlocked pipelined stages instruction set. This processor is implemented on a field programmable gate array (FPGA) and will be used as the foundation for a payload processor on a cube satellite developed at the Naval Postgraduate School. This thesis begins by considering the radiation effects present in the space environment and the various fault– tolerant designs used to guard against specific types of particle events. The internal triple modular redundancy method is selected and implemented at each pipeline stage of the processor. Next, a target FPGA is selected based on the performance requirements of the processor. The Virtex–5 (registered trademark of Xilinx, Inc.) is selected over the ProASIC3 (registered trademark of Microsemi, Inc.) due to its enhanced capabilities and potential to support expansion for future applications. The hardware design is presented as a hybrid Verilog and schematic based design. The system consists of the processor and a universal asynchronous receiver/transmitter that reads and writes data received from a generic serial interface. The device is simulated to ensure proper logic functionality. Conclusions and future work are discussed.

关键词： Fault-tolerant Payload Processor Cube Satellite Internal Triple Modular Redundancy field programmable gate array Universal Asynchronous Receiver Transmitter

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Implementation of TinyOS on FPGA System

Implementation of TinyOS on FPGA System

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IEEE Region 10 Conference on TENCON 2010

作者： Dai-Hai Ton-That Anh-Vu Dinh-Duc Khoi Phan-Dinh Univ Technol Fac Comp Sci & Engn Ho Chi Minh City Vietnam

ISBN: (纸本)9781424468904

Wireless sensor networks are used in many fields. The needs to develop application based on wireless sensor networks are imperious. The node in wireless sensor networks nowaday is not only cheap but also reusable. To fulfill these requirements many technologies were researched and developed, one of which is field programmable gate array (FPGA). We can utilize the reconfigurable characteristic of FPGA to implement nodes of a wireless sensor network with little effort. This paper proposes the method to port TinyOS, an operating system particularly designed for wireless embedded sensor network, on FPGA system. This fills the gaps between FPGA and wireless sensor networks.

关键词： TinyOS field programmable gate array Wireless sensor networks FPGA WSNs

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A comprehensive analysis of DAC-SDC FPGA low power object detection challenge

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Science China(Information Sciences) 2024年第8期67卷 300-320页

作者： Jingwei ZHANG Guoqing LI Meng ZHANG Xinye CAO Yu ZHANG Xiang LI Ziyang CHEN Jun YANG School of Electronics Science and Engineering Southeast University

The lower power object detection challenge(LPODC) at the IEEE/ACM Design Automation Conference is a premier contest in low-power object detection and algorithm(software)-hardware co-design for edge artificial intelligence, which has been a success in the past five years. LPODC focused on designing and implementing novel algorithms on the edge platform for object detection in images taken from unmanned aerial vehicles(UAVs), which attracted hundreds of teams from dozens of countries to participate. Our team SEUer has been participating in this competition for three consecutive years from 2020 to 2022 and obtained sixth place respectively in 2020 and 2021. Recently, we achieved the championship in 2022. In this paper, we presented the LPODC for UAV object detection from 2018 to 2022, including the dataset, hardware platform,and evaluation method. In addition, we also introduced and discussed the details of methods proposed by each year's top three teams from 2018 to 2022 in terms of network, accuracy, quantization method, hardware performance, and total score. Additionally, we conducted an in-depth analysis of the selected entries and results, along with summarizing representative methodologies. This analysis serves as a valuable practical resource for researchers and engineers in deploying the UAV application on edge platforms and enhancing its feasibility and reliability. According to the analysis and discussion, it becomes evident that the adoption of a hardware-algorithm co-design approach is paramount in the context of tiny machine learning(TinyML).This approach surpasses the mere optimization of software and hardware as separate entities, proving to be essential for achieving optimal performance and efficiency in TinyML applications.

关键词： tiny machine learning object detection convolutional neural networks algorithm-hardware co-design low power field programmable gate array

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Real-Time Upstream Services Demonstration in Orthogonal Frequency Division Multiplexing- Passive Optical Network System

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China Communications 2014年第1期11卷 26-33页

作者： LI Ming Andrey Lukyanenko Sasu Tarkoma Antti Yl-Jski Department of Computer Science and Engineering Aalto University Department of Computer Science University of Helsinki

Abstract： Real-time digital service and mul- timedia service upstream transmission in Dig- ital Signal Processing （DSP）-based Orthogo- nal Frequency Division Multiplexing-Passive Optical Network （OFDM-PON） is experimen- tally demonstrated with Centralised Light Sou- rce （CLS） configuration in this paper. After transmitted over 25 km Standard Single Mode Fibre （SSMF） with -16.5 dBm optical power at receiver, the Bit Error Rate （BER） is 9.5 ×10^-11. The implementations of digital domain up-conversion and down-conversion based on field programmable gate array （FPGA） are int- roduced, which can reduce the cost of In-ph- ase and Quadrature （IQ） radio frequency mix- ers utilised at transmitter and receiver. A car- rier synchronization algorithm is implemented for compensating carrier offset. A channel eq- ualization algorithm is adopted for compen- sating the damage of channel. A new structure of Frequency Synchronization Unit （FSU） des- igned in FPGA is also proposed to cope with the frequency shifting at receiver.

关键词： orthogonal frequency division multiplexing-passive optical network real-time field programmable gate array wavelength division multiplexing-OFDM-PON frequency synchronization

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