A series of ultra-lightweight digital true random number generators (TRNGs) are presented. These TRNGs are based on the observation that, when a circuit switches from a metastable state to a bi-stable state, the resul...
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A series of ultra-lightweight digital true random number generators (TRNGs) are presented. These TRNGs are based on the observation that, when a circuit switches from a metastable state to a bi-stable state, the resulting state may be random. Four such circuits with low hardware cost are presented: one uses an XOR gate;one uses a lookup table;one uses a multiplexer and an inverter;and one uses four transistors. The three TRNGs based on the first three circuits are implemented on a field programmable gate array and successfully pass the DIEHARD RNG tests and the National Institute of Standard and Technology (NIST) RNG tests. To the best of the authors' knowledge, the proposed TRNG designs are the most lightweight among existing TRNGs.
This paper discusses the design and implementation of a new generation of digital stethoscopes capable of collecting and processing body sound without the need of a personnel computer and hardware interface. The cost ...
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This paper discusses the design and implementation of a new generation of digital stethoscopes capable of collecting and processing body sound without the need of a personnel computer and hardware interface. The cost of the proposed device is a fraction of that of the data acquisition system used with current digital stethoscopes to collect body sound in a digital format. The new design uses system-on-chip technology and hardware- software co-design to integrate all the functions needed by this application into a single field programmable gate array (FPGA). The new design strategy saves hardware, space, and power consumption. It also allows for signal processing and data interpretation in the same device. The body sound device has been implemented and tested. Its performance compares very favourably to that of existing PC-based digital stethoscope.
The paper describes a field programmable gate array implementation of the main part of speech recognition system - feature extraction. In order to accelerate recognition the whole cepstral analysis scheme is implement...
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ISBN:
(纸本)9780819482358
The paper describes a field programmable gate array implementation of the main part of speech recognition system - feature extraction. In order to accelerate recognition the whole cepstral analysis scheme is implemented in hardware by the use of intellectual property cores. Two field programmable gate array devices are used for evaluation. Comparative experimental results of four different implementations are presented. They grounds achieved 29 times faster speech analysis in comparison with software based analysis subsystem.
Based on FPGA (field programmable gate array) technology, the realization of a sensorless control IC for IPMSM (Interior Permanent Magnet Synchronous Motor) drive is presented in this paper. Firstly, a mathematical mo...
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ISBN:
(纸本)9781424452262
Based on FPGA (field programmable gate array) technology, the realization of a sensorless control IC for IPMSM (Interior Permanent Magnet Synchronous Motor) drive is presented in this paper. Firstly, a mathematical model for IPMSM is derived and an extended EMF (Electro-Motive Force) or EEMF is defined. Secondly, a rotor position is estimated by using a sliding mode observer (SMO). These estimated values are feed-backed to the current loop for vector control and to the speed loop for speed control. Thirdly, an FSM (Finite State Machine) method is adopted to describe the overall SMO-based rotor position estimator. Further, using novel FPGA technology, the realization of a sensorless speed control IC is also described. At last, an experimental system is established to verify the effectiveness of the proposed sensorless speed control IC, and some experimental results are confirmed theoretically.
This paper presents a useful design of the time-series driving, data acquisition and real-time imaging system for the uncooled infrared focal plane arrays (UIRFPA). The field programmable gate array (FPGA) is used as ...
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ISBN:
(纸本)9780819480880
This paper presents a useful design of the time-series driving, data acquisition and real-time imaging system for the uncooled infrared focal plane arrays (UIRFPA). The field programmable gate array (FPGA) is used as the central processing unit (CPU) in the system, which can control and harmonize all functional modules. The Ping-Pong structure is employed to realize real-time imaging. The SDRAM is adopted for the data storage to fulfill the need of mass memory. And there are also some switches and keys to provide human-machine interaction. This system works for UIRFPA with resolution of 320x240 steadily and authoritatively. The noise doesn't merge in main signals, so the system can extract the signals of UIRFPA accurately and efficiently.
This paper describes the development and implementation of a permanent magnet synchronous machine controller for safety critical applications which embeds independent real-time mechanical-fault diagnostics into the dr...
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ISBN:
(纸本)9781424452873
This paper describes the development and implementation of a permanent magnet synchronous machine controller for safety critical applications which embeds independent real-time mechanical-fault diagnostics into the drive controller. The drive is intended for aerospace applications and therefore must employ an ASIC or FPGA as the main control "processor" to provide a more suitable route to flight-product certification. Motor Current Signature Analysis (MCSA) is employed to indicate the development or existence of faults within the drive system and this is achieved by embedding a real-time frequency analysis of the motor current within the FPGA, operating independently of the motor control. Experimental results are provided to validate the proposed control and condition monitoring.
In this article, we reported for the first time, a low complexity field programmable gate array solution for integrating video surveillance into RFID units. The method is comprised of two major building blocks, namely...
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In this article, we reported for the first time, a low complexity field programmable gate array solution for integrating video surveillance into RFID units. The method is comprised of two major building blocks, namely a RFID transmitter operating at a maximum bandwidth of 250 kbps, and a near computation free image compression engine based on an enhanced Decomposed Adaptive Decimation scheme. (C) 2010 Wiley Periodicals, Inc. MIcrowave Opt Technol Lett 52 775-779, 2010.
To sustain advanced interdisciplinary teaching and learning in the rapidly growing and diversifying field of robotics, we have successfully employed FPGA based System on Chip (SoC) technology to provide abstraction be...
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ISBN:
(纸本)9781424466757
To sustain advanced interdisciplinary teaching and learning in the rapidly growing and diversifying field of robotics, we have successfully employed FPGA based System on Chip (SoC) technology to provide abstraction between high level software and low level I/O- and control hardware. Our approach is to provides students with a simple FPGA based framework for hardware access, and hardware I/O development, which is independent of computer platform and programming language, and enable the students to add to, or change I/O hardware in accordance with their skills. We have tested the framework in an embedded systems course and various student projects, and have found that it greatly enhance the students abilities to control hardware from software, and dramatically reduce the time spent on software <-> hardware interfacing. As the framework is also scalable, it can support projects from controlling a single LED, to complex modular and aggregated robots with demands for high bandwidths and low jitter in the control loop.
Face detection is an important aspect for biometrics, video surveillance and human computer interaction. We present a multi-GPU implementation of the Viola-Jones face detection algorithm that meets the performance of ...
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ISBN:
(纸本)9780769540566
Face detection is an important aspect for biometrics, video surveillance and human computer interaction. We present a multi-GPU implementation of the Viola-Jones face detection algorithm that meets the performance of the fastest known FPGA implementation. The GPU design offers far lower development costs, but the FPGA implementation consumes less power. We discuss the performance programming required to realize our design, and describe future research directions.
This paper presents an FPGA-based ultrasonic location system. This system uses low-cost FPGAs and ultrasonic transducers to provide 3-D location to mobile nodes in an indoor environment. Synchronization is reached usi...
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ISBN:
(纸本)9781424463916
This paper presents an FPGA-based ultrasonic location system. This system uses low-cost FPGAs and ultrasonic transducers to provide 3-D location to mobile nodes in an indoor environment. Synchronization is reached using the radiofrequency transducers that mobile nodes usually include. FPGAs have been used to sample ultrasonics and radiofrequency inside a custom peripheral which is attached to a MicroBlaze soft-processor. The calculus of the position of the mobile node is accomplished inside this processor.
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