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检索条件"主题词=Field Programmable Gate array"

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FPGA-based Embedded System for Ultrasonic Positioning

FPGA-based Embedded System for Ultrasonic Positioning

引用

IEEE International Symposium on Industrial Electronics (ISIE)

作者： Sanchez, Alberto de Castro, Angel Glez-de-Rivera, Guillermo Garrido, Javier Univ Autonoma Madrid HCTLab Madrid Spain

ISBN: (纸本)9781424463916

This paper presents an FPGA-based ultrasonic location system. This system uses low-cost FPGAs and ultrasonic transducers to provide 3-D location to mobile nodes in an indoor environment. Synchronization is reached using the radiofrequency transducers that mobile nodes usually include. FPGAs have been used to sample ultrasonics and radiofrequency inside a custom peripheral which is attached to a MicroBlaze soft-processor. The calculus of the position of the mobile node is accomplished inside this processor.

关键词： field programmable gate array location ultrasonics trilateration

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From Petri net models to C implementation of digital controllers

From Petri net models to C implementation of digital control...

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IEEE International Symposium on Industrial Electronics (ISIE)

作者： Gomes, Luis Rebelo, Rogerio Barros, Joao Paulo Costa, Aniko Pais, Rui Univ Nova Lisboa Fac Ciencias & Tecnol P-1200 Lisbon Portugal Univ Nova Lisboa Ctr Tecnol & Sistemas Lisbon Portugal Inst Politecn Beja Escola Sup Technol & Gestao Lisbon Portugal

ISBN: (纸本)9781424463916

This work presents a tool for automatic generation of controllers' implementation code from Petri nets models amenable to be deployed into common platforms using widely used high level programming languages, such as C, C++, and Java. The generated code is linked with platform specific functions, supporting different types of implementation platforms, ranging from low-cost microcontrollers to workstations, and including microcontroller IPs (Intellectual Property) to be embedded into FPGAs (field programmable gate arrays). The system controller behavior is modeled using IOPT (Input-Output Place-Transition) Petri Nets models, which are represented through PNML (Petri nets Mark-up Language) notation. A tool for automatic code generation was developed, which achieved this goal in cooperation with other developed tools within a model-based development framework. Application to an automation system composed by a set of distributed controllers is presented.

关键词： C implementation C++ language Java Java PNML Petri nets Petri nets mark-up language automatic code generation automatic generation digital control digital controller field programmable gate array field programmable gate arrays high level programming languages input output place transition intellectual property low cost microcontroller microcontrollers model based development framework platform specific functions program compilers system controller behavior

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Reconstruction Algorithm Realization with FPGA based on the emission spectral tomography

Reconstruction Algorithm Realization with FPGA based on the ...

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5th International Symposium on Advanced Optical Manufacturing and Testing Technologies - Optical Test and Measurement Technology and Equipment

作者： Leng, Biyan Wan, Xiong Zhang, Zhimin Deng, Xiaoming Luo, Ningning Nanchang Hangkong Univ Key Lab Nondestruct Test Minist Educ Nanchang 330063 Peoples R China

ISBN: (纸本)9780819480866

Reconstruction for Emission Spectral Tomography(EST) is based on thick and fast digital signal processing all along, and the computation quantity is astronomical. With the acknowledgement of SIRT, the parallel computing of FPGA and the flexibility of NIOS II high-speed computing power are well used. Through the hardware description language VERILOG HDL and costuming macros module as well as the embedded system NIOS II, then achieved the purpose of the reconstruction for EST.

关键词： Emission Spectral Tomography field programmable gate array Simultaneous Iterative Reconstruction Technique NIOS II

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A Simple & Cost-Effective Novel Methodology for Predicting SSN System Performance for Different PCB Trace Lengths

A Simple & Cost-Effective Novel Methodology for Predicting S...

引用

IEEE Electrical Design of Advanced Package and Systems Symposium

作者： Ang, Chun Wooi Lo, Wei Wei Wong, Man On Plot 6 Bayan Lepas Technoplex Bayan Lepas 11900 Penang Malaysia

ISBN: (纸本)9781424490684

High data rates, high clock speeds, and low power consumption are synonymous with advanced electronic devices. Consequently, simultaneous switching noise (SSN) is emerging as a critical side-effect of toggling signals within an electronic device because SSN affects signal integrity. Even minute changes in signal voltage in the order of a few millivolts can adversely affect the functioning of a circuit. A PCB typically forms the communication backbone between electronic components including field programmable gate array (FPGA) devices. Signal quality and SSN effects vary with PCB trace lengths. Traditionally, complex board models are used to simulate the SSN characteristics of electronic devices for different PCBs, which can be time consuming and expensive. This paper presents a cost-effective novel methodology for de-embedding the PCB trace effect to accurately characterize an FPGA device's intrinsic SSN characteristics. The methodology uses simple and fast measurement and simulation techniques to de-embed the PCB trace effect for different PCB trace lengths. The predicted SSN data for different PCB trace lengths and intrinsic SSN data obtained using this methodology will be useful to FPGA system designers.

关键词： FPGA device FPGA system designer PCB trace effect PCB trace length SSN system performance prediction advanced electronic device communication backbone complex board model critical side-effect electronic component field programmable gate array field progra

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Design and Implementation of DSP and FPGA-Based Robust Visual Servoing Control of an Inverted Pendulum

Design and Implementation of DSP and FPGA-Based Robust Visua...

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IEEE International Conference on Control Applications Part of 2010 IEEE Multi-Conference on Systems and Control

作者： Tu, Yi-Wei Ho, Ming-Tzu

ISBN: (纸本)9781424453634

This paper presents the design and implementation of robust real-time visual servoing control with an FPGA-based image co-processor for a rotary inverted pendulum. The position of the pendulum is measured with a machine vision system whose image processing algorithms are pipelined and implemented on a field programmable gate array (FPGA) device to meet real-time constraints. To enforce robustness to model uncertainty, and to attenuate disturbance and sensor noise, the design of the stabilizing controller is formulated as a problem of the mixed H(2)/H(infinity) control, which is then solved using the linear matrix inequality (LMI) approach. The designed control law is implemented on a digital signal processor (DSP). The effectiveness of the controller and the FPGA-based image co-processor is verified through experimental studies. The experimental results show that the designed system is able to robustly control an inverted pendulum in real-time.

关键词： DSP FPGA digital signal processing chips digital signal processor field programmable gate array field programmable gate arrays image co-processor inverted pendulum linear matrix inequalities machine vision whose system mixed HÎ¹lHÏ control optimal control path planning robust control robust visual servoing control visual servoing

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Acceleration of FPGA-based ICA processor for real-time processing

Acceleration of FPGA-based ICA processor for real-time proce...

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2010 IEEE International Symposium Antennas and Propagation/CNC-USNC/URSI Radio Science Meeting

作者： Fujio, Shunsuke Shiomi, Hidehisa Okamura, Yasuyuki Osaka Univ Grad Sch Engn Sci Suita Osaka 565 Japan

This paper describes about designing of the architecture of the fastICA for FPGA, and it can check that it is possible to perform ICA processing in real-time for transmission of the QPSK signals of more than 1 Mbps.

ISBN: (纸本)9781424449682

关键词： FPGA-based ICA processor QPSK signals fast ICA algorithm field programmable gate array field programmable gate arrays independent component analysis independent component analysis quadrature phase shift keying quadrature phase shift keying real-time processing

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OpenCV compatible real time processor for background foreground identification

OpenCV compatible real time processor for background foregro...

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22nd International Conference on Microelectronics (ICM 2010)

作者： Genovese, M. Napoli, E. Petra, N. Univ Napoli DIBET I-80125 Naples Italy

ISBN: (纸本)9781612841519

The background identification methods are used in many fields like video surveillance and traffic monitoring. In this paper we propose a hardware implementation of the Gaussian Mixture Model algorithm able to perform background identification on HD images. The proposed circuit is based on the OpenCV implementation, particularly suited to improve the initial background learning phase. Bit-width has been optimized in order to reduce hardware complexity and increase working speed. The proposed circuit processes 22 1920X1080 frames per second when implemented on Virtex 5 FPGA.

关键词： Background identification field programmable gate array Object detection OpenCV

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HALT Evaluation of SJ BIST Technology for Electronic Prognostics

HALT Evaluation of SJ BIST Technology for Electronic Prognos...

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AUTOTESTCON 2010 Systems Readiness Technology Conference

作者： Hofmeister, James P. Vohnout, Sonia Mitchell, Christopher Heimes, Felix O. Saha, Sambit Ridgetop Grp Inc 6595 N Oracle Rd Tucson AZ 85704 USA BAE Syst Platform Solt Johnstown NY 13790 USA

ISBN: (纸本)9781424479597

This paper presents the design, test, and results of a highly accelerated life test (HALT) evaluation of a soft-core called Solder Joint Built-in Self-Test T (SJ BIST (TM)), a method for detecting faults caused by solder-joint fractures in monitored input/output (I/O) pins of field programmable gate array (FPGA) devices, especially those in ball grid array (BGA) type of packages. Modern electronics utilize large FPGAs packages attached to electronic boards by means of solder joints, such as solder balls, between the package and the board. Thermo-mechanical stresses - primarily heat and vibration - cause fatigue damage and eventual fracture failure of one or more balls, which causes intermittent operational faults leading to catastrophic failures in critical systems. Such intermittent faults are difficult to reproduce on a test bench and many field returns of electronic modules with intermittently failing solder balls are diagnosed with code "no trouble found/could not reproduce." The SJ BIST soft-core offers a solution because it detects faults in monitored pins caused by fractured solder joints of programmed FPGAs on deployed electronic boards. At the end of the three-month HALT, selected FPGAs were subjected to die-and-pry and cross-section examination and comparison to the collected data. Analysis confirmed that SJ BIST did report the occurrence of faults on damaged pins, and SJ BIST did not report any false negatives. The HALT confirmed the efficacy, accuracy, and reliability of SJ BIST as both a prognostic and diagnostic tool for FPGAs in BGA type of packages.

关键词： solder joint solder balls FPGA BIST field programmable gate array HALT BGA

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A Design of Self-defect-compensatable Hardware neuron for Multi-layer Neural Networks

A Design of Self-defect-compensatable Hardware neuron for Mu...

引用

25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT)

作者： Yamamori, Kunihito Tashiro, Keisuke Kusano, Masamichi Yoshihara, Ikuo Univ Miyazaki Fac Engn Miyazaki Japan IIM Corp Tokyo Japan NTT Neomeit Corp Tokyo Japan

ISBN: (纸本)9780769542430

Neural network has a problem that learning time becomes so long for real world problems. To achieve fast learning, some researchers proposed to implement a neural network into Wafer Scale Integration (WSI). Since WSI uses one wafer as a parallel computer, a part of defect leads entire system fault. Therefore a defect compensation method is necessary to implement a neural network into WSI. Partial Retraining (PR) method has proposed as one of the defect compensation methods for neural network. However PR method is not verified whether it will perform well on digital hardware or not. It is also not clear how much is circuit required. In this paper we report a design of self-defect-compensatable neuron with PR method by VHDL, and evaluate it by simulations.

关键词： Neural network Partial retraining scheme field programmable gate array VHDL Defect compensation

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A STEP TOWARD 'PLUG AND PLAY' ROBOTICS WITH SoC TECHNOLOGY 13th

A STEP TOWARD 'PLUG AND PLAY' ROBOTICS WITH SoC TECHNOLOGY

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13th International Conference on Climbing and Walking Robots and the Support Technologies for Mobile Machines

作者： Soerensen, Anders Stengaard Falsig, Simon Ugilt, Rolf Univ Southern Denmark Maersk McKinney Moeller Inst DK-5230 Odense M Denmark

ISBN: (纸本)9789814327978

This article describes our progress toward simplifying and streamlining the low level systems integration of experimental robots, combining a System on Chip (SoC) approach with conventional modular approaches. The combined approach has increased flexibility, improved the embedded integration, and decreased the complexity of programming, compared to conventional modular approaches. We show the impact of the SoC approach in a simple demonstration and teaching model of a walking robot.

关键词： System on Chip (SoC) field programmable gate array I/O Interfacing Low Level Systems Integration Embedded

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