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A Run-Time Dynamic Reconfigurable Computing System for Lithium-Ion Battery Prognosis

ENERGIES 2016年第8期9卷 572页

作者： Wang, Shaojun Liu, Datong Zhou, Jianbao Zhang, Bin Peng, Yu Harbin Inst Technol Dept Automat Test & Control Harbin 150080 Peoples R China Imperial Coll London Dept Comp London SW7 2BZ England Univ South Carolina Coll Engn & Comp Columbia SC 29208 USA

As safety and reliability critical components, lithium-ion batteries always require real-time diagnosis and prognosis. This often involves a large amount of computation, which makes diagnosis and prognosis difficult to implement, especially in embedded or mobile applications. To address this issue, this paper proposes a run-time Reconfigurable Computing (RC) system on field programmable gate array (FPGA) for Relevance Vector Machine (RVM) to realize real-time Remaining Useful Life (RUL) estimation. The system leverages state-of-the-art run-time dynamic partial reconfiguration technology and customized computing circuits to balance the hardware occupation and computing efficiency. Optimal hardware resource consumption is achieved by partitioning the RVM algorithm according to a multi-objective optimization. Moreover, pipelined and parallel computation circuits for kernel function and matrix inverse are proposed on FPGA to further accelerate the computation. Experimental results with two different battery data sets show that, without sacrificing the RUL prediction performance, the embedded RC platform significantly reduces the computation time and the requirement of hardware resources. This demonstrates that complex prognostic tasks can be implemented and deployed on the proposed system, and it can be extended to the embedded computation of other machine learning algorithms.

关键词： field programmable gate array relevance vector machine lithium-ion battery remaining useful life

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A digital direction of arrival estimator based on fast on-line sequential random vector functional link network

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AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS 2021年 142卷 153986-153986页

作者： Raiguru, Priyadarshini Sahani, Mrutyunjaya Rout, Susanta Kumar Panda, Dhruba Charan Mishra, Rabindra Kishore Siksha O Anusandhan Deemed Univ Bhubaneswar Odisha India Berhampur Univ Elect Sci & Technol Berhampur Odisha India

This article develops a fast online sequential random vector functional network. In this network, input nodes are connected to both hidden nodes and output nodes. This architecture results in high-speed learning and testing. The network estimates the direction of arrival from signals received by the sparse array in real-time. Neither noisy signal nor effect of mutual coupling among array elements affect the estimation appreciably using the network. The network shows competitive performance in terms of learning speed, accuracy, short event regression time, simplicity, and robustness in comparison to other state-of-the-art methods such as support vector regression, extreme learning machine, and online sequential extreme learning machine. Finally, validation of the network translation into a hardware platform using a fast digital high-speed reconfigurable Xilinx Virtex-5 field-programmable gate array embedded processor for single-source detection completes the work. Comparison with reported measurement shows results with good accuracy and low root mean square error both by the network and its hardware-implemented platform. The direction of arrival estimation is thus possible using the network either through a computer or dedicated hardware as per necessity.

关键词： Fast online sequential random vector functional network Direction of arrival Support vector regression Extreme learning machine Online sequential extreme learning machine field programmable gate array

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An Efficient and High-Speed Implementation of QRD-MGS Algorithm for STAP Application Based on Floating Point FPGAs

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2020年第3期29卷

作者： Hasanikhah, Narjes Amin-Nejad, Siavash Darvish, Ghafar Moniri, M. R. Islamic Azad Univ Sci & Res Branch Dept Elect & Comp Engn Tehran *** Iran Univ Guilan Dept Elect Engn Rasht *** Iran Islamic Azad Univ Yadegar E Emam Branch Dept Elect Engn Tehran *** Iran

Space-Time Adaptive Processing (STAP) can harness the efficacy of interference and clutter significantly. Calculations of the STAP weights involve solving linear equations which require very intensive computations. In this paper, the QR decomposition (QRD) using the modified gram-schmidt (MGS) algorithm is parameterized with vector size to create a trade-off between the hardware resources utilization and computation time. To achieve an efficient floating point structure, the proposed architecture of QRD-MGS algorithm is simulated and implemented in two modes: single-vector and multi-vector. Results show that the multi-vector method can lead to a high-performance design with higher operating frequency, lower power consumption, and less resource utilization than the single-vector method. For example, Modelism simulations show that the decomposition of a 12x51 matrix with vector size of 17 takes 7.86 mu s with the maximum clock frequency of 282MHz, for implementation on the Arria10 FPGA. In real STAP applications, the matrix sizes are too large to be fit on FPGAs and the update rate of the weights are high. Therefore, this method can fit any matrix in the contemporary FPGAs with an acceptable update rate.

关键词： field programmable gate array implementation QR decomposition space-time adaptive processing

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Two-dimensional mechanically resonating fiber optic scanning display system

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OPTICAL ENGINEERING 2010年第9期49卷 097401-097401页

作者： Wang, Wei-Chih Tsui, Chi-Leung Univ Washington Dept Mech Engn Seattle WA 98195 USA Univ Washington Dept Elect Engn Seattle WA 98195 USA

A microdisplay system based on an optical fiber driven by a 2-D piezoelectric actuator is presented. An optical fiber is extended from the free end of a 2-D piezoelectric actuator (free length 4.3 mm). A field programmable gate array (FPGA) drives the actuator using a triangular waveform to deflect the optical fiber in orthogonal directions. The FPGA also controls a LED light source, and the light is coupled into a chemically tapered single-mode fiber (SMF-28, core diameter 10 mu m). At a preset pairing of near-resonance frequencies (horizontal 22 Hz, vertical 5070 Hz), the deflected optical fiber in combination with controlled light produces an output image with an approximate dimension of 0.1 x 0.1 mm(2), and a potential resolution of 400 lines per scan. This work details the design and fabrication of the microdisplay system. The mechanical and optical design for the microresonating scanner is discussed. In addition, the mechanical and optical performance and the resulting output of the 2-D scanner is presented. (C) 2010 Society of Photo-Optical Instrumentation Engineers. [DOI: 10.1117/1.3487745]

关键词： optical display system optical scanner field programmable gate array

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Tunable FPGA Bitstream Obfuscation with Boolean Satisfiability Attack Countermeasure

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ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2020年第2期25卷 19-19页

作者： Olney, Brooks Karam, Robert 4202 E Fowler Ave ENG 030 Tampa FL 33620 USA

field programmable gate arrays (FPGAs) are seeing a surge in usage in many emerging application domains, where the in-field reconfigurability is an attractive characteristic for diverse applications with dynamic design requirements, such as cloud computing, automotive, IoT, and aerospace. The security of the FPGA configuration file, or bitstream, is critical, especially for devices with long in-field lifetimes, where attackers may attempt to extract valuable Intellectual Property (IP) from within. In this article, we propose a tunable obfuscation approach that protects IP from typical bitstream attacks while enabling designers to trade off security with acceptable overhead. We also consider two potential attacks on this protection mechanism: Boolean SAT Attacks on the obfuscation and removal attacks on the protection circuitry. The obfuscation and SAT countermeasure are integrated in a custom CAD framework within a commercial FPGA toolflow and together provide mathematically strong protection against common bitstream attacks. Further, we quantify the difficulty of a removal attack on the protection circuitry through pattern matching and direct bitstream manipulation. The average area, power, and delay overhead for obfuscation with 95% mismatch probability are 18%, 16%, and 8%, respectively, for small combinational circuits, and 1%, 2%, and 5% for larger arithmetic modules.

关键词： field programmable gate array obfuscation SAT attack removal attack overheads

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Accelerating string set matching in FPGA hardware for Bioinformatics research

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BMC BIOINFORMATICS 2008年第1期9卷 197-197页

作者： Dandass, Yoginder S. Burgess, Shane C. Lawrence, Mark Bridges, Susan M. Mississippi State Univ Inst Digital Biol Mississippi State MS 39762 USA Mississippi State Univ Dept Comp Sci & Engn Mississippi State MS 39762 USA Mississippi State Univ Life Sci & Biotechnol Inst Coll Vet Med Mississippi State MS 39762 USA Mississippi State Univ Dept Basic Sci Mississippi State MS 39762 USA

Background: This paper describes techniques for accelerating the performance of the string set matching problem with particular emphasis on applications in computational proteomics. The process of matching peptide sequences against a genome translated in six reading frames is part of a proteogenomic mapping pipeline that is used as a case-study. The Aho-Corasick algorithm is adapted for execution in field programmable gate array (FPGA) devices in a manner that optimizes space and performance. In this approach, the traditional Aho-Corasick finite state machine (FSM) is split into smaller FSMs, operating in parallel, each of which matches up to 20 peptides in the input translated genome. Each of the smaller FSMs is further divided into five simpler FSMs such that each simple FSM operates on a single bit position in the input (five bits are sufficient for representing all amino acids and special symbols in protein sequences). Results: This bit-split organization of the Aho-Corasick implementation enables efficient utilization of the limited random access memory (RAM) resources available in typical FPGAs. The use of on-chip RAM as opposed to FPGA logic resources for FSM implementation also enables rapid reconfiguration of the FPGA without the place and routing delays associated with complex digital designs. Conclusion: Experimental results show storage efficiencies of over 80% for several data sets. Furthermore, the FPGA implementation executing at 100 MHz is nearly 20 times faster than an implementation of the traditional Aho-Corasick algorithm executing on a 2.67 GHz workstation.

关键词： field programmable gate array Finite State Machine Random Access Memory Peptide Match Deterministic Finite Automaton

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FPGA-Based Online PQD Detection and Classification through DWT, Mathematical Morphology and SVD

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ENERGIES 2018年第4期11卷 769页

作者： Lopez-Ramire, Misael Cabal-Yepez, Eduardo Ledesma-Carrillo, Luis M. Miranda-Vidales, Homero Rodriguez-Donate, Carlos Lizarraga-Morales, Rocio A. Univ Guanajuato Div Ingn Campus Irapuato Salamanca Guanajuato 36700 Mexico Univ Autonoma San Luis Potosi Fac Ingn Av Manuel Nava 8 San Luis Potosi 78290 Mexico

Power quality disturbances (PQD) in electric distribution systems can be produced by the utilization of non-linear loads or environmental circumstances, causing electrical equipment malfunction and reduction of its useful life. Detecting and classifying different PQDs implies great efforts in planning and structuring the monitoring system. The main disadvantage of most works in the literature is that they treat a limited number of electrical disturbances through personal computer (PC)-based computation techniques, which makes it difficult to perform an online PQD classification. In this work, the novel contribution is a methodology for PQD recognition and classification through discrete wavelet transform, mathematical morphology, decomposition of singular values, and statistical analysis. Furthermore, the timely and reliable classification of different disturbances is necessary;hence, a field programmable gate array (FPGA)-based integrated circuit is developed to offer a portable hardware processing unit to perform fast, online PQD classification. The obtained numerical and experimental results demonstrate that the proposed method guarantees high effectiveness during online PQD detection and classification of real voltage/current signals.

关键词： artificial neural networks discrete wavelet transform field programmable gate array mathematical morphology power quality disturbance singular value decomposition

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FPGA Implementation of Image Registration Using Accelerated CNN

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SENSORS 2023年第14期23卷 6590-6590页

作者： Aydin, Seda Guzel Bilge, Hasan Sakir Bingol Univ Dept Elect & Elect Engn TR-12000 Bingol Turkiye Gazi Univ Biomed Calibrat & Res Ctr BIYOKAM TR-06560 Ankara Turkiye

Background: Accurate and fast image registration (IR) is critical during surgical interventions where the ultrasound (US) modality is used for image-guided intervention. Convolutional neural network (CNN)-based IR methods have resulted in applications that respond faster than traditional iterative IR methods. However, general-purpose processors are unable to operate at the maximum speed possible for real-time CNN algorithms. Due to its reconfigurable structure and low power consumption, the field programmable gate array (FPGA) has gained prominence for accelerating the inference phase of CNN applications. Methods: This study proposes an FPGA-based ultrasound IR CNN (FUIR-CNN) to regress three rigid registration parameters from image pairs. To speed up the estimation process, the proposed design makes use of fixed-point data and parallel operations carried out by unrolling and pipelining techniques. Experiments were performed on three US datasets in real time using the xc7z020, and the xcku5p was also used during implementation. Results: The FUIR-CNN produced results for the inference phase 139 times faster than the software-based network while retaining a negligible drop in regression performance of under 200 MHz clock frequency. Conclusions: Comprehensive experimental results demonstrate that the proposed end-to-end FPGA-based accelerated CNN achieves a negligible loss, a high speed for registration parameters, less power when compared to the CPU, and the potential for real-time medical imaging.

关键词： accelerated CNN field programmable gate array image registration ultrasound

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Error estimation and enhanced stiffness sensitivity in contact resonance force microscopy with a multiple arbitrary frequency lock-in amplifier (MAFLIA)

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MEASUREMENT SCIENCE AND TECHNOLOGY 2020年第11期31卷 115009-115009页

作者： Flater, Erin E. Mugdha, Arya C. Gupta, Saurabh Hudson, William A. Fahrenkamp, Abbigail A. Killgore, Jason P. Wilson, Jesse W. Luther Coll Dept Phys Decorah IA 52101 USA Colorado State Univ Dept Elect & Comp Engn Ft Collins CO 80521 USA NIST Appl Chem & Mat Div Boulder CO 80305 USA Colorado State Univ Sch Biomed Engn Ft Collins CO 80521 USA

In contact resonance force microscopy and related dynamic atomic force microscopy methods, an accurate description of the real-time cantilever dynamics is essential to the mapping of local material properties, such as viscoelasticity, piezo response, and chemical composition. Stiffness and damping variations of the tip-sample contact result in variations in the cantilever's resonance frequency and quality factor as it scans a sample of interest. When measuring characteristics of the resonance, generally, there is a tradeoff between full spectral coverage, best obtained by sweeping the amplitude versus frequency response in the time or frequency domain, and high-speed information, obtained by observing the cantilever response at one or two discrete frequencies, that may be required to track a resonance frequency that changes spatially. Here, we introduce a new option for performing contact resonance force microscopy with a low-cost multifrequency lock-in amplifier system with up to eight simultaneous independent excitation and detection frequencies. We demonstrate how the multifrequency approach can measure contact resonance frequency, quality factor, amplitude, and phase during imaging, with high precision and error estimation, without the need for frequency-tracking feedback. We show, using a wood composite sample, that this multifrequency approach can determine resonance frequency and quality factor, and associated uncertainty. This ability to estimate uncertainty of resonance parameters is not possible with 1 and 2 frequency methods. We further utilize the multifrequency lock-in to develop a novel means of increasing the stiffness range for highly sensitive nanomechanical sensing by dividing the eight lock-in frequencies to monitor two or four simultaneous eigenmodes, each of which is optimized for sensitivity in a particular stiffness regime. Overall, we show how multifrequency lock-in amplifiers with observation frequency chosen to coincide with an expected eig

关键词： atomic force microscopy contact resonance force microscopy lock-in amplifier field programmable gate array multifrequency AFM digital signal processing

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A neural network accelerated optimization method for FPGA

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JOURNAL OF COMBINATORIAL OPTIMIZATION 2024年第5期47卷 84-84页

作者： Hu, Zhengwei Zhu, Sijie Wang, Leilei Cao, Wangbin Xie, Zhiyuan North China Elect Power Univ Dept Elect & Commun Engn Baoding 071003 Peoples R China

A neural network accelerated optimization method for FPGA hardware platform is proposed. The method realizes the optimized deployment of neural network algorithms for FPGA hardware platforms from three aspects: computational speed, flexible transplantation, and development methods. Replacing multiplication based on Mitchell algorithm not only breaks through the speed bottleneck of neural network hardware acceleration caused by long multiplication period, but also makes the parallel acceleration of neural network algorithm get rid of the dependence on the number of hardware multipliers in FPGA, which can give full play to the advantages of FPGA parallel acceleration and maximize the computing speed. Based on the configurable strategy of neural network parameters, the number of network layers and nodes within layers can be adjusted according to different logical resource of FPGA, improving the flexibility of neural network transplantation. The adoption of HLS development method overcomes the shortcomings of RTL method in designing complex neural network algorithms, such as high difficulty in development and long development cycle. Using the Cyclone V SE 5CSEBA6U23I7 FPGA as the target device, a parameter configurable BP neural network was designed based on the proposed method. The usage of logical resources such as ALUT, Flip-Flop, RAM, and DSP were 39.6%, 40%, 56.9%, and 18.3% of the pre-optimized ones, respectively. The feasibility of the proposed method was verified using MNIST digital recognition and facial recognition as application scenarios. Compare to pre-optimization, the test time of MNIST number recognition is reduced to 67.58%, and the success rate was lost 0.195%. The test time for facial recognition applications was reduced to 69.571%, and the success rate of combining LDA algorithm was lost within 4%.

关键词： field programmable gate array Neural network Hardware acceleration Mitchell algorithm High-level synthesis

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