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检索条件"主题词=Field Programmable Gate array"

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FPGA-Realization of a Sensorless Speed Control IC for IPMSM Drive

FPGA-Realization of a Sensorless Speed Control IC for IPMSM ...

引用

36th Annual Conference of the IEEE Industrial-Electronics-Society (IECON)/4th IEEE International Conference on E-Learning in Industrial Electronics/IES Industry Forum

作者： Kung, Ying-Shieh Huang, Chung-Chun Huang, Liang-Chiao So Taiwan Univ Dept Elect Engn Taipei Taiwan Ind Technol Res Inst Green Energy & Environm Res Labs Hsinchu Taiwan

ISBN: (纸本)9781424452262

Based on FPGA (field programmable gate array) technology, the realization of a sensorless control IC for IPMSM (Interior Permanent Magnet Synchronous Motor) drive is presented in this paper. Firstly, a mathematical model for IPMSM is derived and an extended EMF (Electro-Motive Force) or EEMF is defined. Secondly, a rotor position is estimated by using a sliding mode observer (SMO). These estimated values are feed-backed to the current loop for vector control and to the speed loop for speed control. Thirdly, an FSM (Finite State Machine) method is adopted to describe the overall SMO-based rotor position estimator. Further, using novel FPGA technology, the realization of a sensorless speed control IC is also described. At last, an experimental system is established to verify the effectiveness of the proposed sensorless speed control IC, and some experimental results are confirmed theoretically.

关键词： FPGA realization IPMSM drive electric potential extended electromotive force field programmable gate array field programmable gate arrays finite state machine finite state machines interior permanent magnet synchronous motor permanent magnet motors rotor position estimator rotors sensorless machine control sensorless speed control integrated circuit sliding mode observer synchronous motor drives variable structure systems vector control velocity control

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Acceleration of feature extraction for FPGA based speech recognition

Acceleration of feature extraction for FPGA based speech rec...

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Conference on Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2010

作者： Arminas, Vytautas Tamulevicius, Gintautas Navakauskas, Dalius Ivanovas, Edgaras Vilnius Gediminas Tech Univ Dept Elect Syst Naugarduko Str 41 Vilnius Lithuania Inst Math & Informat Recognit Proc Dept Vilnius Lithuania

ISBN: (纸本)9780819482358

The paper describes a field programmable gate array implementation of the main part of speech recognition system - feature extraction. In order to accelerate recognition the whole cepstral analysis scheme is implemented in hardware by the use of intellectual property cores. Two field programmable gate array devices are used for evaluation. Comparative experimental results of four different implementations are presented. They grounds achieved 29 times faster speech analysis in comparison with software based analysis subsystem.

关键词： field programmable gate array feature extraction cepstral analysis speech recognition

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Real-Time Fault Diagnostics for a Permanent Magnet Synchronous Motor Drive for Aerospace Applications

Real-Time Fault Diagnostics for a Permanent Magnet Synchrono...

引用

IEEE Energy Conversion Congress and Exposition (ECCE)

作者： Odavic, Milijana Sumner, Mark Wheeler, Pat Li, Jing Univ Nottingham Univ Pk Nottingham NG7 2RD England

ISBN: (纸本)9781424452873

This paper describes the development and implementation of a permanent magnet synchronous machine controller for safety critical applications which embeds independent real-time mechanical-fault diagnostics into the drive controller. The drive is intended for aerospace applications and therefore must employ an ASIC or FPGA as the main control "processor" to provide a more suitable route to flight-product certification. Motor Current Signature Analysis (MCSA) is employed to indicate the development or existence of faults within the drive system and this is achieved by embedding a real-time frequency analysis of the motor current within the FPGA, operating independently of the motor control. Experimental results are provided to validate the proposed control and condition monitoring.

关键词： field programmable gate array permanent magnet motor fault diagnosis aircraft maintenance

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A System on Chip approach to enhanced learning in interdisciplinary robotics

A System on Chip approach to enhanced learning in interdisci...

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IEEE/RSJ International Conference on Intelligent Robots and Systems

作者： Sorensen, Anders Stengaard Falsig, Simon Univ So Denmark Maersk Mc Kinney Moller Inst DK-5230 Odense M Denmark

ISBN: (纸本)9781424466757

To sustain advanced interdisciplinary teaching and learning in the rapidly growing and diversifying field of robotics, we have successfully employed FPGA based System on Chip (SoC) technology to provide abstraction between high level software and low level I/O- and control hardware. Our approach is to provides students with a simple FPGA based framework for hardware access, and hardware I/O development, which is independent of computer platform and programming language, and enable the students to add to, or change I/O hardware in accordance with their skills. We have tested the framework in an embedded systems course and various student projects, and have found that it greatly enhance the students abilities to control hardware from software, and dramatically reduce the time spent on software <-> hardware interfacing. As the framework is also scalable, it can support projects from controlling a single LED, to complex modular and aggregated robots with demands for high bandwidths and low jitter in the control loop.

关键词： FPGA control engineering education control hardware educational courses embedded systems embedded systems course field programmable gate array field programmable gate arrays hardware I-O development hardware access interdisciplinary robotics programming language robots student project system on chip system-on-chip teaching

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FPGA-based Embedded System for Ultrasonic Positioning

FPGA-based Embedded System for Ultrasonic Positioning

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IEEE International Symposium on Industrial Electronics (ISIE)

作者： Sanchez, Alberto de Castro, Angel Glez-de-Rivera, Guillermo Garrido, Javier Univ Autonoma Madrid HCTLab Madrid Spain

ISBN: (纸本)9781424463916

This paper presents an FPGA-based ultrasonic location system. This system uses low-cost FPGAs and ultrasonic transducers to provide 3-D location to mobile nodes in an indoor environment. Synchronization is reached using the radiofrequency transducers that mobile nodes usually include. FPGAs have been used to sample ultrasonics and radiofrequency inside a custom peripheral which is attached to a MicroBlaze soft-processor. The calculus of the position of the mobile node is accomplished inside this processor.

关键词： field programmable gate array location ultrasonics trilateration

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From Petri net models to C implementation of digital controllers

From Petri net models to C implementation of digital control...

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IEEE International Symposium on Industrial Electronics (ISIE)

作者： Gomes, Luis Rebelo, Rogerio Barros, Joao Paulo Costa, Aniko Pais, Rui Univ Nova Lisboa Fac Ciencias & Tecnol P-1200 Lisbon Portugal Univ Nova Lisboa Ctr Tecnol & Sistemas Lisbon Portugal Inst Politecn Beja Escola Sup Technol & Gestao Lisbon Portugal

ISBN: (纸本)9781424463916

This work presents a tool for automatic generation of controllers' implementation code from Petri nets models amenable to be deployed into common platforms using widely used high level programming languages, such as C, C++, and Java. The generated code is linked with platform specific functions, supporting different types of implementation platforms, ranging from low-cost microcontrollers to workstations, and including microcontroller IPs (Intellectual Property) to be embedded into FPGAs (field programmable gate arrays). The system controller behavior is modeled using IOPT (Input-Output Place-Transition) Petri Nets models, which are represented through PNML (Petri nets Mark-up Language) notation. A tool for automatic code generation was developed, which achieved this goal in cooperation with other developed tools within a model-based development framework. Application to an automation system composed by a set of distributed controllers is presented.

关键词： C implementation C++ language Java Java PNML Petri nets Petri nets mark-up language automatic code generation automatic generation digital control digital controller field programmable gate array field programmable gate arrays high level programming languages input output place transition intellectual property low cost microcontroller microcontrollers model based development framework platform specific functions program compilers system controller behavior

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Reconstruction Algorithm Realization with FPGA based on the emission spectral tomography

Reconstruction Algorithm Realization with FPGA based on the ...

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5th International Symposium on Advanced Optical Manufacturing and Testing Technologies - Optical Test and Measurement Technology and Equipment

作者： Leng, Biyan Wan, Xiong Zhang, Zhimin Deng, Xiaoming Luo, Ningning Nanchang Hangkong Univ Key Lab Nondestruct Test Minist Educ Nanchang 330063 Peoples R China

ISBN: (纸本)9780819480866

Reconstruction for Emission Spectral Tomography(EST) is based on thick and fast digital signal processing all along, and the computation quantity is astronomical. With the acknowledgement of SIRT, the parallel computing of FPGA and the flexibility of NIOS II high-speed computing power are well used. Through the hardware description language VERILOG HDL and costuming macros module as well as the embedded system NIOS II, then achieved the purpose of the reconstruction for EST.

关键词： Emission Spectral Tomography field programmable gate array Simultaneous Iterative Reconstruction Technique NIOS II

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A Simple & Cost-Effective Novel Methodology for Predicting SSN System Performance for Different PCB Trace Lengths

A Simple & Cost-Effective Novel Methodology for Predicting S...

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IEEE Electrical Design of Advanced Package and Systems Symposium

作者： Ang, Chun Wooi Lo, Wei Wei Wong, Man On Plot 6 Bayan Lepas Technoplex Bayan Lepas 11900 Penang Malaysia

ISBN: (纸本)9781424490684

High data rates, high clock speeds, and low power consumption are synonymous with advanced electronic devices. Consequently, simultaneous switching noise (SSN) is emerging as a critical side-effect of toggling signals within an electronic device because SSN affects signal integrity. Even minute changes in signal voltage in the order of a few millivolts can adversely affect the functioning of a circuit. A PCB typically forms the communication backbone between electronic components including field programmable gate array (FPGA) devices. Signal quality and SSN effects vary with PCB trace lengths. Traditionally, complex board models are used to simulate the SSN characteristics of electronic devices for different PCBs, which can be time consuming and expensive. This paper presents a cost-effective novel methodology for de-embedding the PCB trace effect to accurately characterize an FPGA device's intrinsic SSN characteristics. The methodology uses simple and fast measurement and simulation techniques to de-embed the PCB trace effect for different PCB trace lengths. The predicted SSN data for different PCB trace lengths and intrinsic SSN data obtained using this methodology will be useful to FPGA system designers.

关键词： FPGA device FPGA system designer PCB trace effect PCB trace length SSN system performance prediction advanced electronic device communication backbone complex board model critical side-effect electronic component field programmable gate array field progra

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Acceleration of FPGA-based ICA processor for real-time processing

Acceleration of FPGA-based ICA processor for real-time proce...

引用

2010 IEEE International Symposium Antennas and Propagation/CNC-USNC/URSI Radio Science Meeting

作者： Fujio, Shunsuke Shiomi, Hidehisa Okamura, Yasuyuki Osaka Univ Grad Sch Engn Sci Suita Osaka 565 Japan

This paper describes about designing of the architecture of the fastICA for FPGA, and it can check that it is possible to perform ICA processing in real-time for transmission of the QPSK signals of more than 1 Mbps.

ISBN: (纸本)9781424449682

关键词： FPGA-based ICA processor QPSK signals fast ICA algorithm field programmable gate array field programmable gate arrays independent component analysis independent component analysis quadrature phase shift keying quadrature phase shift keying real-time processing

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HALT Evaluation of SJ BIST Technology for Electronic Prognostics

HALT Evaluation of SJ BIST Technology for Electronic Prognos...

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AUTOTESTCON 2010 Systems Readiness Technology Conference

作者： Hofmeister, James P. Vohnout, Sonia Mitchell, Christopher Heimes, Felix O. Saha, Sambit Ridgetop Grp Inc 6595 N Oracle Rd Tucson AZ 85704 USA BAE Syst Platform Solt Johnstown NY 13790 USA

ISBN: (纸本)9781424479597

This paper presents the design, test, and results of a highly accelerated life test (HALT) evaluation of a soft-core called Solder Joint Built-in Self-Test T (SJ BIST (TM)), a method for detecting faults caused by solder-joint fractures in monitored input/output (I/O) pins of field programmable gate array (FPGA) devices, especially those in ball grid array (BGA) type of packages. Modern electronics utilize large FPGAs packages attached to electronic boards by means of solder joints, such as solder balls, between the package and the board. Thermo-mechanical stresses - primarily heat and vibration - cause fatigue damage and eventual fracture failure of one or more balls, which causes intermittent operational faults leading to catastrophic failures in critical systems. Such intermittent faults are difficult to reproduce on a test bench and many field returns of electronic modules with intermittently failing solder balls are diagnosed with code "no trouble found/could not reproduce." The SJ BIST soft-core offers a solution because it detects faults in monitored pins caused by fractured solder joints of programmed FPGAs on deployed electronic boards. At the end of the three-month HALT, selected FPGAs were subjected to die-and-pry and cross-section examination and comparison to the collected data. Analysis confirmed that SJ BIST did report the occurrence of faults on damaged pins, and SJ BIST did not report any false negatives. The HALT confirmed the efficacy, accuracy, and reliability of SJ BIST as both a prognostic and diagnostic tool for FPGAs in BGA type of packages.

关键词： solder joint solder balls FPGA BIST field programmable gate array HALT BGA

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