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检索条件"主题词=Field Programmable Gate array"

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Slope-Based Point Pursuing Maneuvers of Nonholonomic Robots using FPGA

Slope-Based Point Pursuing Maneuvers of Nonholonomic Robots ...

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IEEE/RSJ International Conference on Intelligent Robots and Systems

作者： Yu, Ying-Hao Kodagoda, S. Ha, Q. P. Univ Technol Sydney Fac Engn & Informat Technol ARC Ctr Excellence Autonomous Syst CAS Broadway NSW 2007 Australia

ISBN: (纸本)9781424466757

Steering maneuver is essential in robotic motion planning. Despite a lot of steering mechanisms successfully developed in past years, for miniature robots, real-time computation is still a limitation for robot path tracking. The design issues in cooperative control of battery-powered nonholonomic robots rest with the complicacy of the control strategies, the low power consumption and real-time processing capability. Conventionally, the improvement of computing speed mostly relies on the increment of the system clock and often results in some transient loss. Thus, an elaborate control algorithm developed for PC might not work on an embedded system. This paper presents a comprehensive steering algorithm which, via issuing predicaments for computation, will dramatically reduce the resource usage in hardware circuit design. The proposed algorithm is implemented on an embedded system for ubiquitous robotics using the field programmable gate array (FPGA) technology.

关键词： FPGA battery powered nonholonomic robots comprehensive steering algorithm elaborate control algorithm embedded system field programmable gate array field programmable gate arrays hardware circuit design miniature robots mobile robots motion control nonholonomic robots real-time computation robot path tracking robotic motion planning slope based point pursuing maneuvers steering maneuver steering mechanisms steering systems ubiquitous robotics

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Generation, encoding and presentation of content on holographic displays in real time

Generation, encoding and presentation of content on holograp...

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Conference on Three-Dimensional Imaging, Visualization, and Display 2010 and Display Technologies and Applications for Defence, Security, and Avionics IV

作者： Zschau, Enrico Missbach, Robert Schwerdtner, Alexander Stolle, Hagen SeeReal Technol GmbH D-01307 Dresden Germany

ISBN: (纸本)9780819481542

This paper discusses our solution for driving holographic displays with interactive or video content encoded in real-time by using SeeReal's Sub-Hologram-technology in combination with off-the-shelf-hardware. Guidelines for correctly creating complex content including aspects regarding transparency in holograms from both the content side and the holography side are presented. The conventional approaches for generating computer generated holograms are discussed in comparison with our solution using Sub-Holograms, to rapidly reduce computation power. Finally the computing-platform and the specification of our 20 inch direct-view holographic prototype will be presented.

关键词： 3D-displays Holographic displays 3D-content Real-time holography Computer generated holograms Sub-Holograms Graphics processing unit field programmable gate array

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A Simple Pipelined Logarithmic Multiplier

A Simple Pipelined Logarithmic Multiplier

引用

IEEE International Conference on Computer Design

作者： Bulic, Patricio Babic, Zdenka Avramovic, Aleksej Univ Ljubljana Fac Comp & Informat Sci Ljubljana 61000 Slovenia Univ Banja Luka Fac Elect Engn Banja Luka Bosnia & Herceg

ISBN: (纸本)9781424489350

Digital signal processing algorithms often rely heavily on a large number of multiplications, which is both time and power consuming. However, there are many practical solutions to simplify multiplication, like truncated and logarithmic multipliers. These methods consume less time and power but introduce errors. Nevertheless, they can be used in situations where a shorter time delay is more important than accuracy. In digital signal processing, these conditions are often met, especially in video compression and tracking, where integer arithmetic gives satisfactory results. This paper presents and compare different multipliers in a logarithmic number system. For the hardware implementation assessment, the multipliers are implemented on the Spartan 3 FPGA chip and are compared against speed, resources required for implementation, power consumption and error rate. We also propose a simple and efficient logarithmic multiplier with the possibility to achieve an arbitrary accuracy through an iterative procedure. In such a way, the error correction can be done almost in parallel (actually this is achieved through pipelining) with the basic multiplication. The hardware solution involves adders and shifters, so it is not gate and power consuming. The error of proposed multiplier for operands ranging from 8 bits to 16 bits indicates a very low relative error percentage.

关键词： Spartan 3 FPGA chip digital signal processing field programmable gate array field programmable gate arrays iterative methods iterative procedure logarithmic number system pipelined logarithmic multiplier signal processing truncated multiplier video compression video tracking

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FPGA Implementation of a 16-Channel Lock-in Laser Light Scattering System

FPGA Implementation of a 16-Channel Lock-in Laser Light Scat...

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7th IEEE Electronics, Robotics and Automotive Mechanics Conference (CERMA)

作者： Moreno-Baez, Arturo Miramontes-de Leon, Gerardo Sifuentes-Gallardo, Claudia Garcia-Dominguez, Ernesto Alaniz-Lumbreras, Daniel Huerta-Ruelas, Jorge A. Univ Autonoma Zacatecas Lab PDS Lopez Velarde 801 Zacatecas Zac Mexico IPN Grp Mecatron CICATA Queretaro Qro Mexico

ISBN: (纸本)9780769542041

The use of optical techniques for the measurement and characterization of physical phenomena is of great interest in the scientific and industrial communities. This work shows the implementation of an integrated system for measuring Multi-angle Laser Light Scattering on a field programmable gate array. The embedded design delivers a compact and highly competitive system. The system is able to display, in real-time, the light intensity from a photo-detector array showing in this way the corresponding pattern distribution of the scattered light at 16 sensing points. Some laser light scattering patterns from metallic samples with different roughness are shown.

关键词： 16-channel lock-in laser light scattering system FPGA FPGA embedded design field programmable gate array field programmable gate arrays integrated circuit testing light intensity light scattering light scattering lock-in amplifier measurement by laser bea

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FPGA-based Real-time Calculation of the Harmonic Impedance of Series Resonant Inductive Loads

FPGA-based Real-time Calculation of the Harmonic Impedance o...

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36th Annual Conference of the IEEE Industrial-Electronics-Society (IECON)/4th IEEE International Conference on E-Learning in Industrial Electronics/IES Industry Forum

作者： Jimenez, O. Barragan, L. A. Navarro, D. Lucia, O. Artigas, J. I. Urriza, I. Univ Zaragoza Dept Ingn Elect & Comunicac Zaragoza 50018 Spain

ISBN: (纸本)9781424452262

This paper presents a field programmable gate array (FPGA) implementation of a digital circuit that measures in real- time the first harmonic load impedance of medium-frequency (25 kHz - 70 kHz) induction heating cooking appliances. The load impedance of a planar inductor coupled to a pan depends on the geometry, pan material, temperature, and frequency. Real-time load measurement is desirable for a proper control of the inverter. The Goertzel algorithm is implemented to calculate the Discrete Fourier Transform (DFT) of the inverter output voltage and load current over a half mains period. From the real and imaginary amplitudes of the harmonics of voltage and current, the load impedance at those harmonics can be computed. The algorithm has been developed using a hardware description language (HDL). The digital circuit, the power converter, the signal conditioning circuits, and the sigma-delta modulators are simulated as a whole using a mixed-signal simulation tool. From these simulations the accuracy of the method can be evaluated when first order sigma-delta converters are used to sense voltage and current. Finally, the simulations are experimentally verified.

关键词： FPGA-based FPGA-based real-time calculation Goertzel algorithm digital circuit digital circuits discrete Fourier transform discrete Fourier transforms domestic appliances field programmable gate array field programmable gate arrays first order sigma-delta converters frequency 25 kHz to 70 kHz hardware description language hardware description languages induction heating inverter control inverter output voltage medium-frequency induction heating cooking appliances mixed-signal simulation tool pan material planar inductor power converter power convertors real-time load measurement series resonant inductive load harmonic impedance sigma-delta modulation sigma-delta modulators signal conditioning circuits signal conditioning circuits

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Baseband MIMO receiver architecture for MC-CDMA and its FPGA implementation

Baseband MIMO receiver architecture for MC-CDMA and its FPGA...

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6th Annual IEEE International Conference on Wireless and Mobile Computing, Networking and Communications (WiMob)/STMWC/NASSUE/CMPA/VECON/AWSAN/AWSAN

作者： LaRoche, Isabelle Roy, Sebastien Fortier, Paul Beaumont, Jean-Francois Univ Laval Dept Elect & Comp Engn Quebec City PQ G1V 0A6 Canada Def Res Dev Canada Ottawa ON K1A 0Z4 Canada

ISBN: (纸本)9781424477425

A baseband multi-input, multi-output (MIMO) multi-carrier code division multiple access (MC-CDMA) downlink system meeting wideband CDMA (WCDMA) bandwidth requirements is simulated and its receiver part is implemented into a field programmable gate array (FPGA). The receiver was designed by integrating an existing single-input, single-output (SISO) fixed-point MC-CDMA receiver with an existing floating-point MIMO receiver. The receiver employs temporal multiplexing in order to use a single Vertical Bell Laboratories LAyered Space-Time (V-BLAST) detector. Simulation results of a complete MIMO MC-CDMA system show improvements over the SISO case. Implementation results show that it is possible to implement this receiver design into a single FPGA device.

关键词： FPGA MIMO communication V-BLAST detector Vertical Bell Laboratories layered space-time detector WCDMA baseband MIMO receiver architecture code division multiple access field programmable gate array field programmable gate arrays floating-point MIMO receiver multicarrier code division multiple access downlink system multiple-input multiple-output receiver radio receivers single-input single-output fixed-point MC-CDMA receiver temporal multiplexing wideband CDMA

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Soft-Core Embedded Processor-Based Built-In Self-Test of FPGAs: A Case Study

Soft-Core Embedded Processor-Based Built-In Self-Test of FPG...

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42nd South Eastern Symposium on System Theory

作者： Dutton, Bradley F. Stroud, Charles E. Auburn Univ Dept Elect & Comp Engn Auburn AL 36849 USA

ISBN: (纸本)9781424456925

This paper presents the results of a case study which investigates the use of an embedded soft-core processor to perform Built-In Self-Test (BIST) of the logic resources in Xilinx Virtex-5 field programmable gate arrays (FPGAs). We show that the approach reduces the complexity of an external BIST controller and the number of external reconfigurations, making it particularly appealing for in-system testing of high-reliability and fault-tolerant systems with FPGAs. However, the overall test time is not improved due to an increase in the size of the required configuration files as a consequence of the inclusion of the softcore embedded processor logic, whose relative irregularity results in less effective compression of configuration data files.

关键词： Built-In Self-Test field programmable gate array System-Test Fault Tolerance Virtex-5

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Prototype of a wearable system for remote fetal monitoring during pregnancy

Prototype of a wearable system for remote fetal monitoring d...

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32nd Annual International Conference of the IEEE Engineering-in-Medicine-and-Biology-Society (EMBC 10)

作者： Fanelli, Andrea Ferrario, Manuela Piccini, Luca Andreoni, Giuseppe Matrone, Giulia Magenes, Giovanni Signorini, Maria G. Politecn Milan Dipartimento Bioingn Piazza Leonardo da Vinci 32 I-20133 Milan Italy Sensibilab I-23900 Lecce Italy Politecn Milan Indaco Dept Sensibilab I-20158 Milan Italy Univ Pavia Dipartimento Informat & Sistemist I-27100 Pavia Italy Politecn Milan Dipartimento Bioingn I-20133 Milan Italy

ISBN: (纸本)9781424441242

Fetal Heart Rate( FHR) monitoring gives important information about the fetus health state during pregnancy. This paper presents a new prototype for remote fetal monitoring. The device will allow to monitor FHR in a domiciliary context and to send fetal ECG traces to a hospital facility, where clinicians can interpret them. In this way the mother could receive prompt feedback about fetal wellbeing. The system is characterized by two units:( i) a wearable unit endowed with textile electrodes for abdominal ECG recordings and with a field programmable gate array( FPGA) board for fetal heart rate( FHR) extraction;( ii) a dock station for the transmission of the data through the telephone line. The system will allow to reduce costs in fetal monitoring, improving the assessment of fetal conditions. The device is actually in development state. In this paper, the most crucial aspects behind its fulfillment are discussed.

关键词： FPGA abdominal ECG recordings bioelectric potentials biomedical electrodes biomedical equipment biomedical telemetry data transmission dock station electrocardiography fetal heart rate extraction fetus health state field programmable gate array field programmable gate arrays gynaecology hospital facility medical signal processing patient care patient monitoring pregnancy prototype wearable system remote fetal heart rate monitoring remote sensing telephone line textile electrodes

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A Sub-Threshold FPGA with Low-Swing Dual-V_DD Interconnect in 90nm CMOS

A Sub-Threshold FPGA with Low-Swing Dual-V<sub>DD</sub> Inte...

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32nd Annual Custom Integrated Circuits Conference CICC

作者： Ryan, Joseph F. Calhoun, Benton H. Univ Virginia Charlottesville VA 22904 USA

ISBN: (纸本)9781424457601

This paper presents a sub-threshold field programmable gate array (FPGA) that uses a low-swing dual-V(DD) global interconnect fabric to reduce energy and improve delay. A 90nm chip implements the FPGA with 1134 LUTs, which is 2.7X smaller, 14X faster, and 4.7X less energy than a sub-threshold FPGA using conventional interconnect and 22X less energy than an equivalent FPGA at full V(DD).

关键词： field programmable gate array field programmable gate arrays integrated circuit interconnections low-swing dual-VDD interconnect size 90 nm sub-threshold FPGA

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A Power-Gatable Reconfigurable Logic Chip with FeRAM Cells

A Power-Gatable Reconfigurable Logic Chip with FeRAM Cells

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IEEE Region 10 Conference on TENCON 2010

作者： Koga, Masahiro Iida, Masahiro Amagasaki, Motoki Ichida, Yoshinobu Saji, Mitsuro Iida, Jun Sueyoshi, Toshinori Kumamoto Univ Grad Sch Sci & Technol 2-39-1 Kurokami Kumamoto 8608555 Japan ROHM Co Ltd Ukyo Ku Kyoto 6158585 Japan ROHM Co Ltd Yokohama Kanagawa 2228575 Japan

ISBN: (纸本)9781424468904

An advantage of a RLD (Reconfigurable logic device) such as an FPGA (field programmable gate array) is that it can be customized after being manufactured. However, there is a problem related to standby power when using SRAM as a configuration memory. Power gating, which is one of the power reduction techniques, is difficult to use in SRAM-based RLDs because of the high overhead - data hibernation and reconfiguration time - and SRAM being volatile. In this paper, we describe a chip that we developed - a reconfigurable logic chip based on FeRAM (Ferroelectric random access memory) technology. The chip employs island-style routing architecture and uses a variable grain logic cell as a logic block. A NV-FF (Non-Volatile FlipFlop), which contains FeRAM, a FF, and power-gating control circuits, is used as configuration memory. The NV-FF can transmit data between FeRAM and FF automatically when power to the chip is turned off/on. Thus, chip-level power gating is possible. The hibernate/restore time is less than 1 ms. The chip has 18 x 18 logic blocks and an area of 54.76 mm(2). We also make test circuits for testing the chip after fabrication. Target fault model is Stack-at faults model. When we merge all 28 circuits, fault coverage is 78 %.

关键词： FPGA FeRAM cells RLD SRAM SRAM chips Stack-at fault model chip-level power gating data hibernation fault diagnosis ferroelectric random access memory technology ferroelectric storage field programmable gate array field programmable gate arrays flip-flops

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