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IEEE Annual Symposium on VLSI (ISVLSI)

作者： Liu, Ming Lu, Zhonghai Kuehn, Wolfgang Jantsch, Axel Justus Liebig Univ Giessen JLU Phys Inst 2 Giessen Germany Royal Inst Technol KTH Dept Elect Syst Stockholm Sweden

ISBN: (纸本)9780769540764

In FPGA-based adaptive computing, Inter-Process Communications (IPC) are required to exchange information among hardware processes which time-multiplex the resources in a same reconfigurable region. In this paper, we use pipes for IPC and analyze the performance in terms of throughput, throughput efficiency and latency in switching contexts. We also present two practical implementations using FPGA BRAM and external DDR memory. Experimental results expose the key role that context switching plays in determining the IPC performance at various pipe sizes and data rates.

关键词： Adaptive computing FPGA partial reconfiguration FPGA-based adaptive computing Inter-Process Communication (IPC) Pipes context switching external DDR memory field programmable gate array field programmable gate arrays inter-process communication multiprogramming pipe concept resource time-multiplex

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A FPGA-Based Bit-Word PLC CPUs Development Platform

A FPGA-Based Bit-Word PLC CPUs Development Platform

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10th IFAC Workshop on programmable Devices and Embedded Systems (PDeS)

作者： Chmiel, Miroslaw Mocha, Jan Hrynkiewicz, Edward Silesian Tech Univ Inst Elect Gliwice Poland

ISBN: (纸本)9783902661951

The conception of the hardware-software platform is presented in the paper. Presented platform is designed in order to test different constructions of the central processing units dedicated to programmable logic controllers. Selected hardware solutions for the PLC dual processor bit-byte (word) CPUs, which are oriented for optimised maximum utilization of capabilities of the two-processor architecture of the CPU are presented in the paper. The key point is preserving high speed of instruction processing by the bit-processor, and high speed and functionality of the byte (word)-processor. The structure should enable the processors to work in concurrent mode as far as it is possible, and minimize the situations, when one processor has to wait for the other. Designed platform is based on the development board equipped with Xilinx Virtex-4 FPGA. Software tool for testing possibilities of the selected units and testing utilization of the programmable structure was also developed.

关键词： programmable Logic Controller Central Processing Unit Bit-Byte (Word) Structure of CPU Scan Time Throughput Time Concurrent Operation field programmable gate array

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Two-Dimensional Systolic-array Architecture for Pixel-Level Vision Tasks

Two-Dimensional Systolic-Array Architecture for Pixel-Level ...

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Conference on Real-Time Image and Video Processing 2010

作者： Vijverberg, Julien A. de With, Peter H. N. Eindhoven Univ Technol Eindhoven Netherlands

ISBN: (纸本)9780819481979

This paper presents ongoing work on the design of a two-dimensional (2D) systolic array for image processing. This component is designed to operate on a multi-processor system-on-chip. In contrast with other 2D systolic-array architectures and many other hardware accelerators, we investigate the applicability of executing multiple tasks in a time-interleaved fashion on the Systolic array (SA). This leads to a lower external memory bandwidth and better load balancing of the tasks on the different processing tiles. To enable the interleaving of tasks, we add a shadow-state register for fast task switching. To reduce the number of accesses to the external memory, we propose to share the communication assist between consecutive tasks. A preliminary, non-functional version of the SA has been synthesized for an XV4S25 FPGA device and yields a maximum clock frequency of 150 MHz requiring 1,447 slices and 5 memory blocks. Mapping tasks from video content-analysis applications from literature on the SA yields reductions in the execution time of 1-2 orders of magnitude compared to the software implementation. We conclude that the choice for an SA architecture is useful, but a scaled version of the SA featuring less logic with fewer processing and pipeline stages yielding a lower clock frequency, would be sufficient for a video analysis system-on-chip.

关键词： Real-Time Imaging Two-Dimensional Systolic array Logic Devices Multi-Processor System-on-Chip field programmable gate array

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An Impulse C Application in the LDPC Decoding Algorithm

An Impulse C Application in the LDPC Decoding Algorithm

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6th International Conference on Intelligent Computing

作者： Zhang, Pei Tao, Zhifu Wang, Yiming Zhou, Changxiong JiangSu Prov Support Software Engn R&D Ctr Modern Suzhou 215104 Jiangsu Peoples R China Suzhou Vocat Univ Suzhou 215104 Peoples R China Suzhou Univ Suzhou 215021 Peoples R China

ISBN: (纸本)9783642148309

In order to obtain the balance of the decoding rate and the hardware consumption, a new method to design LDPC decoder is proposed, which is a communicating sequential process model intended for streams-oriented and mixed hardware/software applications. For the characteristics of the decoding algorithm, this method is based on an up-to-date parallel technique from Impulse C programming to FPGA hardware implementation, which is more efficient than the traditional HDL method. A decoder for a family of (3,6) LDPC Codes with a code rate of 0.5 and a block size of 2500 bits is implemented on Xilinx Virtex2 XC2V2000. By performing maximum 10 decoding iterations, the decoder can achieve a maximum bit throughput of 10Mbps.

关键词： Low-Density Parity Check Codes Streams-Oriented Parallel Impulse C programming field programmable gate array

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AUTOMATIC VHDL GENERATION SOFTWARE TOOL FOR PARAMETERIZED FPGA BASED FFT ARCHITECTURES

AUTOMATIC VHDL GENERATION SOFTWARE TOOL FOR PARAMETERIZED FP...

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IEEE National Aerospace and Electronics Conference

作者： Schmuland, Todd E. Longbrake, Matthew B. Buxa, Peter E. Jamali, Mohsin M. Univ Toledo Dept EECS Toledo OH 43606 USA Wright Patterson AFB AFRL RYDR Dayton OH USA

ISBN: (纸本)9781424465781

This paper describes the development of a software tool for simulating and generating fully parallel generic VHDL representations of Fast Fourier Transforms. Several fixed-point number optimizations are described with emphasis on maximizing speed and/or minimizing FPGA area. Twiddle factor bit precision and its effects on FPGA area usage are also explored.

关键词： Hardware design language Software tool field programmable gate array Discrete Fourier transform

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Design methodology and FPGA-based controllers for Power Electronics and drive applications

Design methodology and FPGA-based controllers for Power Elec...

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5th IEEE Conference on Industrial Electronics and Applications

作者： Monmasson, E. Idkhajine, L. Bahri, I. Naouar, M-W- Charaabi, L. UCP SATIE Rue dEragny F-95031 Cergy Pontoise France Ecole Natl Ingn Tunis LSE Tunis Tunisia

ISBN: (纸本)9781424450466

This paper presents a short state-of-the-art field programmable gate array (FPGA) technology. An efficient design methodology for designing FPGA-based controllers is also described. To illustrate the interest of this methodology, a complex sensorless algorithm for AC drives has been chosen. It consists in an Extended Kalman Filter (EKF), which is most of the time implemented in a DSP controller. In the last part of the paper, authors try to demonstrate all the benefits of using FPGAs for power electronic and drive applications. Two cases are discussed, the high demanding applications and the constrained switching frequency applications.

关键词： Design Methodology field programmable gate array Extended Kalman Filter System-on-programmable Chip FPGA-based controller Digital control of power electronics

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Creating Next Generation HIL Simulators with FPGA Technology

Creating Next Generation HIL Simulators with FPGA Technology

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AUTOTESTCON 2010 Systems Readiness Technology Conference

作者： Washington, Chris Dolman, Jordan Natl Instruments Inc Real Time Testing Austin TX 78759 USA Natl Instruments Inc Modular Instruments Austin TX 78759 USA

ISBN: (纸本)9781424479597

As embedded control devices become more common in today's electro-mechanical systems, HIL Simulation is growing in its importance to the success of these systems. HIL testing provides a simulated environment for the unit under test, simulating the parts of the system that are not physically present. As these systems grow in complexity, traditional HIL simulation techniques are falling short. Fortunately, technologies such as field programmable gate arrays (FPGAs) are being applied to produce the next generation of HIL simulators. FPGAs enable test system developers to create custom hardware that can be easily reconfigured without physically modifying the device. In addition to being reconfigurable, for certain applications, FPGAs can offer superior performance compared to microprocessors. More specifically for HIL test systems, FPGA-based I/O devices provide superior determinism, on the order of nanoseconds, enabling realistic simulation of plant components not typically realizable with microprocessor-only based systems. They are also used to off-load some of the processing that would otherwise be required of the test system microprocessor increasing the total system bandwidth. Because of the ease with which their personalities can be reconfigured, FPGAs are also used in HIL test systems to create custom IO interfaces as well as IO interfaces that can adapt to multiple UUT types or changes to UUT interfaces that evolve during product development. In this paper, we will discuss examples of how FPGAs are being used for sensor simulation to create better, more adaptable HIL test systems.

关键词： FPGA technology HIL simulator HIL test systems automatic testing digital simulation field programmable gate array field programmable gate arrays hardware-in-the-loop simulator input-output interfaces microprocessors sensor simulation

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Embedding an array Self-Recovery Algorithm into an FPGA Controller

Embedding an Array Self-Recovery Algorithm into an FPGA Cont...

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2010 IEEE International Symposium Antennas and Propagation/CNC-USNC/URSI Radio Science Meeting

作者： Malnar, Damir Joler, Miroslav Christodoulou, Christos G. Univ Rijeka Fac Engn Dept Comp Engn Rijeka 51000 Croatia Univ New Mexico Dpet Elect & Comp Engn Albuquerque NM 87131 USA

ISBN: (纸本)9781424449682

In this paper, we report on our work of embedding a self-recovery algorithm into a field programmable gate array (FPGA) board, as a means of radiation pattern recovery after failure of any antenna array element. In the previous work, the principle approach was laid out and sample failure cases discussed, followed by an example of a successful recovery of the pattern using a genetic algorithm (G A)-based solution. The next objective then was to load that self-recovery code onto an FPGA board to take advantage of the FPGA's speed, reconfigurability, and potential for autonomous operation. However, that is not a straightforward task to do, as it will be discussed below, regardless of the particular approach taken to link and match the software (SW)and the hardware (HW)part of this job.

关键词： FPGA controller antenna array element antenna arrays antenna radiation patterns array self-recovery algorithm field programmable gate array field programmable gate arrays genetic algorithm genetic algorithms radiation pattern recovery

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Implementation of Lossy Haptic Data Compression Using Integer DCT to FPGA

Implementation of Lossy Haptic Data Compression Using Intege...

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36th Annual Conference of the IEEE Industrial-Electronics-Society (IECON)/4th IEEE International Conference on E-Learning in Industrial Electronics/IES Industry Forum

作者： Tanaka, Hiroyuki Ohnishi, Kouhei Nishi, Hiroaki Keio Univ Dept Syst Design Engn Tokyo Japan

ISBN: (纸本)9781424452262

In this paper, lossy compression based on Integer DCT (Discrete Cosine Transform) for haptic data is presented and implemented to an FPGA (field programmable gate array). The lossy data compression accomplishes to reduce data size of the haptic data. In the lossy data compression, DCT-based techniques are often used. The Integer DCT (IntDCT) achieves the operation of the DCT with the format of integer. The compatibility of the IntDCT with the FPGA is therefore high. The lossy compression method is applied to a bilateral control system and the efficacy is confirmed by experiments.

关键词： FPGA bilateral control system data compression discrete cosine transforms field programmable gate array field programmable gate arrays integer DCT integer discrete cosine transform lossy compression lossy haptic data compression master robot slave robot teleoperation telerobotics

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High-Speed Parallel Matched Filter Designing and FPGA Implementation

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Wuhan University Journal of Natural Sciences 2010年第4期15卷 335-339页

作者： ZHANG Qinglin, CHEN Shuzhen, LUO Yijun, WANG Shan School of Electronic Information, Wuhan University, Wuhan 430072, Hubei, China School of Electronic Information Wuhan University Wuhan Hubei China

Matched filter is one of the key technologies to achieve high-speed data transmission. In this paper,a parallel finite-impulse response (FIR) filter structure based on polyphase filter-ing is used to achieve high-speed matched filter in quadrature phase-shift keying (QPSK) demodulation up to 800 Mb·s-1. First,a window function is employed of to obtain impulse response of matched filter. Second,the high-speed parallel FIR structure is presented based on polyphase filtering. Then,the filter with EP2S180F1020 on the Quartus II 7.2 platform is achieved. The final results show that the design is correct and can implement high-speed matched filtering,wherein the equivalent frequency of which is up to 2 037 MHz. In addition,this scheme is easy to real-ize,which brings great value to the application of this filter in high-speed matched filters design in demodulation systems.

关键词： parallel matched filter finite-impulse response (FIR) window function polyphase filtering field programmable gate array

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