The conception of the hardware-software platform is presented in the paper. Presented platform is designed in order to test different constructions of the central processing units dedicated to programmable logic contr...
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ISBN:
(纸本)9783902661951
The conception of the hardware-software platform is presented in the paper. Presented platform is designed in order to test different constructions of the central processing units dedicated to programmable logic controllers. Selected hardware solutions for the PLC dual processor bit-byte (word) CPUs, which are oriented for optimised maximum utilization of capabilities of the two-processor architecture of the CPU are presented in the paper. The key point is preserving high speed of instruction processing by the bit-processor, and high speed and functionality of the byte (word)-processor. The structure should enable the processors to work in concurrent mode as far as it is possible, and minimize the situations, when one processor has to wait for the other. Designed platform is based on the development board equipped with Xilinx Virtex-4 FPGA. Software tool for testing possibilities of the selected units and testing utilization of the programmable structure was also developed.
This paper presents ongoing work on the design of a two-dimensional (2D) systolic array for image processing. This component is designed to operate on a multi-processor system-on-chip. In contrast with other 2D systol...
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ISBN:
(纸本)9780819481979
This paper presents ongoing work on the design of a two-dimensional (2D) systolic array for image processing. This component is designed to operate on a multi-processor system-on-chip. In contrast with other 2D systolic-array architectures and many other hardware accelerators, we investigate the applicability of executing multiple tasks in a time-interleaved fashion on the Systolic array (SA). This leads to a lower external memory bandwidth and better load balancing of the tasks on the different processing tiles. To enable the interleaving of tasks, we add a shadow-state register for fast task switching. To reduce the number of accesses to the external memory, we propose to share the communication assist between consecutive tasks. A preliminary, non-functional version of the SA has been synthesized for an XV4S25 FPGA device and yields a maximum clock frequency of 150 MHz requiring 1,447 slices and 5 memory blocks. Mapping tasks from video content-analysis applications from literature on the SA yields reductions in the execution time of 1-2 orders of magnitude compared to the software implementation. We conclude that the choice for an SA architecture is useful, but a scaled version of the SA featuring less logic with fewer processing and pipeline stages yielding a lower clock frequency, would be sufficient for a video analysis system-on-chip.
In order to obtain the balance of the decoding rate and the hardware consumption, a new method to design LDPC decoder is proposed, which is a communicating sequential process model intended for streams-oriented and mi...
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ISBN:
(纸本)9783642148309
In order to obtain the balance of the decoding rate and the hardware consumption, a new method to design LDPC decoder is proposed, which is a communicating sequential process model intended for streams-oriented and mixed hardware/software applications. For the characteristics of the decoding algorithm, this method is based on an up-to-date parallel technique from Impulse C programming to FPGA hardware implementation, which is more efficient than the traditional HDL method. A decoder for a family of (3,6) LDPC Codes with a code rate of 0.5 and a block size of 2500 bits is implemented on Xilinx Virtex2 XC2V2000. By performing maximum 10 decoding iterations, the decoder can achieve a maximum bit throughput of 10Mbps.
This paper describes the development of a software tool for simulating and generating fully parallel generic VHDL representations of Fast Fourier Transforms. Several fixed-point number optimizations are described with...
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ISBN:
(纸本)9781424465781
This paper describes the development of a software tool for simulating and generating fully parallel generic VHDL representations of Fast Fourier Transforms. Several fixed-point number optimizations are described with emphasis on maximizing speed and/or minimizing FPGA area. Twiddle factor bit precision and its effects on FPGA area usage are also explored.
This paper presents a short state-of-the-art field programmable gate array (FPGA) technology. An efficient design methodology for designing FPGA-based controllers is also described. To illustrate the interest of this ...
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ISBN:
(纸本)9781424450466
This paper presents a short state-of-the-art field programmable gate array (FPGA) technology. An efficient design methodology for designing FPGA-based controllers is also described. To illustrate the interest of this methodology, a complex sensorless algorithm for AC drives has been chosen. It consists in an Extended Kalman Filter (EKF), which is most of the time implemented in a DSP controller. In the last part of the paper, authors try to demonstrate all the benefits of using FPGAs for power electronic and drive applications. Two cases are discussed, the high demanding applications and the constrained switching frequency applications.
As embedded control devices become more common in today's electro-mechanical systems, HIL Simulation is growing in its importance to the success of these systems. HIL testing provides a simulated environment for t...
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ISBN:
(纸本)9781424479597
As embedded control devices become more common in today's electro-mechanical systems, HIL Simulation is growing in its importance to the success of these systems. HIL testing provides a simulated environment for the unit under test, simulating the parts of the system that are not physically present. As these systems grow in complexity, traditional HIL simulation techniques are falling short. Fortunately, technologies such as field programmable gate arrays (FPGAs) are being applied to produce the next generation of HIL simulators. FPGAs enable test system developers to create custom hardware that can be easily reconfigured without physically modifying the device. In addition to being reconfigurable, for certain applications, FPGAs can offer superior performance compared to microprocessors. More specifically for HIL test systems, FPGA-based I/O devices provide superior determinism, on the order of nanoseconds, enabling realistic simulation of plant components not typically realizable with microprocessor-only based systems. They are also used to off-load some of the processing that would otherwise be required of the test system microprocessor increasing the total system bandwidth. Because of the ease with which their personalities can be reconfigured, FPGAs are also used in HIL test systems to create custom IO interfaces as well as IO interfaces that can adapt to multiple UUT types or changes to UUT interfaces that evolve during product development. In this paper, we will discuss examples of how FPGAs are being used for sensor simulation to create better, more adaptable HIL test systems.
In this paper, we report on our work of embedding a self-recovery algorithm into a field programmable gate array (FPGA) board, as a means of radiation pattern recovery after failure of any antenna array element. In th...
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ISBN:
(纸本)9781424449682
In this paper, we report on our work of embedding a self-recovery algorithm into a field programmable gate array (FPGA) board, as a means of radiation pattern recovery after failure of any antenna array element. In the previous work, the principle approach was laid out and sample failure cases discussed, followed by an example of a successful recovery of the pattern using a genetic algorithm (G A)-based solution. The next objective then was to load that self-recovery code onto an FPGA board to take advantage of the FPGA's speed, reconfigurability, and potential for autonomous operation. However, that is not a straightforward task to do, as it will be discussed below, regardless of the particular approach taken to link and match the software (SW)and the hardware (HW)part of this job.
In this paper, lossy compression based on Integer DCT (Discrete Cosine Transform) for haptic data is presented and implemented to an FPGA (field programmable gate array). The lossy data compression accomplishes to red...
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ISBN:
(纸本)9781424452262
In this paper, lossy compression based on Integer DCT (Discrete Cosine Transform) for haptic data is presented and implemented to an FPGA (field programmable gate array). The lossy data compression accomplishes to reduce data size of the haptic data. In the lossy data compression, DCT-based techniques are often used. The Integer DCT (IntDCT) achieves the operation of the DCT with the format of integer. The compatibility of the IntDCT with the FPGA is therefore high. The lossy compression method is applied to a bilateral control system and the efficacy is confirmed by experiments.
Matched filter is one of the key technologies to achieve high-speed data transmission. In this paper,a parallel finite-impulse response (FIR) filter structure based on polyphase filter-ing is used to achieve high-spee...
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Matched filter is one of the key technologies to achieve high-speed data transmission. In this paper,a parallel finite-impulse response (FIR) filter structure based on polyphase filter-ing is used to achieve high-speed matched filter in quadrature phase-shift keying (QPSK) demodulation up to 800 Mb·s-1. First,a window function is employed of to obtain impulse response of matched filter. Second,the high-speed parallel FIR structure is presented based on polyphase filtering. Then,the filter with EP2S180F1020 on the Quartus II 7.2 platform is achieved. The final results show that the design is correct and can implement high-speed matched filtering,wherein the equivalent frequency of which is up to 2 037 MHz. In addition,this scheme is easy to real-ize,which brings great value to the application of this filter in high-speed matched filters design in demodulation systems.
Wireless sensor networks are used in many fields. The needs to develop application based on wireless sensor networks are imperious. The node in wireless sensor networks nowaday is not only cheap but also reusable. To ...
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ISBN:
(纸本)9781424468904
Wireless sensor networks are used in many fields. The needs to develop application based on wireless sensor networks are imperious. The node in wireless sensor networks nowaday is not only cheap but also reusable. To fulfill these requirements many technologies were researched and developed, one of which is field programmable gate array (FPGA). We can utilize the reconfigurable characteristic of FPGA to implement nodes of a wireless sensor network with little effort. This paper proposes the method to port TinyOS, an operating system particularly designed for wireless embedded sensor network, on FPGA system. This fills the gaps between FPGA and wireless sensor networks.
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