This paper describes the development and implementation of a permanent magnet synchronous machine controller for safety critical applications which embeds independent real-time mechanical-fault diagnostics into the dr...
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ISBN:
(纸本)9781424452873
This paper describes the development and implementation of a permanent magnet synchronous machine controller for safety critical applications which embeds independent real-time mechanical-fault diagnostics into the drive controller. The drive is intended for aerospace applications and therefore must employ an ASIC or FPGA as the main control "processor" to provide a more suitable route to flight-product certification. Motor Current Signature Analysis (MCSA) is employed to indicate the development or existence of faults within the drive system and this is achieved by embedding a real-time frequency analysis of the motor current within the FPGA, operating independently of the motor control. Experimental results are provided to validate the proposed control and condition monitoring.
Face detection is an important aspect for biometrics, video surveillance and human computer interaction. We present a multi-GPU implementation of the Viola-Jones face detection algorithm that meets the performance of ...
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ISBN:
(纸本)9780769540566
Face detection is an important aspect for biometrics, video surveillance and human computer interaction. We present a multi-GPU implementation of the Viola-Jones face detection algorithm that meets the performance of the fastest known FPGA implementation. The GPU design offers far lower development costs, but the FPGA implementation consumes less power. We discuss the performance programming required to realize our design, and describe future research directions.
This work presents a tool for automatic generation of controllers' implementation code from Petri nets models amenable to be deployed into common platforms using widely used high level programming languages, such ...
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ISBN:
(纸本)9781424463916
This work presents a tool for automatic generation of controllers' implementation code from Petri nets models amenable to be deployed into common platforms using widely used high level programming languages, such as C, C++, and Java. The generated code is linked with platform specific functions, supporting different types of implementation platforms, ranging from low-cost microcontrollers to workstations, and including microcontroller IPs (Intellectual Property) to be embedded into FPGAs (field programmable gate arrays). The system controller behavior is modeled using IOPT (Input-Output Place-Transition) Petri Nets models, which are represented through PNML (Petri nets Mark-up Language) notation. A tool for automatic code generation was developed, which achieved this goal in cooperation with other developed tools within a model-based development framework. Application to an automation system composed by a set of distributed controllers is presented.
The paper describes a field programmable gate array implementation of the main part of speech recognition system - feature extraction. In order to accelerate recognition the whole cepstral analysis scheme is implement...
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ISBN:
(纸本)9780819482358
The paper describes a field programmable gate array implementation of the main part of speech recognition system - feature extraction. In order to accelerate recognition the whole cepstral analysis scheme is implemented in hardware by the use of intellectual property cores. Two field programmable gate array devices are used for evaluation. Comparative experimental results of four different implementations are presented. They grounds achieved 29 times faster speech analysis in comparison with software based analysis subsystem.
The background identification methods are used in many fields like video surveillance and traffic monitoring. In this paper we propose a hardware implementation of the Gaussian Mixture Model algorithm able to perform ...
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ISBN:
(纸本)9781612841519
The background identification methods are used in many fields like video surveillance and traffic monitoring. In this paper we propose a hardware implementation of the Gaussian Mixture Model algorithm able to perform background identification on HD images. The proposed circuit is based on the OpenCV implementation, particularly suited to improve the initial background learning phase. Bit-width has been optimized in order to reduce hardware complexity and increase working speed. The proposed circuit processes 22 1920X1080 frames per second when implemented on Virtex 5 FPGA.
This paper presents the design and implementation of robust real-time visual servoing control with an FPGA-based image co-processor for a rotary inverted pendulum. The position of the pendulum is measured with a machi...
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ISBN:
(纸本)9781424453634
This paper presents the design and implementation of robust real-time visual servoing control with an FPGA-based image co-processor for a rotary inverted pendulum. The position of the pendulum is measured with a machine vision system whose image processing algorithms are pipelined and implemented on a field programmable gate array (FPGA) device to meet real-time constraints. To enforce robustness to model uncertainty, and to attenuate disturbance and sensor noise, the design of the stabilizing controller is formulated as a problem of the mixed H(2)/H(infinity) control, which is then solved using the linear matrix inequality (LMI) approach. The designed control law is implemented on a digital signal processor (DSP). The effectiveness of the controller and the FPGA-based image co-processor is verified through experimental studies. The experimental results show that the designed system is able to robustly control an inverted pendulum in real-time.
In this article, we reported for the first time, a low complexity field programmable gate array solution for integrating video surveillance into RFID units. The method is comprised of two major building blocks, namely...
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In this article, we reported for the first time, a low complexity field programmable gate array solution for integrating video surveillance into RFID units. The method is comprised of two major building blocks, namely a RFID transmitter operating at a maximum bandwidth of 250 kbps, and a near computation free image compression engine based on an enhanced Decomposed Adaptive Decimation scheme. (C) 2010 Wiley Periodicals, Inc. MIcrowave Opt Technol Lett 52 775-779, 2010.
This paper presents an FPGA-based ultrasonic location system. This system uses low-cost FPGAs and ultrasonic transducers to provide 3-D location to mobile nodes in an indoor environment. Synchronization is reached usi...
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ISBN:
(纸本)9781424463916
This paper presents an FPGA-based ultrasonic location system. This system uses low-cost FPGAs and ultrasonic transducers to provide 3-D location to mobile nodes in an indoor environment. Synchronization is reached using the radiofrequency transducers that mobile nodes usually include. FPGAs have been used to sample ultrasonics and radiofrequency inside a custom peripheral which is attached to a MicroBlaze soft-processor. The calculus of the position of the mobile node is accomplished inside this processor.
Steering maneuver is essential in robotic motion planning. Despite a lot of steering mechanisms successfully developed in past years, for miniature robots, real-time computation is still a limitation for robot path tr...
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ISBN:
(纸本)9781424466757
Steering maneuver is essential in robotic motion planning. Despite a lot of steering mechanisms successfully developed in past years, for miniature robots, real-time computation is still a limitation for robot path tracking. The design issues in cooperative control of battery-powered nonholonomic robots rest with the complicacy of the control strategies, the low power consumption and real-time processing capability. Conventionally, the improvement of computing speed mostly relies on the increment of the system clock and often results in some transient loss. Thus, an elaborate control algorithm developed for PC might not work on an embedded system. This paper presents a comprehensive steering algorithm which, via issuing predicaments for computation, will dramatically reduce the resource usage in hardware circuit design. The proposed algorithm is implemented on an embedded system for ubiquitous robotics using the field programmable gate array (FPGA) technology.
This paper describes about designing of the architecture of the fastICA for FPGA, and it can check that it is possible to perform ICA processing in real-time for transmission of the QPSK signals of more than 1 Mbps.
ISBN:
(纸本)9781424449682
This paper describes about designing of the architecture of the fastICA for FPGA, and it can check that it is possible to perform ICA processing in real-time for transmission of the QPSK signals of more than 1 Mbps.
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