A microdisplay system based on an optical fiber driven by a 2-D piezoelectric actuator is presented. An optical fiber is extended from the free end of a 2-D piezoelectric actuator (free length 4.3 mm). A field program...
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A microdisplay system based on an optical fiber driven by a 2-D piezoelectric actuator is presented. An optical fiber is extended from the free end of a 2-D piezoelectric actuator (free length 4.3 mm). A field programmable gate array (FPGA) drives the actuator using a triangular waveform to deflect the optical fiber in orthogonal directions. The FPGA also controls a LED light source, and the light is coupled into a chemically tapered single-mode fiber (SMF-28, core diameter 10 mu m). At a preset pairing of near-resonance frequencies (horizontal 22 Hz, vertical 5070 Hz), the deflected optical fiber in combination with controlled light produces an output image with an approximate dimension of 0.1 x 0.1 mm(2), and a potential resolution of 400 lines per scan. This work details the design and fabrication of the microdisplay system. The mechanical and optical design for the microresonating scanner is discussed. In addition, the mechanical and optical performance and the resulting output of the 2-D scanner is presented. (C) 2010 Society of Photo-Optical Instrumentation Engineers. [DOI: 10.1117/1.3487745]
This paper proposes a multi-core architecture for implementation of a unified chassis control (UCC) algorithm on a field programmable gate array (FPGA) which operates as a multi-core process. The proposed multi-core a...
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This paper proposes a multi-core architecture for implementation of a unified chassis control (UCC) algorithm on a field programmable gate array (FPGA) which operates as a multi-core process. The proposed multi-core architecture aims to reduce the operating load and maximize the reliability for improving the performance of the UCC system. The proposed multi-core architecture supports distributed control with analytical and physical redundancy capabilities. The UCC algorithm used in this research consists of three parts: a supervisor, a main controller, and fault detection/isolation/tolerance control (FDI/FTC). These three components are implemented and evaluated with the multi-core process environment with the FPGA. An electronic control unit is configured by three Micro Blaze processors with FPGA, and a control area network (CAN) is also implemented for hardware-in-the-loop (HILS) evaluation. Three types of multi-core architectures, i.e. distributed processing, triple voting, and hybrid operation, are implemented to investigate the performance and reliability. A vehicle simulator and brake HILS are used to evaluate the proposed multi-core architectures. From the test results, it is shown that all of the proposed multi-core systems have better performance and improved reliability compared with the single core system. In particular, the hybrid operation architecture shows better reliability and performance compared with the other two multi-core architectures, distributed processing and triple voting.
Background: Likelihood (ML)-based phylogenetic inference has become a popular method for estimating the evolutionary relationships among species based on genomic sequence data. This method is used in applications such...
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Background: Likelihood (ML)-based phylogenetic inference has become a popular method for estimating the evolutionary relationships among species based on genomic sequence data. This method is used in applications such as RAxML, GARLI, MrBayes, PAML, and PAUP. The Phylogenetic Likelihood Function (PLF) is an important kernel computation for this method. The PLF consists of a loop with no conditional behavior or dependencies between iterations. As such it contains a high potential for exploiting parallelism using micro-architectural techniques. In this paper, we describe a technique for mapping the PLF and supporting logic onto a field programmable gate array (FPGA)-based co-processor. By leveraging the FPGA's on-chip DSP modules and the high-bandwidth local memory attached to the FPGA, the resultant co-processor can accelerate ML-based methods and outperform state-of-the-art multi-core processors. Results: We use the MrBayes 3 tool as a framework for designing our co-processor. For large datasets, we estimate that our accelerated MrBayes, if run on a current-generation FPGA, achieves a 10x speedup relative to software running on a state-of-the-art server-class microprocessor. The FPGA-based implementation achieves its performance by deeply pipelining the likelihood computations, performing multiple floating-point operations in parallel, and through a natural log approximation that is chosen specifically to leverage a deeply pipelined custom architecture. Conclusions: Heterogeneous computing, which combines general-purpose processors with special-purpose co-processors such as FPGAs and GPUs, is a promising approach for high-performance phylogeny inference as shown by the growing body of literature in this field. FPGAs in particular are well-suited for this task because of their low power consumption as compared to many-core processors and Graphics Processor Units (GPUs) [1].
This work presents a design framework for real-time image and video processing enabling exploration and evaluation of different processing techniques. The goal of our educational approach is to develop a flexible and ...
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This work presents a design framework for real-time image and video processing enabling exploration and evaluation of different processing techniques. The goal of our educational approach is to develop a flexible and easily customizable environment for prototyping different processing techniques on field programmable gate arrays (FPGAs), targeting specific applications. In this paper we give an overview of different requirements and techniques of video processing featuring FPGAs. Three real-time video processing algorithms were combined to show the advantages and characteristics of our approach. Within the framework, the modules running in parallel can be easily swapped at run-time according to the application specific needs.
The conception of the hardware-software platform is presented in the paper. Presented platform is designed in order to test different constructions of the central processing units dedicated to programmable logic contr...
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The conception of the hardware-software platform is presented in the paper. Presented platform is designed in order to test different constructions of the central processing units dedicated to programmable logic controllers. Selected hardware solutions for the PLC dual processor bit-byte (word) CPUs, which are oriented for optimised maximum utilization of capabilities of the two-processor architecture of the CPU are presented in the paper. The key point is preserving high speed of instruction processing by the bit-processor, and high speed and functionality of the byte (word)-processor. The structure should enable the processors to work in concurrent mode as far as it is possible, and minimize the situations, when one processor has to wait for the other. Designed platform is based on the development board equipped with Xilinx Virtex-4 FPGA. Software tool for testing possibilities of the selected units and testing utilization of the programmable structure was also developed.
This paper presents the implementation of a high resolution time-to-digital converter (TDC) on a dynamically reconfigurable FPGA. The TDC architecture is based on the Vernier method using two ring oscillators with sli...
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ISBN:
(纸本)9781605589114
This paper presents the implementation of a high resolution time-to-digital converter (TDC) on a dynamically reconfigurable FPGA. The TDC architecture is based on the Vernier method using two ring oscillators with slightly different frequencies. The proposed oscillators can be calibrated with picoseconds resolution by taking advantage of partial reconfiguration, and moreover recalibrated over time. The results obtained on a Xilinx Virtex-II Pro FPGA show that the proposed TDC implementation can achieve unprecedented resolutions (on FPGA) as low as 5ps and precisions up to 25ps.
In this article, we reported for the first time, a low complexity field programmable gate array solution for integrating video surveillance into RFID units. The method is comprised of two major building blocks, namely...
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In this article, we reported for the first time, a low complexity field programmable gate array solution for integrating video surveillance into RFID units. The method is comprised of two major building blocks, namely a RFID transmitter operating at a maximum bandwidth of 250 kbps, and a near computation free image compression engine based on an enhanced Decomposed Adaptive Decimation scheme. (C) 2010 Wiley Periodicals, Inc. MIcrowave Opt Technol Lett 52 775-779, 2010.
Synthetic aperture (SA) imaging techniques have drawn many attentions since they are capable of providing improved spatial resolution over conventional receive dynamic focusing (CRDF) methods. However, the processing ...
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ISBN:
(纸本)9781457703829
Synthetic aperture (SA) imaging techniques have drawn many attentions since they are capable of providing improved spatial resolution over conventional receive dynamic focusing (CRDF) methods. However, the processing of SA imaging is computationally demanding for real-time processing. Furthermore, massive memories for storing the pre-beamformed radio frequency (RF) data are required, leading to substantial increase in hardware complexity. In this paper, we propose the efficient real-time SA beamformer architecture that could be integrated in modern ultrasound imaging systems. The feasibility of the proposed architecture was demonstrated by implementing a 64-channel SA beamformer on two high-performance field programmable gate arrays (FPGAs, Virtex-5 SX95T, Xilinx, USA). The developed SA beamformer can support up to 12 synthesis beams by utilizing 61percent of slice registers, 43percent of lookup tables (LUTs), 89percent of random access memories (RAMs) and 51percent of digital signal processing (DSP) blocks in each FPGA.
Explain the factors which affect the performance of optical current transformer (OCT) and Solutions. Signal processing measure is the key to the application of optical current transformer. Therefore the signal process...
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Explain the factors which affect the performance of optical current transformer (OCT) and Solutions. Signal processing measure is the key to the application of optical current transformer. Therefore the signal processing system’s improved method of optical current transformer was introduced, and prospects the future development of optical current transformers.
This study reports a heuristic genetic algorithm to determine the decoding parameters in a first-order ambisonic system for reconstructing a three-dimensional sound field with an arbitrary quad speaker configuration. ...
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This study reports a heuristic genetic algorithm to determine the decoding parameters in a first-order ambisonic system for reconstructing a three-dimensional sound field with an arbitrary quad speaker configuration. On this basis, a hardware prototype has been developed using a field programmable gate array (FPGA) to decode ambisonic signals that are encoded in the standard B-format. To allow direct coupling with digital audio sources, the input and output channels of the decoder are implemented with the 12S interface. Evaluations reveal that the decoding parameters derived by this method are superior to existing approaches in terms of flexibility in loudspeaker configuration and optimisation of some of the essential factors in surround sound reconstruction.
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