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IEEE Region 10 Conference on TENCON 2010

作者： Dai-Hai Ton-That Anh-Vu Dinh-Duc Khoi Phan-Dinh Univ Technol Fac Comp Sci & Engn Ho Chi Minh City Vietnam

ISBN: (纸本)9781424468904

Wireless sensor networks are used in many fields. The needs to develop application based on wireless sensor networks are imperious. The node in wireless sensor networks nowaday is not only cheap but also reusable. To fulfill these requirements many technologies were researched and developed, one of which is field programmable gate array (FPGA). We can utilize the reconfigurable characteristic of FPGA to implement nodes of a wireless sensor network with little effort. This paper proposes the method to port TinyOS, an operating system particularly designed for wireless embedded sensor network, on FPGA system. This fills the gaps between FPGA and wireless sensor networks.

关键词： TinyOS field programmable gate array Wireless sensor networks FPGA WSNs

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Two-dimensional mechanically resonating fiber optic scanning display system

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OPTICAL ENGINEERING 2010年第9期49卷 097401-097401页

作者： Wang, Wei-Chih Tsui, Chi-Leung Univ Washington Dept Mech Engn Seattle WA 98195 USA Univ Washington Dept Elect Engn Seattle WA 98195 USA

A microdisplay system based on an optical fiber driven by a 2-D piezoelectric actuator is presented. An optical fiber is extended from the free end of a 2-D piezoelectric actuator (free length 4.3 mm). A field programmable gate array (FPGA) drives the actuator using a triangular waveform to deflect the optical fiber in orthogonal directions. The FPGA also controls a LED light source, and the light is coupled into a chemically tapered single-mode fiber (SMF-28, core diameter 10 mu m). At a preset pairing of near-resonance frequencies (horizontal 22 Hz, vertical 5070 Hz), the deflected optical fiber in combination with controlled light produces an output image with an approximate dimension of 0.1 x 0.1 mm(2), and a potential resolution of 400 lines per scan. This work details the design and fabrication of the microdisplay system. The mechanical and optical design for the microresonating scanner is discussed. In addition, the mechanical and optical performance and the resulting output of the 2-D scanner is presented. (C) 2010 Society of Photo-Optical Instrumentation Engineers. [DOI: 10.1117/1.3487745]

关键词： optical display system optical scanner field programmable gate array

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Coordinated implementation and processing of a unified chassis control algorithm with multi-central processing unit

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PROCEEDINGS OF THE INSTITUTION OF MECHANICAL ENGINEERS PART D-JOURNAL OF AUTOMOBILE ENGINEERING 2010年第D5期224卷 565-586页

作者： Seo, K. Yoon, J. Kim, J. Chung, T. Yi, K. Chang, N. Seoul Natl Univ Dept Mech & Aerosp Engn Sch Mech & Aerosp Engn Seoul 151792 South Korea Seoul Natl Univ Sch Comp Sci Engn Seoul 151792 South Korea Hyundai Mobis Gyunggi Do South Korea

This paper proposes a multi-core architecture for implementation of a unified chassis control (UCC) algorithm on a field programmable gate array (FPGA) which operates as a multi-core process. The proposed multi-core architecture aims to reduce the operating load and maximize the reliability for improving the performance of the UCC system. The proposed multi-core architecture supports distributed control with analytical and physical redundancy capabilities. The UCC algorithm used in this research consists of three parts: a supervisor, a main controller, and fault detection/isolation/tolerance control (FDI/FTC). These three components are implemented and evaluated with the multi-core process environment with the FPGA. An electronic control unit is configured by three Micro Blaze processors with FPGA, and a control area network (CAN) is also implemented for hardware-in-the-loop (HILS) evaluation. Three types of multi-core architectures, i.e. distributed processing, triple voting, and hybrid operation, are implemented to investigate the performance and reliability. A vehicle simulator and brake HILS are used to evaluate the proposed multi-core architectures. From the test results, it is shown that all of the proposed multi-core systems have better performance and improved reliability compared with the single core system. In particular, the hybrid operation architecture shows better reliability and performance compared with the other two multi-core architectures, distributed processing and triple voting.

关键词： electronic control unit fault tolerance control field programmable gate array hardware-in-the-loop simulator multi-core processor unified chassis control

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FPGA Acceleration of the phylogenetic likelihood function for Bayesian MCMC inference methods

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BMC BIOINFORMATICS 2010年第1期11卷 184-184页

作者： Zierke, Stephanie Bakos, Jason D. Univ S Carolina Dept Comp Sci & Engn Columbia SC 29208 USA

Background: Likelihood (ML)-based phylogenetic inference has become a popular method for estimating the evolutionary relationships among species based on genomic sequence data. This method is used in applications such as RAxML, GARLI, MrBayes, PAML, and PAUP. The Phylogenetic Likelihood Function (PLF) is an important kernel computation for this method. The PLF consists of a loop with no conditional behavior or dependencies between iterations. As such it contains a high potential for exploiting parallelism using micro-architectural techniques. In this paper, we describe a technique for mapping the PLF and supporting logic onto a field programmable gate array (FPGA)-based co-processor. By leveraging the FPGA's on-chip DSP modules and the high-bandwidth local memory attached to the FPGA, the resultant co-processor can accelerate ML-based methods and outperform state-of-the-art multi-core processors. Results: We use the MrBayes 3 tool as a framework for designing our co-processor. For large datasets, we estimate that our accelerated MrBayes, if run on a current-generation FPGA, achieves a 10x speedup relative to software running on a state-of-the-art server-class microprocessor. The FPGA-based implementation achieves its performance by deeply pipelining the likelihood computations, performing multiple floating-point operations in parallel, and through a natural log approximation that is chosen specifically to leverage a deeply pipelined custom architecture. Conclusions: Heterogeneous computing, which combines general-purpose processors with special-purpose co-processors such as FPGAs and GPUs, is a promising approach for high-performance phylogeny inference as shown by the growing body of literature in this field. FPGAs in particular are well-suited for this task because of their low power consumption as compared to many-core processors and Graphics Processor Units (GPUs) [1].

关键词： Conditional Probability field programmable gate array Single Precision Graphic Processor Unit Memory Port

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Image and video processing on FPGAs: An Exploration Framework for Real-Time Applications

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IFAC Proceedings Volumes 2010年第24期43卷 54-59页

作者： Zied El Hadhri Carlos Valderrama Paulo da Cunha Possa University of Mons Department of Electronics and Microelectronics Mons 7000 Belgium (Tel: +32-6537-4222)

This work presents a design framework for real-time image and video processing enabling exploration and evaluation of different processing techniques. The goal of our educational approach is to develop a flexible and easily customizable environment for prototyping different processing techniques on field programmable gate arrays (FPGAs), targeting specific applications. In this paper we give an overview of different requirements and techniques of video processing featuring FPGAs. Three real-time video processing algorithms were combined to show the advantages and characteristics of our approach. Within the framework, the modules running in parallel can be easily swapped at run-time according to the application specific needs.

关键词： Video processing field programmable gate array embedded systems hardware description language object tracking pattern detection

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A FPGA-Based Bit-Word PLC CPUs Development Platform

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IFAC Proceedings Volumes 2010年第24期43卷 132-137页

作者： Miroslaw Chmiel Jan Mocha Edward Hrynkiewicz University of Technology Institute of Electronics Gliwice Poland

The conception of the hardware-software platform is presented in the paper. Presented platform is designed in order to test different constructions of the central processing units dedicated to programmable logic controllers. Selected hardware solutions for the PLC dual processor bit-byte (word) CPUs, which are oriented for optimised maximum utilization of capabilities of the two-processor architecture of the CPU are presented in the paper. The key point is preserving high speed of instruction processing by the bit-processor, and high speed and functionality of the byte (word)-processor. The structure should enable the processors to work in concurrent mode as far as it is possible, and minimize the situations, when one processor has to wait for the other. Designed platform is based on the development board equipped with Xilinx Virtex-4 FPGA. Software tool for testing possibilities of the selected units and testing utilization of the programmable structure was also developed.

关键词： programmable Logic Controller Central Processing Unit Bit-Byte (Word) Structure of CPU Scan Time Throughput Time Concurrent Operation field programmable gate array

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Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only) 10

Towards 5ps resolution TDC on a dynamically reconfigurable F...

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Proceedings of the 18th annual ACM/SIGDA international symposium on field programmable gate arrays

作者： Marc-Andre Daigneault Jean Pierre David École Polytechnique de Montréal Montreal PQ Canada

ISBN: (纸本)9781605589114

This paper presents the implementation of a high resolution time-to-digital converter (TDC) on a dynamically reconfigurable FPGA. The TDC architecture is based on the Vernier method using two ring oscillators with slightly different frequencies. The proposed oscillators can be calibrated with picoseconds resolution by taking advantage of partial reconfiguration, and moreover recalibrated over time. The results obtained on a Xilinx Virtex-II Pro FPGA show that the proposed TDC implementation can achieve unprecedented resolutions (on FPGA) as low as 5ps and precisions up to 25ps.

关键词： field programmable gate array time-to-digital converter vernier method dynamic reconfiguration

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A LOW COMPLEXITY SOLUTION FOR INTEGRATING VIDEO SURVEILLANCE AND RFID IN REMOTE SCENE MONITORING

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MICROWAVE AND OPTICAL TECHNOLOGY LETTERS 2010年第3期52卷 775-779页

作者： Tsang, P. W. M. Yung, K. N. So, K. H. Cheung, K. W. K. City Univ Hong Kong Dept Elect Engn Kowloon Hong Kong Peoples R China

In this article, we reported for the first time, a low complexity field programmable gate array solution for integrating video surveillance into RFID units. The method is comprised of two major building blocks, namely a RFID transmitter operating at a maximum bandwidth of 250 kbps, and a near computation free image compression engine based on an enhanced Decomposed Adaptive Decimation scheme. (C) 2010 Wiley Periodicals, Inc. MIcrowave Opt Technol Lett 52 775-779, 2010.

关键词： RFID video surveillance decomposed adaptive decimation field programmable gate array

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A Real-time Synthetic Aperture Beamformer for Medical Ultrasound Imaging 2010

A Real-time Synthetic Aperture Beamformer for Medical Ultras...

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2010 IEEE International Ultrasonics Symposium

作者： Jong-Ho Park Changhan Yoon Jin Ho Chang Yangmo Yoo Tai-Kyung Song Interdisciplinary Program of Integrated Biotechnology Sogang University Seoul Korea Department of Electronic Engineering Sogang University Seoul Korea Sogang Institute of Advanced Technology Sogang University Seoul Korea

ISBN: (纸本)9781457703829

Synthetic aperture (SA) imaging techniques have drawn many attentions since they are capable of providing improved spatial resolution over conventional receive dynamic focusing (CRDF) methods. However, the processing of SA imaging is computationally demanding for real-time processing. Furthermore, massive memories for storing the pre-beamformed radio frequency (RF) data are required, leading to substantial increase in hardware complexity. In this paper, we propose the efficient real-time SA beamformer architecture that could be integrated in modern ultrasound imaging systems. The feasibility of the proposed architecture was demonstrated by implementing a 64-channel SA beamformer on two high-performance field programmable gate arrays (FPGAs, Virtex-5 SX95T, Xilinx, USA). The developed SA beamformer can support up to 12 synthesis beams by utilizing 61percent of slice registers, 43percent of lookup tables (LUTs), 89percent of random access memories (RAMs) and 51percent of digital signal processing (DSP) blocks in each FPGA.

关键词： Synthetic aperture beamformer field programmable gate array dynamic receive focusing radiofrequency random access machine Digital signal processing Synthetic aperture field programmable gate arrays slicing Ultrasonography

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Optical current transformer accuracy problems and solutions

Optical current transformer accuracy problems and solutions

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2010 Asia-Pacific Conference on Power Electronics and Design (APPED 2010)

作者： Guo Weina College of Computer and Automation Hebei Polytechnic University Tangshan,China Huang Wenjie College of Computer and Automation Hebei Polytechnic University Tangshan,China

Explain the factors which affect the performance of optical current transformer (OCT) and Solutions. Signal processing measure is the key to the application of optical current transformer. Therefore the signal processing system’s improved method of optical current transformer was introduced, and prospects the future development of optical current transformers.

关键词： Matlab power system technology optical current transformer faraday effect digital signal processing adaptive interference cancellation field programmable gate array real-time wavelet analysis

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