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Digital-Analog Hybrid Scheme and Its Application to Chaotic Random Number Generators

INTERNATIONAL JOURNAL OF BIFURCATION AND CHAOS 2017年第14期27卷 1750210-1750210页

作者： Yuan, Zeshi Li, Hongtao Miao, Yunchi Hu, Wen Zhu, Xiaohua Nanjing Univ Sci & Technol Sch Elect & Opt Engn Nanjing 210094 Jiangsu Peoples R China Nanjing Univ Aeronaut & Astronaut Coll Elect & Informat Engn Nanjing 210094 Jiangsu Peoples R China

Practical randomnumber generation (RNG) circuits are typically achieved with analog devices or digital approaches. Digital-based techniques, which use field programmable gate array (FPGA) and graphics processing units (GPU) etc. usually have better performances than analog methods as they are programmable, efficient and robust. However, digital realizations suffer from the effect of finite precision. Accordingly, the generated random numbers (RNs) are actually periodic instead of being real random. To tackle this limitation, in this paper we propose a novel digitalanalog hybrid scheme that employs the digital unit as the main body, and minimum analog devices to generate physical RNs. Moreover, the possibility of realizing the proposed scheme with only one memory element is discussed. Without loss of generality, we use the capacitor and the memristor along with FPGA to construct the proposed hybrid system, and a chaotic true random number generator (TRNG) circuit is realized, producing physical RNs at a throughput of Gbit/ s scale. These RNs successfully pass all the tests in the NIST SP800-22 package, confirming the significance of the scheme in practical applications. In addition, the use of this new scheme is not restricted to RNGs, and it also provides a strategy to solve the effect of finite precision in other digital systems.

关键词： field programmable gate array finite precision hybrid scheme random number generator NIST

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Real-time processing of a long perimeter fiber optic intrusion system

Real-time processing of a long perimeter fiber optic intrusi...

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作者： Snider, William Timothy Texas A&M University

This thesis reports on recent advances made in real-time intruder detection for an intrusion system developed at Texas A&M University that utilizes a phase-sensitive optical time-domain reflectometer. The system uses light pulses from a highly coherent laser to interrogate a length of buried optical fiber. The Rayleigh backscattered light is detected, and a FPGA-based system is used to implement real-time signal processing algorithms. With the introduction of real-time signal processing, the system can run continuously, only triggering intrusions when they are detected. These recent advances allow for more effective processing of intruder signatures, while still giving results comparable to previous off-line signal processing results. With these advances, this technology is a prime candidate for low-cost perimeter monitoring of high-value and high-security targets, such as nuclear power plants, military bases, and national borders.

关键词： perimeter security intrusion sensor fiber sensor distributed sensor optical time domain reflectometer field programmable gate array Thesis

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Heterogeneous Sensor Data Analysis Using Efficient Adaptive Artificial Neural Network on FPGA Based Edge gateway

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KSII TRANSACTIONS ON INTERNET AND INFORMATION SYSTEMS 2019年第10期13卷 4865-4885页

作者： Gaikwad, Nikhil B. Tiwari, Varun Keskar, Avinash Shivaprakash, N. C. Indian Inst Sci IISc Dept Instrumentat & Appl Phys CV Raman Ave Bengaluru 560012 India

We propose a FPGA based design that performs real-time power-efficient analysis of heterogeneous sensor data using adaptive ANN on edge gateway of smart military wearables. In this work, four independent ANN classifiers are developed with optimum topologies. Out of which human activity, BP and toxic gas classifier are multiclass and ECG classifier is binary. These classifiers are later integrated into a single adaptive ANN hardware with a select line( s) that switches the hardware architecture as per the sensor type. Five versions of adaptive ANN with different precisions have been synthesized into IP cores. These IP cores are implemented and tested on Xilinx Artix-7 FPGA using Microblaze test system and LabVIEW based sensor simulators. The hardware analysis shows that the adaptive ANN even with 8-bit precision is the most efficient IP core in terms of hardware resource utilization and power consumption without compromising much on classification accuracy. This IP core requires only 31 microseconds for classification by consuming only 12 milliwatts of power. The proposed adaptive ANN design saves 61% to 97% of different FPGA resources and 44% of power as compared with the independent implementations. In addition, 96.87% to 98.75% of data throughput reduction is achieved by this edge gateway.

关键词： Real-time data analysis field programmable gate array adaptive artificial neural network edge gateway fog computing smart wearables

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Robust Haptic Teleoperation by FPGA

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IFAC Proceedings Volumes 2012年第22期45卷 361-366页

作者： Aleš Hace Marko Franc University of Maribor Institute of Robotics Slovenia Isomat d.o.o. Mežica Slovenia

This paper describes a robust algorithm for haptic-based teleoperation. The robust control algorithm was derived by sliding mode control design approach. Such control assures robustness to the disturbances and model uncertainties. Furthermore, the presented design approach guaranties chattering-free performance. Moreover, it is also easy to implement, since the detailed knowledge of the model is not required. The control has been implemented by FPGA in order to realize high control rate which is strongly required for haptic teleoperation. The control algorithm was validated by the 2-DoF laboratory haptic experimental system with linear motors with built-in Hall sensors; therefore no external sensor is required. The experiments validated the proposed control algorithm regarding the robustness and haptic performance.

关键词： haptics bilateral teleoperation motion control sliding mode control field programmable gate array

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Hierarchical hardware trojan for LUT-based AI devices and its evaluation

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ELECTRONICS AND COMMUNICATIONS IN JAPAN 2022年第1期105卷

作者： Nozaki, Yusuke Takemoto, Shu Ikezaki, Yoshiya Yoshikawa, Masaya Meijo Univ Fac Sci & Technol Tenpaku Ku Nagoya Aichi 4688502 Japan Meijo Univ Grad Sch Sci & Technol Tempaku Ku Nagoya Aichi Japan

To realize Society 5.0, edge AI techniques have attracted attention. On the other hand, security issues of edge AI have been reported. In addition, in the field of hardware security, the threat of hardware Trojan (HT) is emphasized. To defend the AI device from malicious attacks, it is important to check the vulnerability against various attacks. Therefore, this study proposes a new HT for AI inference devices. The proposed HT falsifies the inference result with respect to an arbitrary trigger input. The proposed HT concentrates on the Lookup Table (LUT) structure, and can be achieved by rewriting the LUT table information. As a result, the proposed HT does not need additional trojan trigger and payload circuits, that is, it can be implemented without the circuit overhead. Experiments by field programable gate array show the validity of the proposed HT.

关键词： AI security field programmable gate array hardware security hardware Trojan

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FPGA accelerator for CNN: an exploration of the kernel structured sparsity and hybrid arithmetic computation

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JOURNAL OF ELECTRONIC IMAGING 2021年第3期30卷 033034-033034页

作者： Zhang, Guanwen Zhou, Song Duan, Zhemin Zhou, Wei Northwestern Polytech Univ Xian Peoples R China Shandong Prov Res Inst Coal Geol Planning & Explo Jinan Peoples R China

The deployment of large-scale deep neural networks on field programmable gate array (FPGA) platforms is severely hindered by the high requirements on computational resources and off-chip data bandwidth. Traditional nonstructured sparsity algorithms can efficiently reduce the nonzero weights of neural network models. However, the nonstructured sparse connections across channels also degrade the degree of computational parallelism and consequently seriously deteriorate the performance of the FPGA accelerator. We propose an FPGA accelerator by exploring the kernel structured sparsity and hybrid arithmetic computation for the convolutional neural network (CNN). On the one hand, we introduce a hardware-friendly kernel pruning method to reduce the number of arithmetic operations of the CNN model. Our proposed method maintains high accuracy (achieving a less than 0.32% accuracy loss) and achieves a high degree of parallelism. On the other hand, we design a specific hybrid arithmetic computation for the FPGA accelerator to speed up the performance of the pruned CNN model. The FPGA accelerator consists of only 64 sets of hybrid 8-bit and 16-bit floating-point units for the convolution operation. Experiments on VGGNet16 demonstrate that the proposed FPGA accelerator achieves a state-of-the-art 5x convolution operation reduction and a 3x parameter compression. The proposed FPGA accelerator is able to perform at 13.2 FPS, and the corresponding energy efficiency can be boosted up to 1.9 image/J. (C) 2021 SPIE and IS&T

关键词： field programmable gate array convolutional neural network kernel structured sparsity hybrid arithmetic computation

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FPGA control system technology for integrating the PV/wave/FC hybrid system using ANN optimized by MFO techniques

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SUSTAINABLE CITIES AND SOCIETY 2022年第0期80卷 103825-103825页

作者： Talaat, M. Alblawi, Adel Tayseer, M. Elkholy, M. H. Zagazig Univ Fac Engn Elect Power & Machines Dept PO Zagazig 44519 Egypt Shaqra Univ Coll Engn Mech Engn Dept PO Ar Riyadh 11911 Saudi Arabia Egyptian Chinese Univ Fac Engn & Technol PO Cairo 11787 Egypt

Despite the merits of Renewable Energy Sources (RES) as clean and reliable alternatives for electrical energy generation, there are some problems related to their highly cost and low efficient operation with non - linear loads. As one of the most vital methodologies to improve the operational quality of RES within the electrical network, the integration of RES in a one hybrid system can effectively contribute to overcome the obstacles of the randomness and inability to accurately predict the daily generation of each individual RES. In this research, Fuel Cells (FCs) are practically integrated with two renewable sources (wave energy and solar energy) utilizing the field programmable gate array (FPGA) as a new innovative digital controller technique. FPGAs are chosen in this study for its ultra - fast processing speed that is expected to reach to almost 100 MHz and its higher response than other microcontrollers for RES integration. Although the merits of FPGAs like fast response, having no processors and behaving in a parallel manner, there are some obstacles in controlling the energy level of RES during the integration process. To overcome the problems of FPGAs, Moth Flame Optimization (MFO) algorithm is utilized with Artificial Neural Network (ANN) to enhance its operational accuracy for providing an effective and precise forecasting control scenario for the proposed hybrid system. In this paper, FCs are provided as an effective Battery Energy Storage Systems (ESS) to overcome the sudden operational outage of any RES to ensure the reliability of the proposed hybrid system within the electrical network. This research provides the hybrid combination between the Buck - Boost converter and FPGA as a vital approach to adjust the voltage level of the proposed RES integration within a reasonable value. In this research, all the obtained results are assessed based on the available previous simulation and empirical data to confirm the validity and high response of the FPGA

关键词： field programmable gate array Fuel Cells Wave Energy Solar Energy Buck Boost Artificial Neural Network Moth Flame Optimization Algorithm

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Implementation of a tunable hybrid system with coupled high Q-factor resonators based on mode localization for sensing purposes

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SMART MATERIALS AND STRUCTURES 2020年第2期36卷

作者： Humbert, C. Goavec-Merou, G. Walter, V Kacem, N. Leblois, T. Fudan Univ Sch Microelect State Key Lab ASIC & Syst Shanghai 200433 Peoples R China

In this paper, we present a fully tunable system able to generate mode localization between a 170000Q-factor quartz crystal microbalance at 1MHz= 250 degrees C in air. For the TFTs annealed at 300 degrees C for 30 min, the extracted hole and electron field-effect mobility is 1.48 cm(2)V(-1)s(-1) and 0.21 cm(2)V(-1)s(-1), respectively. The performance of both p- and n-type TFTs could be further improved by optimizing fabrication process and post-annealing conditions because of a trade-off between hole and electron mobility.

关键词： tunable hybrid system mode localization digital resonator weak coupling quartz crystal microbalance field programmable gate array

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FFT-Based Simultaneous Calculations of Very Long Signal Multi-Resolution Spectra for Ultra-Wideband Digital Radio Frequency Receiver and Other Digital Sensor Applications

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SENSORS 2024年第4期24卷 1207页

作者： Wu, Chen Low, Michael Def Res & Dev Canada Ottawa Res Ctr Ottawa ON K1A 0Z4 Canada

The discrete Fourier transform (DFT) is the most commonly used signal processing method in modern digital sensor design for signal study and analysis. It is often implemented in hardware, such as a field programmable gate array (FPGA), using the fast Fourier transform (FFT) algorithm. The frequency resolution (i.e., frequency bin size) is determined by the number of time samples used in the DFT, when the digital sensor's bandwidth is fixed. One can vary the sensitivity of a radio frequency receiver by changing the number of time samples used in the DFT. As the number of samples increases, the frequency bin width decreases, and the digital receiver sensitivity increases. In some applications, it is useful to compute an ensemble of FFT lengths;e.g., 2P-j for j=0, 1, 2, horizontal ellipsis , J, where j is defined as the spectrum level with frequency resolution 2j center dot Delta f. Here Delta f is the frequency resolution at j=0. However, calculating all of these spectra one by one using the conventional FFT method would be prohibitively time-consuming, even on a modern FPGA. This is especially true for large values of P;e.g., P >= 20. The goal of this communication is to introduce a new method that can produce multi-resolution spectrum lines corresponding to sample lengths 2P-j for all J+1 levels, concurrently, while one long 2P-length FFT is being calculated. That is, the lower resolution spectra are generated naturally as by-products during the computation of the 2P-length FFT, so there is no need to perform additional calculations in order to obtain them.

关键词： digital receiver discrete Fourier transform fast Fourier transform multi-resolution spectrum blocking fast Fourier transform signal processing field programmable gate array

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Mixed-signal data acquisition system for optically detected magnetic resonance of solid-state spins

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REVIEW OF SCIENTIFIC INSTRUMENTS 2021年第11期92卷 114702-114702页

作者： Zhou, Feifei Song, Shupei Deng, Yuxuan Zhang, Ting Chen, Bing Xu, Nanyang Hefei Univ Technol Sch Phys Hefei 230009 Anhui Peoples R China

We report a mixed-signal data acquisition (DAQ) system for optically detected magnetic resonance (ODMR) of solid-state spins. This system is designed and implemented based on a field-programmable-gate-array chip assisted with high-speed peripherals. The ODMR experiments often require high-speed mixed-signal data acquisition and processing for general and specific tasks. To this end, we realized a mixed-signal DAQ system that can acquire both analog and digital signals with precise hardware synchronization. The system consisting of four analog channels (two inputs and two outputs) and 16 optional digital channels works at up to 125 MHz clock rate. With this system, we performed general-purpose ODMR and advanced lock-in detection experiments of nitrogen-vacancy (NV) centers, and the reported DAQ system shows excellent performance in both single and ensemble spin cases. This work provides a uniform DAQ solution for the NV center quantum control system and could be easily extended to other spin-based systems. Published under an exclusive license by AIP Publishing.

关键词： Collections Editor's Pick Topics Quantum information field programmable gate array Digital signal processing Data acquisition Mixed-signal oscilloscopes Optically detected magnetic resonance

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