Emphasis of the present work is on an elegant real-time solution for GPS/INS integration. Micro-electro mechanical system (MEMS) based inertial sensors are light but not accurate enough for inertial navigation system ...
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Emphasis of the present work is on an elegant real-time solution for GPS/INS integration. Micro-electro mechanical system (MEMS) based inertial sensors are light but not accurate enough for inertial navigation system (INS) applications. An integrated INS/GPS system provides better accuracy compared with either INS or GPS, used individually. This paper describes an improved design and fabrication of a loosely coupled INS-GPS integrated system. The systems currently available use commercial off-the-shelf (COTS) hardware and are, therefore, not optimized for compact, single supply, and low power requirements. In the proposed system, a digital signal processor (DSP) is used for inertial navigation solution and Kalman filter computations. A field programmable gate array (FPGA) is used for creating an efficient interface of the GPS with the DSP. Direct serial interface of the GPS involve tedious processing overhead on the navigation processor. Therefore, a universal asynchronous receiver transmitter (UART) and dual port random axis memory (DPRAM) are created on the FPGA itself. This also reduces the total chip count, resulting in a compact system. The system is designed to give real time processed navigation solutions with an update rate of 100 Hz. All the details of this work are presented.
This paper presents a novel architecture for multi-rate control system with disturbance estimation and rejection using FPGA connected with sensors and actuators through IEEE 1451 standard. A signum function is used fo...
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This paper presents a novel architecture for multi-rate control system with disturbance estimation and rejection using FPGA connected with sensors and actuators through IEEE 1451 standard. A signum function is used for estimation error correction. Estimated states are used to provide the control input at a rate higher or lower than the sample rate thus providing multi-rate control. An architecture is proposed to implement the proposed multi-rate controller in FPGA platform through IEEE 1451.0-2007 standard. The control scheme requires minimum analog hardware, namely comparator and digital to analog convertor and provides multi-bit resolution with multi-rate processing. (c) 2009 Elsevier B.V. All rights reserved.
Fine grained reconfigurable architectures, like Xilinx field programmable gate arrays (FPGAs) provide a high flexibility through runtime re-programming, called dynamic and partial reconfiguration. This feature allows ...
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Fine grained reconfigurable architectures, like Xilinx field programmable gate arrays (FPGAs) provide a high flexibility through runtime re-programming, called dynamic and partial reconfiguration. This feature allows for runtime adaptation of the system architecture and behavior configured on the FPGA. The exploitation of this feature enables to load video image processing algorithms on-demand in order to adapt the configuration in correspondence to the changing requirements of the application depending on the image content. For high resolution sensor images, this novel computing paradigm can provide a huge benefit in power reduction and performance gain for actual and future embedded electronic systems. This paper presents a two dimensional system approach exploiting dynamic and partial reconfiguration in order to adapt the system architecture to the actual requirements of image processing applications. The methodology of runtime reconfiguration can be exploited beneficially for highly adaptive multiprocessor systems. Such systems, different from the traditional static approach for multi-and many-core architectures have the advantage, for providing computational performance directly linked to the requirements of the application. The architecture presented in this paper allows for adapting the processing elements as well as the communication infrastructure which is a novel 2D switch-based Network-on-Chip. The presented approach follows and extends the actual trend in computer science of using many- and multi-core processors for bridging the gap between required computation performance for future application in the field of image processing.
Pulse width modulation （ PWM） drive control digitalization is the key for the full digital invert power supply. New ideas are proposed, which are based on field programmable gate array （ FPGA ）. First, digital PWM...
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Pulse width modulation （ PWM） drive control digitalization is the key for the full digital invert power supply. New ideas are proposed, which are based on field programmable gate array （ FPGA ）. First, digital PWM principles are discussed. The primary and secondary current characteristics are analyzed when the transformer is in both normal and magnetic bias conditions. Second, two digitalization methods are put forward after the research on PWM adjustment principles, which are based on the primary current feedback. Though the two methods could restrain magnetic bias, their realization is difficult. A new method is researched on double close-loops to overcome the above shortcomings, which uses the secondary current as the feedback signal and the primary current as the protection signal. Finally, the secondary current control made is discussed and realized. Welding experimental results show that the method has strong flexibility and adaptability, which can be used to realize the full digital welding power supply.
Network Intrusion Detection Systems (NIDS) detect and prevent numerous security threats in network traffic. Advanced IDS go beyond packet header and examine packet payload to detect content-based security threats. But...
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ISBN:
(纸本)9788184244403
Network Intrusion Detection Systems (NIDS) detect and prevent numerous security threats in network traffic. Advanced IDS go beyond packet header and examine packet payload to detect content-based security threats. But payload scanning is intensive task in IDS, since each packet must be compared against thousands of predefined attacks at multigigabit rate. Software based IDS achieve throughput only at the rate of Mbps, whereas hardware based solutions achieve higher throughput at the rate of Gbps. In this paper we present an optimized hash based algorithm called Word Split Hash algorithm (WSHA) to compare payload against attacks. In previous hash based algorithms the elimination or detection of virus is at last stage after finding hash for the whole word but in WSHA we will do checks after finding subhash values at many stages and also in the final stage. Hence throughput is increased. Also only a bit comparison is carried out for checking purpose after finding the subhash values. So the memory space utilized wil be very much reduced. This string matching algorithm can be implemented in FPGA, which can provide very fast and efficient scanning with less memory space occupied. They are designed and simulated in VHDL using Modelsim tool.
There are large subsets of digital circuits that are designed with bidirectional ports, like microprocessors, peripherals and certain communication circuits. During the design phase, the reliability of these circuits ...
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There are large subsets of digital circuits that are designed with bidirectional ports, like microprocessors, peripherals and certain communication circuits. During the design phase, the reliability of these circuits can be tested by means of fault injection. Traditional fault injection techniques have to arrange the design in order to perform the testing the bidirectional ports, because these tests have to take into account not only errors in the values, but also possible damages in the direction of the data. The present paper presents a solution adopted in an existing fault injection system FT-UNSHADES and the new incoming platform FT-UNSHADES2, for bidirectional signals and the solutions of some practical problems encountered.
To solve the crossing-linkable polyethylene (XLPE) insulation compound purity evaluation problem, a high speed scanning measurement system was designed according to FPGA With the updated information technology and adv...
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ISBN:
(纸本)9781424447541
To solve the crossing-linkable polyethylene (XLPE) insulation compound purity evaluation problem, a high speed scanning measurement system was designed according to FPGA With the updated information technology and advanced electronic devices, It is possible to develop a new inspecting technology for sorting, checking and evaluating material quality, by which defects microscopic images can be real-time recorded, processed and displayed The experimental results demonstrated that defects within 70 mu m similar to 1000 mu m were inspected effectively by the CCD scanning defects inspection instrument, and Good agreement was shown between defects images real-time reconstructed and optical microscopic images not only in shape but also in gray
A power factor correction (PFC) technique based on pre-calculated duty cycle values is presented in this paper. In this method the duty ratios for half a line period are calculated in advance and stored in a memory. B...
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ISBN:
(纸本)9781424446483
A power factor correction (PFC) technique based on pre-calculated duty cycle values is presented in this paper. In this method the duty ratios for half a line period are calculated in advance and stored in a memory. By synchronizing the memory with the line, near unity power factors can be achieved in a specific operating point. The main advantage of this technique is that neither current measurement nor current loop are needed. To obtain stable output voltages a voltage loop is included. A boost converter prototype controlled by an FPGA evaluation board has been implemented in order to verify the functionality of the proposed method. Both the simulation and experimental results show that near unity power factor can be achieved with this PFC strategy.
There are large subsets of digital circuits that are designed with bidirectional ports, like microprocessors, peripherals and certain communication circuits. During the design phase, the reliability of these circuits ...
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There are large subsets of digital circuits that are designed with bidirectional ports, like microprocessors, peripherals and certain communication circuits. During the design phase, the reliability of these circuits can be tested by means of fault injection. Traditional fault injection techniques have to arrange the design in order to perform the testing the bidirectional ports, because these tests have to take into account not only errors in the values, but also possible damages in the direction of the data. The present paper presents a solution adopted in an existing fault injection system FT-UNSHADES and the new incoming platform FT-UNSHADES2, for bidirectional signals and the solutions of some practical problems encountered.
We present a Built-In Self-Test (BIST) approach for testing and diagnosing the embedded digital signal processors (DSPs) in Xilinx Virtex-4 series field programmable gate arrays (FPGAs). The BIST architecture and conf...
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ISBN:
(纸本)9781424433247
We present a Built-In Self-Test (BIST) approach for testing and diagnosing the embedded digital signal processors (DSPs) in Xilinx Virtex-4 series field programmable gate arrays (FPGAs). The BIST architecture and configurations needed to test these programmable DSPs in all of their modes of operation are presented along with fault injection and timing analysis of the BIST configurations.
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