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Vortex-excited acoustic resonance in channel with coaxial side-branches: Vortex dynamics and aeroacoustic energy transfer

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PHYSICS OF FLUIDS 2018年第12期30卷 125104-125104页

作者： Wang, Peng Deng, Yifan Liu, Yingzheng Shanghai Jiao Tong Univ Sch Mech Engn Key Lab Educ Minist Power Machinery & Engn 800 Dongchuan Rd Shanghai 200240 Peoples R China Shanghai Jiao Tong Univ Gas Turbine Res Inst 800 Dongchuan Rd Shanghai 200240 Peoples R China Shanghai Jiao Tong Univ Collaborat Innovat Ctr Adv Ship & Deep Sea Explor Shanghai 200240 Peoples R China

Vortex dynamics and aeroacoustic energy transfer, which play essential roles in vortex-excited acoustic resonance inside straight channels with coaxial side-branches, were investigated by phase-locked particle image velocimetry (PIV) and Howe's acoustic analogy. In the experiments, the periodic acoustic pressure fluctuations at the endplates of the side branches were used to trigger PIV via a field-programmable gate array control system. The results revealed that the spatiotemporal evolution of vortex shedding can be classified into three regions in response to the acoustic standing-wave propagations: the formation region, the convection region, and the collapse region, along with the flapping recirculation zone and the intermittent vertical flow streaks that occur inside the side branches. Further investigation was performed in terms of phase-dependent quantities such as the shear and normal stresses;the normal stress production, which was attributed to the evolution of vortex shedding, was found to be the major contributor to the kinematics and energetics of the self-sustained flow. Finally, Howe's acoustic analogy was used to determine the instantaneous acoustic power and the accumulated aeroacoustic energy during one acoustic resonance cycle. The aeroacoustic energy extracted from the acoustic standing-wave propagations contributed to the formation and subsequent growth of the shedding vortex, whereas the decreased turbulent kinetic energy of the shedding vortex was transferred to the acoustic standing waves to maintain the longitudinal wave propagations. Published by AIP Publishing.

关键词： Acoustic standing waves Aeroacoustics Acoustic phenomena field programmable gate array Flow visualization Vortex dynamics

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Flexible Matrix of Controllers for Real Time Parallel Control

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ENERGIES 2022年第5期15卷 1833-1833页

作者： Chaber, Patryk Wojtulewicz, Andrzej Warsaw Univ Technol Fac Elect & Informat Technol Inst Control & Computat Engn Ul Nowowiejska 15-19 PL-00665 Warsaw Poland

This work aims to develop a novel system, including software and hardware, to perform independent control tasks in a genuine parallel manner. Currently, to control processes with various sampling periods, distributed control systems are most commonly utilized. The main goal of this system is to propose an alternative solution, which allows simultaneous control of both fast and slow processes. The presented approach utilizes FPGA (field programmable gate array) with Nios II processor (Intel Soft Processor Series) to implement and maintain instances of independent controllers. Instances can implement FDMC (Fast Dynamic Matrix Control) and PID (Proportional-Integral-Derivative) control algorithms with various sampling times. The FPGA-based design allows for true independence of controllers' execution both from one another and the managing processor. Also, pure parallel execution allows for implementing slow and fast controllers in the same device. The complete flexible system with a matrix of controllers working in parallel in real-time was tested with both simulated and actual control processes (servomotor), yielding the same results as fully simulated experiments.

关键词： Model Predictive Control Fast Dynamic Matrix Controller field programmable gate array servomotor matrix of controllers

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Unveiling robust security: Chaotic maps for frequency hopping implementation in FPGA

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AIN SHAMS ENGINEERING JOURNAL 2024年第11期15卷

作者： Ayoub, Harith G. Abdulrazzaq, Zaid A. Fathil, Ahmed F. Hasso, Shahd A. Suhail, Aamer T. Northern Tech Univ NTU Tech Management Inst Nineveh Iraq Northern Tech Univ NTU Tech Engn Coll Mosul Iraq Univ Mosul Math Dept Mosul Iraq

Frequency hopping is a main technique for wireless communication, avoiding interference and interception. This paper provides novel hardware design for frequency-hopping pseudorandom bit generator (PRBG).PRBG design by chaotic maps on *** proposed methods in this work first combine chaotic maps in a cascade manner called fixed point cascade chaotic maps (FPCCM-FHSS), and second, the conjunction of chaotic maps done in an XORed manner called fixed point an XOR chaotic method (FPXORCM-FHSS).The results were the first eight NIST randomness *** indicates that all p-values larger than 0.01 are needed to achieve better randomness,Second and third were die-hard tests, many distribution tests with significant p-values (p <0.01) that meet high standards of statistical randomness, making them suitable for channel *** were the FPGA results between the proposed methods for speed and hardware resources).The works implemented on XILINX ZC702 achieved 2 Gbps to meet the speed requirements of the change of the carrier frequency.

关键词： Frequency hopping Xilinx system generator field programmable gate array Chaotic maps

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Hardware implementation of deep neural network for seizure prediction

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AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS 2023年 172卷

作者： Massoud, Yasmin M. Ahmad, Ahmad A. Abdelzaher, Mennatallah Kuhlmann, Levin Abd El Ghany, Mohamed A. German Univ Cairo Cairo Egypt Univ Melbourne Parkville Australia Swinbourne Univ Brain Dynam Lab Melbourne Australia Tech Univ Darmstadt Integrated Elect Syst Lab Darmstadt Germany

Epilepsy is a neurological disorder characterized by seizures, which are caused by a sudden, uncontrollable electrical disturbance in the brain. Recently, machine learning and deep learning techniques have been used in seizure prediction algorithms, which greatly aids epilepsy patients. Moreover, the usage of hardware that is available for both medical practitioners and epilepsy patients would help enhance the quality of life for epilepsy patients. For this purpose, a field-programmable gate array (FPGA) is used in this work to implement a hardware model of a neural network that is able to predict seizures. In this research, the main aim is to implement an FPGA-based general and patient-specific seizure prediction algorithm that detects seizures for epilepsy patients using Multilayer Perceptron (MLP) neural network models. Moreover, the work will also tackle ways to optimize the FPGA resources and the computational time of the seizure prediction models. The data available for training and testing are raw electroencephalogram (EEG) signal samples provided by the Melbourne-NeuroVista seizure trial and the Melbourne-University AES-MathWorks-NIH Seizure Prediction Challenge. The results show that the general model had an Area under curve (AUC) score of 0.72 while the

关键词： Seizure prediction Machine learning Deep learning field programmable gate array

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Coordinated implementation and processing of a unified chassis control algorithm with multi-central processing unit

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PROCEEDINGS OF THE INSTITUTION OF MECHANICAL ENGINEERS PART D-JOURNAL OF AUTOMOBILE ENGINEERING 2010年第D5期224卷 565-586页

作者： Seo, K. Yoon, J. Kim, J. Chung, T. Yi, K. Chang, N. Seoul Natl Univ Dept Mech & Aerosp Engn Sch Mech & Aerosp Engn Seoul 151792 South Korea Seoul Natl Univ Sch Comp Sci Engn Seoul 151792 South Korea Hyundai Mobis Gyunggi Do South Korea

This paper proposes a multi-core architecture for implementation of a unified chassis control (UCC) algorithm on a field programmable gate array (FPGA) which operates as a multi-core process. The proposed multi-core architecture aims to reduce the operating load and maximize the reliability for improving the performance of the UCC system. The proposed multi-core architecture supports distributed control with analytical and physical redundancy capabilities. The UCC algorithm used in this research consists of three parts: a supervisor, a main controller, and fault detection/isolation/tolerance control (FDI/FTC). These three components are implemented and evaluated with the multi-core process environment with the FPGA. An electronic control unit is configured by three Micro Blaze processors with FPGA, and a control area network (CAN) is also implemented for hardware-in-the-loop (HILS) evaluation. Three types of multi-core architectures, i.e. distributed processing, triple voting, and hybrid operation, are implemented to investigate the performance and reliability. A vehicle simulator and brake HILS are used to evaluate the proposed multi-core architectures. From the test results, it is shown that all of the proposed multi-core systems have better performance and improved reliability compared with the single core system. In particular, the hybrid operation architecture shows better reliability and performance compared with the other two multi-core architectures, distributed processing and triple voting.

关键词： electronic control unit fault tolerance control field programmable gate array hardware-in-the-loop simulator multi-core processor unified chassis control

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Software and hardware co-design and implementation of intelligent optimization algorithms

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APPLIED SOFT COMPUTING 2022年第0期129卷

作者： Fu, Zonglin Chu, Shu-Chuan Watada, Junzo Huc, Chia-Cheng Pan, Jeng-Shyang Shandong Univ Sci & Technol Coll Comp Sci & Engn Qingdao 266590 Peoples R China Waseda Univ Grad Sch Informat Prod & Syst Kitakyushu Fukuoka 8080135 Japan Yango Univ Coll Artificial Intelligence Fuzhou 330015 Peoples R China Chaoyang Univ Technol Dept Informat Management Taichung Taiwan

In order to improve the operating efficiency of the algorithm, some intelligent optimization algorithms are considered to be implemented on hardware. However, the existing design scheme has the problem of poor versatility. Therefore, this paper proposes a general software-hardware co-design scheme of intelligent optimization algorithms. In the design scheme, the initialization module and fitness module of the algorithm are deployed on the Advanced RISC Machines (ARM) for execution to increase the flexibility of the program. The update module of the algorithm is deployed on the field programmable gate array (FPGA) for execution to realize the hardware acceleration. The data between ARM and FPGA is transferred through Advanced eXtensible Interface (AXI) bus. In this paper, the PSO, BA, WOA, GWO, CMAES and EO algorithms are implemented with the proposed design scheme. And the six algorithms are tested on thirteen benchmark functions of different types. The experimental results prove the feasibility of the design scheme. In addition, by comparing with software and other implementation methods in execution time, resource occupancy and convergence, the effectiveness and superiority of the proposed scheme are proved. (c) 2022 Elsevier B.V. All rights reserved.

关键词： Intelligent optimization algorithm Advanced RISC machines field programmable gate array Advanced eXtensible interface

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BIDS: An efficient Intrusion Detection System for in-vehicle networks using a two-stage Binarised Neural Network on low-cost FPGA

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JOURNAL OF SYSTEMS ARCHITECTURE 2024年 156卷

作者： Rangsikunpum, Auangkun Amiri, Sam Ost, Luciano Loughborough Univ Wolfson Sch Mech Elect & Mfg Engn Loughborough LE11 3TU England

Automotive networks are crucial for ensuring safety as the number of Electronic Control Units (ECUs) grows to support vehicle intelligence. The Controller Area Network (CAN) is commonly used for efficient in-vehicle communication among ECUs. However, its broadcast nature and lack of a dedicated security layer make it vulnerable to attacks. This paper proposes a novel CAN bus Intrusion Detection System (IDS), named BNNbased IDS (BIDS), which efficiently provides both unknown attack detection and known attack classification using a hierarchical two-stage Binarised Neural Network (BNN) and Generative Adversarial Network (GAN). BIDS was validated on three datasets, and its implementation achieves an average inference time of less than 0.170 ms with minimal resource utilisation on a low-cost field programmable gate array (FPGA). This rapid inference speed enables real-time inference on individual CAN messages using a sliding window technique, eliminating the need to wait for multiple accumulated CAN messages required for data preprocessing. Evaluation metrics demonstrate that our IDS achieves high accuracy in both identifying unseen attacks and categorising known attacks. Furthermore, our FPGA implementation consumes merely 2.09 W, which is a 57% reduction compared to a cutting-edge FPGA-based IDS that is capable of detecting unknown attacks using the same dataset.

关键词： Intrusion Detection System Controller Area Network Machine Learning field programmable gate array Generative Adversarial Network Binarised Neural Network

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GPlace3.0: Routability-Driven Analytic Placer for UltraScale FPGA Architectures

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ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2018年第5期23卷 1–33页

作者： Abuowaimer, Ziad Maarouf, Dani Martin, Timothy Foxcroft, Jeremy Grewal, Gary Areibi, Shawki Vannelli, Anthony Univ Guelph 50 Stone Rd E Guelph ON N1G 2W1 Canada

Optimizing for routability during FPGA placement is becoming increasingly important, as failure to spread and resolve congestion hotspots throughout the chip, especially in the case of large designs, may result in placements that either cannot be routed or that require the router to work excessively hard to obtain success. In this article, we introduce a new, analytic routability-aware placement algorithm for Xilinx UltraScale FPGA architectures. The proposed algorithm, called GPlace3.0, seeks to optimize both wirelength and routability. Our work contains several unique features including a novel window-based procedure for satisfying legality constraints in lieu of packing, an accurate congestion estimation method based on modifications to the pathfinder global router, and a novel detailed placement algorithm that optimizes both wirelength and external pin count. Experimental results show that compared to the top three winners at the recent ISPD'16 FPGA placement contest, GPlace3.0 is able to achieve (on average) a 7.53%, 15.15%, and 33.50% reduction in routed wirelength, respectively, while requiring less overall runtime. As well, an additional 360 benchmarks were provided directly from Xilinx Inc. These benchmarks were used to compare GPlace3.0 to the most recently improved versions of the first- and second-place contest winners. Subsequent experimental results show that GPlace3.0 is able to outperform the improved placers in a variety of areas including number of best solutions found, fewest number of benchmarks that cannot be routed, runtime required to perform placement, and runtime required to perform routing.

关键词： Placement field programmable gate array congestion routing-aware heterogeneous ultrascale architecture

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A parallel decision-making design for highly speedy packet classification

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MICROPROCESSORS AND MICROSYSTEMS 2023年第1期99卷

作者： Adiseshaiah, Midde Sailaja, Maruvada Jawaharlal Nehru Technol Univ Kakinada Dept Elect & Commun Engn Kakinada 533003 Andhra Pradesh India

Packet classification is crucial in computer networks to increase network security because of developments in high-speed data communication. To support different network services including Quality of Service (QoS), se-curity, and resource reservation, network packet classification is a crucial network kernel function. It became extremely challenging to classify arriving packets using the traditional packet classification algorithms at a decent pace due to the rapidly increasing size of rulesets and rule fields in current networks. In addition to hardware-based solutions, numerous contemporary software-based classification techniques have been put out to speed up packet classification. In general, it's critical to manage low latency, fast throughput, and higher energy efficiency with minimal memory needs while designing a packet classification method. In this paper, proposed the architecture makes use of the parallelism provided by current hardware technologies to classify numerous packets at once to improve throughput, reduce energy consumption, and significantly decrease the latency. The suggested high-speed parallel classification procedure uses two DPRAMs (DPRAM1 and DPRAM2) to support multiple read of the data. DPRAMs(Dual Port Random Access Memories) are preferred for stage memory because of their low latency performance, which enables quick rate packet lookup. The packet scheduling module re-ceives the data from the DPRAM. The four successive packet splitter modules receive the packets in parallel. As a result, the packet classification throughput increased. To optimize throughput, and latency while maintaining low energy consumption, facilitating parallel packet classification architecture on FPGA is discussed in this work. Several parameters, including throughput, latency, energy efficiency, and memory requirements, will be eval-uated and compared to traditional methods to assess performance. The classifier offers less latency of 51 ns and the lowest energy

关键词： Dual port random access memory field programmable gate array Packet classification Packet scheduling Software -defined networking

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Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms

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ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2013年第3期6卷 12-12页

作者： Liu, Hanyu Rajavel, Senthilkumar T. Akoglu, Ali Univ Arizona Dept Elect & Comp Engn Tucson AZ 85721 USA

In FPGA CAD flow, the clustering stage builds the foundation for placement and routing stages and affects performance parameters, such as routability, delay, and channel width significantly. Net sharing and criticality are the two most commonly used factors in clustering cost functions. With this study, we first derive a third term, net-length factor, and then design a generic method for integrating net length into the clustering algorithms. Net-length factor enables characterizing the nets based on the routing stress they might cause during later stages of the CAD flow and is essential for enhancing the routability of the design. We evaluate the effectiveness of integrating net length as a factor into the well-known timing (T-VPack)-, depopulation (T-NDPack)-, and routability (iRAC and T-RPack)-driven clustering algorithms. Through exhaustive experimental studies, we show that net-length factor consistently helps improve the channel-width performance of routability-, depopulation-, and timing-driven clustering algorithms that do not explicitly target low fan-out nets in their cost functions. Particularly, net-length factor leads to average reduction in channel width for T-VPack, T-RPack, and T-NDPack by 11.6%, 10.8%, and 14.2%, respectively, and in a majority of the cases, improves the critical-path delay without increasing the array size.

关键词： Design Performance Channel width clustering field programmable gate array net length prediction

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