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Bitwise efficiency in chaotic models

PROCEEDINGS OF THE ROYAL SOCIETY A-MATHEMATICAL PHYSICAL AND ENGINEERING SCIENCES 2017年第2205期473卷 20170144-20170144页

作者： Jeffress, Stephen Duben, Peter Palmer, Tim Univ Oxford Dept Atmospher Phys Oxford England

Motivated by the increasing energy consumption of supercomputing for weather and climate simulations, we introduce a framework for investigating the bit-level information efficiency of chaotic models. In comparison with previous explorations of inexactness in climate modelling, the proposed and tested information metric has three specific advantages: (i) it requires only a single high-precision time series;(ii) information does not grow indefinitely for decreasing time step;and (iii) information is more sensitive to the dynamics and uncertainties of the model rather than to the implementation details. We demonstrate the notion of bit-level information efficiency in two of Edward Lorenz's prototypical chaotic models: Lorenz 1963 (L63) and Lorenz 1996 (L96). Although L63 is typically integrated in 64-bit 'double' floating point precision, we show that only 16 bits have significant information content, given an initial condition uncertainty of approximately 1% of the size of the attractor. This result is sensitive to the size of the uncertainty but not to the time step of the model. We then apply the metric to the L96 model and find that a 16-bit scaled integer model would suffice given the uncertainty of the unresolved sub-grid-scale dynamics. We then show that, by dedicating computational resources to spatial resolution rather than numeric precision in a field programmable gate array (FPGA), we see up to 28.6% improvement in forecast accuracy, an approximately fivefold reduction in the number of logical computing elements required and an approximately 10-fold reduction in energy consumed by the FPGA, for the L96 model.

关键词： information chaos supercomputing inexactness precision field programmable gate array

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Extending the BEAGLE library to a multi-FPGA platform

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BMC BIOINFORMATICS 2013年第1期14卷 1-11页

作者： Jin, Zheming Bakos, Jason D. Univ S Carolina Dept Comp Sci & Engn Columbia SC 29208 USA

Background: Maximum Likelihood (ML)-based phylogenetic inference using Felsenstein's pruning algorithm is a standard method for estimating the evolutionary relationships amongst a set of species based on DNA sequence data, and is used in popular applications such as RAxML, PHYLIP, GARLI, BEAST, and MrBayes. The Phylogenetic Likelihood Function (PLF) and its associated scaling and normalization steps comprise the computational kernel for these tools. These computations are data intensive but contain fine grain parallelism that can be exploited by coprocessor architectures such as FPGAs and GPUs. A general purpose API called BEAGLE has recently been developed that includes optimized implementations of Felsenstein's pruning algorithm for various data parallel architectures. In this paper, we extend the BEAGLE API to a multiple field programmable gate array (FPGA)-based platform called the Convey HC-1. Results: The core calculation of our implementation, which includes both the phylogenetic likelihood function (PLF) and the tree likelihood calculation, has an arithmetic intensity of 130 floating-point operations per 64 bytes of I/O, or 2.03 ops/byte. Its performance can thus be calculated as a function of the host platform's peak memory bandwidth and the implementation's memory efficiency, as 2.03 x peak bandwidth x memory efficiency. Our FPGA-based platform has a peak bandwidth of 76.8 GB/s and our implementation achieves a memory efficiency of approximately 50%, which gives an average throughput of 78 Gflops. This represents a similar to 40X speedup when compared with BEAGLE's CPU implementation on a dual Xeon 5520 and 3X speedup versus BEAGLE's GPU implementation on a Tesla T10 GPU for very large data sizes. The power consumption is 92 W, yielding a power efficiency of 1.7 Gflops per Watt. Conclusions: The use of data parallel architectures to achieve high performance for likelihood-based phylogenetic inference requires high memory bandwidth and a design methodology

关键词： field programmable gate array Memory Bandwidth Memory Controller Target Platform Data Flow Graph

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Multipoint Lock-in Detection for Diamond Nitrogen-Vacancy Magnetometry Using DDS-Based Frequency-Shift Keying

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MICROMACHINES 2024年第1期15卷 14-14页

作者： Hu, Qidi Cheng, Luheng Liu, Yushan Zhu, Xinyi Tian, Yu Xu, Nanyang Zhejiang Lab Res Ctr Quantum Sensing Hangzhou 311000 Peoples R China Hefei Univ Technol Sch Microelect Hefei 230009 Peoples R China Zhejiang Univ Inst Quantum Sensing Hangzhou 310027 Peoples R China Zhejiang Univ Coll Opt Sci & Engn Hangzhou Peoples R China

In recent years, the nitrogen-vacancy (NV) center in diamonds has been demonstrated to be a high-performance multiphysics sensor, where a lock-in amplifier (LIA) is often adopted to monitor photoluminescence changes around the resonance. It is rather complex when multiple resonant points are utilized to realize a vector or temperature-magnetic joint sensing. In this article, we present a novel scheme to realize multipoint lock-in detection with only a single-channel device. This method is based on a direct digital synthesizer (DDS) and frequency-shift keying (FSK) technique, which is capable of freely hopping frequencies with a maximum of 1.4 GHz bandwidth and encoding an unlimited number of resonant points during the sensing process. We demonstrate this method in experiments and show it would be generally useful in quantum multi-frequency excitation applications, especially in the portable and highly mobile cases.

关键词： field programmable gate array quantum precision measurement direct digital synthesizer acquisition and processing equipment microwave source

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An open-source high-frequency lock-in amplifier

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REVIEW OF SCIENTIFIC INSTRUMENTS 2019年第9期90卷 094701-094701页

作者： Stimpson, G. A. Skilbeck, M. S. Patel, R. L. Green, B. L. Morley, G. W. Univ Warwick Dept Phys Coventry CV4 7AL W Midlands England Univ Warwick Diamond Sci & Technol Ctr Doctoral Training Gibbet Hill Rd Coventry CV4 7AL W Midlands England

We present characterization of a lock-in amplifier based on a field programmable gate array capable of demodulation at up to 50 MHz. The system exhibits 90 nV/root Hz of input noise at an optimum demodulation frequency of 500 kHz. The passband has a full-width half-maximum of 2.6 kHz for modulation frequencies above 100 kHz. Our code is open source and operates on a commercially available platform.

关键词： Infinite impulse response Signal processing Demodulators Direct digital synthesis Digital-to-analog converter Software engineering Fourier analysis Amplifiers Telecommunications engineering field programmable gate array

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Low Power Transposed Form 4-Tap Finite Impulse Response Filter Using Power Efficient Multiply Accumulate Unit

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2022年第1期31卷 2250016-2250016页

作者： Rakesh, S. Grace, K. S. Vijula Noorul Islam Ctr Higher Educ Dept Elect & Commun Engn Thuckalay 629180 Tamil Nadu India

Finite impulse response (FIR) filters find wide application in signal processing applications on account of the stability and linear phase response of the filter. These digital filters are used in applications, like biomedical engineering, wireless communication, image processing, speech processing, digital audio and video processing. Low power design of FIR filter is one of the major constraints that researchers are trying hard to achieve. This paper presents the implementation of a novel power efficient design of a 4-tap 16-bit FIR filter using a modified Vedic multiplier (MVM) and a modified Han Carlson adder (MHCA). The units are coded using Verilog hardware description language and simulated using Xilinx Vivado Design Suite 2015.2. The filter is synthesized for the 7-series Artix field programmable gate array with xc7a100tcsg324-1 as the target device. The proposed filter design showed an improvement of a maximum of 57.44% and a minimum of 2.44% in the power consumption compared to the existing models.

关键词： Finite impulse response filter field programmable gate array modified Han Carlson adder modified Vedic multiplier multiply accumulate unit Xilinx Vivado design suite

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DoubleQExt: Hardware and Memory Efficient CNN Through Two Levels of Quantization

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IEEE ACCESS 2021年 9卷 169082-169091页

作者： See, Jin-Chuan Ng, Hui-Fuang Tan, Hung-Khoon Chang, Jing-Jing Lee, Wai-Kong Hwang, Seong Oun Univ Tunku Abdul Rahman Fac Informat & Commun Technol FICT Kampar 31900 Petaling Jaya Malaysia Gachon Univ Dept Comp Engn Seongnam 13120 South Korea

To fulfil the tight area and memory constraints in IoT applications, the design of efficient Convolutional Neural Network (CNN) hardware becomes crucial. Quantization of CNN is one of the promising approach that allows the compression of large CNN into a much smaller one, which is very suitable for IoT applications. Among various proposed quantization schemes, Power-of-two (PoT) quantization enables efficient hardware implementation and small memory consumption for CNN accelerators, but requires retraining of CNN to retain its accuracy. This paper proposes a two-level post-training static quantization technique (DoubleQ) that combines the 8-bit and PoT weight quantization. The CNN weight is first quantized to 8-bit (level one), then further quantized to PoT (level two). This allows multiplication to be carried out using shifters, by expressing the weights in their PoT exponent form. DoubleQ also reduces the memory storage requirement for CNN, as only the exponent of the weights is needed for storage. However, DoubleQ trades the accuracy of the network for reduced memory storage. To recover the accuracy, a selection process (DoubleQExt) was proposed to strategically select some of the less informative layers in the network to be quantized with PoT at the second level. On ResNet-20, the proposed DoubleQ can reduce the memory consumption by 37.50% with 7.28% accuracy degradation compared to 8-bit quantization. By applying DoubleQExt, the accuracy is only degraded by 1.19% compared to 8-bit version while achieving a memory reduction of 23.05%. This result is also 1% more accurate than the state-of-the-art work (SegLog). The proposed DoubleQExt also allows flexible configuration to trade off the memory consumption with better accuracy, which is not found in the other state-of-the-art works. With the proposed two-level weight quantization, one can achieve a more efficient hardware architecture for CNN with minimal impact to the accuracy, which is crucial for IoT applicati

关键词： Quantization (signal) Convolutional neural networks Hardware Memory management field programmable gate arrays Internet of Things Degradation Convolutional neural network quantization Internet of Things deep learning field programmable gate array

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Resource-aware Montgomery modular multiplication optimization for digital signal processing

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JOURNAL OF SYSTEMS ARCHITECTURE 2024年 151卷

作者： Tao, Qiqi Li, Liying Zhou, Junlong Cao, Guitao Meng, Dan East China Normal Univ Shanghai Key Lab Trustworthy Comp Shanghai 200062 Peoples R China East China Normal Univ MoE Engn Res Ctr SW HW Codesign Technol & Applica Shanghai 200062 Peoples R China Nanjing Univ Sci & Technol Sch Comp Sci & Engn Nanjing 210094 Peoples R China Southeast Univ Natl Mobile Commun Res Lab Nanjing 211111 Peoples R China

Homomorphic encryption is an important technology for protecting data privacy, and the performance of modular multiplication directly affects the efficiency of homomorphic encryption. Currently, there are numerous FPGA-based acceleration techniques targeting modular multiplication. However, many of these implementations require substantial hardware resources or suffer from resource imbalance. This leads to a lower throughput. Therefore, we present a novel FPGA-based implementation of Montgomery Modular Multiplication aimed at addressing these challenges. Our design employs a suitable radix bit width and word size based on the digital signal processing (DSP) bit width rather than the conventional binary powers of two. We aim to instantiate more modular multipliers using limited resources while minimizing latency. We also introduce a novel DSP cascade structure, called parallel grouping cascade DSP, which reduces the number of clock cycles of internal multipliers. To balance the ratio of lookup table (LUT) and DSP usage, we also use multipliers implemented in the LUT to replace some DSPs. Our results, implemented on Xilinx Virtex-7 field -programmable gate array (FPGA), demonstrate more than 27% improvement in throughput on 1024bit modular multiplication and more than 70% improvement on 2048 -bit compared to the best previous state-of-the-art references.

关键词： Cryptosystem Large integer arithmetic field programmable gate array Digital signal processing Montgomery modular multiplication

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Novel Record Replacement Algorithm and Architecture for QoS Management over Local Area Networks

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MICROMACHINES 2022年第4期13卷 594-594页

作者： Tung, Yi-Chih Law, Yuk-Wing Hwang, Wen-Jyi Tai, Tsung-Ming Ho, Chih-Hsiang Chen, Cheng-Chang Ming Chi Univ Technol Dept Elect Engn New Taipei 243 Taiwan Natl Taiwan Normal Univ Dept Comp Sci & Informat Engn Taipei 116 Taiwan NVIDIA AI Technol Ctr Taipei 114 Taiwan Inst Informat Ind Taipei 106 Taiwan Bur Stand Metrol & Inspect MOEA Taipei 100 Taiwan

An effective System-on-Chip (SoC) for smart Quality-of-Service (QoS) management over a virtual local area network (LAN) is presented in this study. The SoC is implemented by field programmable gate array (FPGA) for accelerating the delivery quality prediction for a service. The quality prediction is carried out by the general regression neural network (GRNN) algorithm based on a time-varying profile consisting of the past delivery records of the service. A novel record replacement algorithm is presented to update the profile, so that the bandwidth usage of the service can be effectively tracked by GRNN. Experimental results show that the SoC provides self-aware QoS management with low computation costs for applications over virtual LAN.

关键词： System-on-Chip Quality-of-Service field programmable gate array local area network general regression neural network network function virtualization

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Performance verification and latency time evaluation of hardware image processing module for appearance inspection systems using FPGA

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JOURNAL OF REAL-TIME IMAGE PROCESSING 2024年第1期21卷 20-20页

作者： Hoshino, Yukinobu Shimasaki, Masahiro Rathnayake, Namal Dang, Tuan Linh Kochi Univ Technol Sch Syst Engn Tosayamada Kochi 7828502 Japan Univ Tokyo Grad Sch Engn Bunkyo Ku7-3-1 Tokyo 1138656 Japan Hanoi Univ Sci & Technol Sch Informat & Commun Technol 1Dai Co Viet Rd Hanoi 100000 Vietnam

This paper analyzes a hardware-accelerated image processing module for visual inspection systems. These systems are essential for maintaining product quality and decreasing manual inspection. The proposed system harnesses FPGA technology to enhance the efficiency of image processing tasks, with a specific focus on filtering and labeling processes. To evaluate the performance gains achieved through hardware processing, the latency metric is put to use, which holds significant importance in real-time applications. The FPGA-based hardware processing methods have been shown to be highly effective in enhancing the performance of visual inspection systems. The experimental results prove that these methods successfully reduce latency up to the microsecond level, resulting in remarkable improvements in overall system performance. On average, the FPGA-based solution is demonstrated to be 10-100 times faster than conventional processors. Additionally, a notable advantage of this approach is its ability to synchronize processing with the inspection target flow, leveraging the camera device and sensor timing.

关键词： Pipeline image processing Run-length encoding labeling Latency time field programmable gate array

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XOR-Free Approach for Implementation of Polar Encoder

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IEEE Embedded Systems Letters 2024年

作者： Kumar, Navin Kedia, Deepak Purohit, Gaurav Department of Ece Gjus and T Haryana Hisar India CSIR-CEERI Advance Information Technology Group Rajasthan Pilani India

This letter presents a new algorithmic approach to construct an XOR-Free architecture for a non-systematic polar encoder (NSPE). Optimization of XOR units is the main concern while implementing NSPE, which consumes a significant amount of dynamic power. To generate polar sequences of code length N, the approach uses N/2-1 binary patterns extracted from the N/2th order generator matrix GN/2 instead of GN. The algorithm reduces the logical operations by virtue of the recursive patterns, thereby improving hardware (HW) cost. The pattern logics are inferred with 2:1 multiplexers and inverters, making the implementation XOR-Free. An auto HDL code generation script is written targeting variable code lengths (23≤N≥210) for direct comparison with similar approaches, viz. stage folded & punctured NSPE design. The results show that the proposed architecture improves area by 31-83% and power consumption by 15-57% for various N and code rates (R = 1, 1/2) on Virtex-6 FPGA devices. © 2009-2012 IEEE.

关键词： bit patterns field programmable gate array implementation Non-systematic polar encoder recursive

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