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作者： Snider, William Timothy Texas A&M University

This thesis reports on recent advances made in real-time intruder detection for an intrusion system developed at Texas A&M University that utilizes a phase-sensitive optical time-domain reflectometer. The system uses light pulses from a highly coherent laser to interrogate a length of buried optical fiber. The Rayleigh backscattered light is detected, and a FPGA-based system is used to implement real-time signal processing algorithms. With the introduction of real-time signal processing, the system can run continuously, only triggering intrusions when they are detected. These recent advances allow for more effective processing of intruder signatures, while still giving results comparable to previous off-line signal processing results. With these advances, this technology is a prime candidate for low-cost perimeter monitoring of high-value and high-security targets, such as nuclear power plants, military bases, and national borders.

关键词： perimeter security intrusion sensor fiber sensor distributed sensor optical time domain reflectometer field programmable gate array Thesis

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A notion of r -admissibility and its application in logic synthesis

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IFAC Proceedings Volumes 2009年第21期42卷 172-177页

作者： Grzegorz Borowik Tadeusz Łuba Paweł Tomaszewicz Institute of Telecommunications Warsaw University of Technology Warsaw Poland

This paper presents a theory for disjoint and non-disjoint multi-output Boolean function decomposition. This method is dedicated for FPGAs with embedded memory blocks (EMB). Proposed technique is an extension of known approach commonly used for LUT-based FPGA structures. A scheme for generating the set of bound variables that make the function decomposable is presented. Experiments that were carried out show significant area reduction.

关键词： Boolean logic Logic synthesis Decomposition field programmable gate array Logic cell Embedded memory block

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Hardware Implementation of a Robust Adaptive Filter: Two Approaches based in High-Level Synthesis Design Tools

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IFAC Proceedings Volumes 2009年第21期42卷 190-194页

作者： M. Bataller-Mompean A. Rosado-Muñoz E. Soria-Olivas J. Guerrero-Martínez J. Vila-Francés Electronic Engineering Department University of Valencia Valencia Spain

Adaptive filters are used in a wide range of applications. Impulsive noise affects the proper operation of the filter and the adaptation process. This noise is one of the most damaging types of signal distortion, not always considered when implementing algorithms. field programmable gate array (FPGA) are widely used for applications where timing requirements are strict. Nowadays, two main design processes can be followed, namely, Hardware Description Language (HDL) and a High Level Synthesis (HLS) design tool for embedded system design. This paper describes the FPGA implementation of an adaptive filter robust to impulsive noise using two approaches based in HLS and the implementation has been carried out on the Xilinx ISE development system for FPGA prototyping. In order to test the system for functionality and implementation results, a widely used standard system identification problem is implemented. Results are provided in order to test accuracy, performance and logic occupation.

关键词： Adaptive Systems Impulsive Noise field programmable gate array High Level Synthesis System Generator

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A HW/SW Co-Verification Technique for FPGA Test

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Journal of Electronic Science and Technology of China 2009年第4期7卷 390-394页

作者： Yong-Bo Liao Ping Li Ai-Wu Ruan Yi-Wen Wang Wen-Chang Li Key Laboratory of Electronic Thin Fills and Integrated Devices University of Electronic Science ＆ Technology of China Chengdu 610054 China

field programmable gate arrays （FPGAs） have wide and extensive applications in many areas. Due to programmable feature of FPGAs, faults of FPGAs can be easily tolerated if fault sites can be located. A hardware/software （HW/SW） co-verification technique for FPGA test is proposed in this paper. Taking advantage of flexibility and observability of software in conjunction with high-speed simulation of hardware, this technique is capable of testing each input/output block （IOB） and configurable logic block （CLB） of FPGA automatically, exhaustively and repeatedly. Fault cells of FPGA can be positioned automatically by the proposed approach. As a result, test efficiency and reliability can be enhanced without manual work.

关键词： Configurable logic block field programmable gate array hardware/software co-verification input/output block.

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The Study on Real-time Data Processing Based on CCD Scanning and Detecting Device on FPGA

The Study on Real-time Data Processing Based on CCD Scanning...

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2009 IEEE International Conference on Intelligent Computing and Intelligent Systems(ICIS2009)

作者： XU Guo-sheng I.Information and Control Engineering College Weifang University 261061 Weifang China

To solve the crossing-linkable polyethylene （XLPE） insulation compound purity evaluation problem,a high speed scanning measurement system was designed according to *** the updated information technology and advanced electronic devices,it is possible to develop a new inspecting technology for sorting,checking and evaluating material quality,by which defects microscopic images can be real-time recorded,processed and *** experimental results demonstrated that defects within 70μm～1000μm were inspected effectively by the CCD scanning defects inspection instrument,and Good agreement was shown between defects images real-time reconstructed and optical microscopic images not only in shape but also in gray.

关键词： data processing defects inspection field programmable gate array charge coupled device

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Visual Analysis of Ductility/Brittleness of Welding Fracture Points on Charpy Test Specimens Using Graphical Blocks on field programmable gate arrays

Visual Analysis of Ductility/Brittleness of Welding Fracture...

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Conference on Optical Design and Engineering III

作者： Tickle, Andrew J. Camargo-Rodriquez, Anyela Smith, Jeremy S. Univ Liverpool Dept Elect Engn & Elect Liverpool L69 3GJ Merseyside England Univ Ulster Sch Comp & Math Antrim BT370QB England

ISBN: (纸本)9780819473301

The charpy impact is a technique used to evaluate the toughness of an engineering material that determines the amount of energy absorbed by it during fracture. Initially, measurements were estimated manually and later replaced by a PC version. This study reports the development of the field programmable gate array (FPGA) portable version. The FPGA based version allows easy analysis of samples without the need of sending them to a, lab for analysis. The process, presented here,as the original, is based on measuring the percent of crystal in the test sample after impact, to determine if the material is ductile or brittle. The FPGA version, adapted under the MATLAB Simulink environment, shows a graphical block representation of the charpy impact PC version. An important asset of the FPGA version is its portability, it has to be easily modified and downloaded onto a device to estimate the percent of brittle fracture of the broken Charpy surface. The beauty of the DSP Builder programme is that it allows the model to be compiled to various types of optimise code for any Altera FPCA device. To provide a firm basis for scientific comparison to the new FPGA system, images already analysed via the PC based Java system were also used for testing and comparison purposes. The FPGA system converts the image into an 8 bit grayscale image and analyses it in a 5x5 sampling window. This produces texture features that can be used in a comparison system, similar to the Support Vector Machine (SVM) used in the original. The output is a signal that, states the material being tested is brittle or not via, an output of '1' for brittle and a '0' for ductile. A detailed pixel by pixel analysis of the various output images is then investigated to state the percentage difference between the PC and FPGA based systems.

关键词： Charpy Impact Technique field programmable gate array Brittle Analysis Ductile Analysis Image Processing Mathematical Morphology Altera DSP Builder VHDL

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A non-IQ sampling controller in low level RF system

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Chinese Physics C 2008年第10期32卷 852-856页

作者：尹成科戴志敏刘建飞赵玉彬张同宣付泽川刘维清 Shanghai Institute of Applied Physics CASP.O.Box 800-204

This paper describes a non-IQ controller for digital Low Level RF （LLRF） feedback control. Based on this non-IQ sampling method, arbitrary frequency relationship between ADC/DAC sampling clocks and IF signals can be employed. The nonlinearity in digital conversion can be reduced and the system dynamic performance improved. This paper analyzes the nonlinearity in conventional IQ sampling, gives the state variable description of the non-IQ algorithm, presents an implementation and its synchronization, and compares its performances with IQ sampling.

关键词： Shanghai synchrotron radiation facility LLRF non-IQ field programmable gate array

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Hardware-assisted initialisation for constant modulus algorithm adaptive antenna

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IET MICROWAVES ANTENNAS & PROPAGATION 2008年第4期2卷 303-311页

作者： Boonpoonga, A. Sirisuk, P. Chongcheawchamnan, M. Patisang, S. Krairiksh, M. King Mongkuts Inst Technol Ladkrabang Fac Engn Bangkok 10520 Thailand King Mongkuts Inst Technol Ladkrabang Res Ctr Commun & Informat Technol Bangkok 10520 Thailand Mahanakorn Univ Technol Fac Engn Bangkok 10530 Thailand

A cost-effective approach for initialisation of an adaptive antenna based on the constant modulus algorithm (CMA) is proposed. The technique utilises 1 bit phase shifters and a power detector, which are normally integrated with a multibeam antenna, to determine the maximum power beam direction. Consequently, the beam is exploited as an initial beam for CMA. Development of hardware-assisted initialisation is discussed. In addition field programmable gate array implementation of a CMA processor and associated control circuitry is presented. Several simulations are performed to evaluate the performance of the proposed initialisation technique. In addition, the developed prototype is tested with a phase array antenna designed for operation at the IMT2000 frequency of 1.95 GHz. Experimental results confirm superiority of the proposed technique.

关键词： Other analogue circuits field programmable gate arrays multibeam antenna field programmable gate array constant modulus algorithm hardware-assisted initialisation adaptive antenna arrays phase shifters associated control circuitry Logic circuits CMA processor CMA based adaptive antenna Antenna arrays power detector

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QPACE: Quantum Chromodynamics Parallel Computing on the Cell Broadband Engine

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COMPUTING IN SCIENCE & ENGINEERING 2008年第6期10卷 46-54页

作者： Goldrian, Gottfried Huth, Thomas Krill, Benjamin Lauritsen, Jack Schick, Heiko Ouda, Ibrahim Heybrock, Simon Hierl, Dieter Maurer, Thilo Meyer, Nils Schaefer, Andreas Solbrig, Stefan Streuer, Thomas Wettig, Tilo Pleiter, Dirk Sulanke, Karl-Heinz Winter, Frank Simma, Hubert Schifano, Sebastiano Fabio Tripiccione, Raffaele Nobile, Andrea Drochner, Matthias Lippert, Thomas Fodor, Zoltan IBM Res & Dev Lab Boblingen Germany IBM Lab Boblingen Germany IBM Syst & Technol Grp Rochester MN USA IBM Lab Rochester MN USA Univ Regensburg D-8400 Regensburg Germany DESY Zeuthen Germany Univ Milan I-20122 Milan Italy Univ Ferrara I-44100 Ferrara Italy European Ctr Theoret Studies Trento Italy Res Ctr Julich Inst Adv Simulat Julich Germany Julich Supercomp Ctr Julich Germany Univ Wuppertal Wuppertal Germany

Application-driven computers for Lattice Gauge Theory simulations have often been based on system-on-chip designs, but the development costs can be prohibitive for academic project budgets. An alternative approach uses compute nodes based on a commercial processor tightly coupled to a custom-designed network processor. Preliminary analysis shows that this solution offers good performance, but it also entails several challenges, including those arising from the processor's multicore structure and from implementing the network processor on a field-programmable gate array.

关键词： field programmable gate arrays gauge field theory parallel machines quantum chromodynamics system-on-chip cell broadband engine field programmable gate array lattice gauge theory parallel computing system-on-chip designs QCD field-programmable gate array quantum chromodynamics chip scale packaging Network Processor String theory field programmable gate arrays parallel machines PARALLEL PROCESSING (COMPUTERS) system-on-chip Lattice gauge theory

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A hardware design of a massive-parallel, modular NN-based vector quantizer for real-time video coding

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MICROPROCESSORS AND MICROSYSTEMS 2008年第1期32卷 33-44页

作者： Ramirez-Agundis, Agustin Gadea-Girones, Rafael Colom-Palero, Ricardo Inst Technol Celaya Dept Elect Engn Celaya 38010 Gto Mexico Univ Politecn Valencia Dept Elect Engn Valencia 46020 Spain

This report describes the design of a modular, massive-parallel, neural-network (NN)-based vector quantizer for real-time video coding. The NN is a self-organizing map (SOM) that works only in the training phase for codebook generation, only at the recall phase for real-time image coding, or in both phases for adaptive applications. The neural net can be learned using batch or adaptive training and is controlled by an inside circuit, finite-state machine-based hard controller. The SOM is described in VHDL and implemented on electrically (FPGA) and mask (standard-cell) programmable devices. (C) 2007 Elsevier B.V. All rights reserved.

关键词： vector quantization self-organizing map neural network video compression hardware implementation field programmable gate array

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