This paper proposes a technique custom to the optimization requirements suited for a particular family of FPGA. As FPGAs have introduced reconfigurable black boxes there is a need to perform optimization across FPGAs ...
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ISBN:
(纸本)9781424444168
This paper proposes a technique custom to the optimization requirements suited for a particular family of FPGA. As FPGAs have introduced reconfigurable black boxes there is a need to perform optimization across FPGAs slice fabric in order to achieve optimum performance. Though the RTL HDL code should be technology independent but in many design instances it is imperative to understand the target technology especially once the target device embeds dedicated arithmetic blocks. No matter what the degree of optimization of tire algorithm is, the configuration of target device plays an important role as far as the device utilization and path delays are concerned.
This thesis reports on recent advances made in real-time intruder detection for an intrusion system developed at Texas A&M University that utilizes a phase-sensitive optical time-domain reflectometer. The system ...
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This thesis reports on recent advances made in real-time intruder detection for an intrusion system developed at Texas A&M University that utilizes a phase-sensitive optical time-domain reflectometer. The system uses light pulses from a highly coherent laser to interrogate a length of buried optical fiber. The Rayleigh backscattered light is detected, and a FPGA-based system is used to implement real-time signal processing algorithms. With the introduction of real-time signal processing, the system can run continuously, only triggering intrusions when they are detected. These recent advances allow for more effective processing of intruder signatures, while still giving results comparable to previous off-line signal processing results. With these advances, this technology is a prime candidate for low-cost perimeter monitoring of high-value and high-security targets, such as nuclear power plants, military bases, and national borders.
This paper presents a theory for disjoint and non-disjoint multi-output Boolean function decomposition. This method is dedicated for FPGAs with embedded memory blocks (EMB). Proposed technique is an extension of known...
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This paper presents a theory for disjoint and non-disjoint multi-output Boolean function decomposition. This method is dedicated for FPGAs with embedded memory blocks (EMB). Proposed technique is an extension of known approach commonly used for LUT-based FPGA structures. A scheme for generating the set of bound variables that make the function decomposable is presented. Experiments that were carried out show significant area reduction.
Adaptive filters are used in a wide range of applications. Impulsive noise affects the proper operation of the filter and the adaptation process. This noise is one of the most damaging types of signal distortion, not ...
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Adaptive filters are used in a wide range of applications. Impulsive noise affects the proper operation of the filter and the adaptation process. This noise is one of the most damaging types of signal distortion, not always considered when implementing algorithms. field programmable gate array (FPGA) are widely used for applications where timing requirements are strict. Nowadays, two main design processes can be followed, namely, Hardware Description Language (HDL) and a High Level Synthesis (HLS) design tool for embedded system design. This paper describes the FPGA implementation of an adaptive filter robust to impulsive noise using two approaches based in HLS and the implementation has been carried out on the Xilinx ISE development system for FPGA prototyping. In order to test the system for functionality and implementation results, a widely used standard system identification problem is implemented. Results are provided in order to test accuracy, performance and logic occupation.
field programmable gate arrays （FPGAs） have wide and extensive applications in many areas. Due to programmable feature of FPGAs, faults of FPGAs can be easily tolerated if fault sites can be located. A hardware/soft...
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field programmable gate arrays （FPGAs） have wide and extensive applications in many areas. Due to programmable feature of FPGAs, faults of FPGAs can be easily tolerated if fault sites can be located. A hardware/software （HW/SW） co-verification technique for FPGA test is proposed in this paper. Taking advantage of flexibility and observability of software in conjunction with high-speed simulation of hardware, this technique is capable of testing each input/output block （IOB） and configurable logic block （CLB） of FPGA automatically, exhaustively and repeatedly. Fault cells of FPGA can be positioned automatically by the proposed approach. As a result, test efficiency and reliability can be enhanced without manual work.
To solve the crossing-linkable polyethylene （XLPE） insulation compound purity evaluation problem,a high speed scanning measurement system was designed according to *** the updated information technology and advanced...
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To solve the crossing-linkable polyethylene （XLPE） insulation compound purity evaluation problem,a high speed scanning measurement system was designed according to *** the updated information technology and advanced electronic devices,it is possible to develop a new inspecting technology for sorting,checking and evaluating material quality,by which defects microscopic images can be real-time recorded,processed and *** experimental results demonstrated that defects within 70μm～1000μm were inspected effectively by the CCD scanning defects inspection instrument,and Good agreement was shown between defects images real-time reconstructed and optical microscopic images not only in shape but also in gray.
The charpy impact is a technique used to evaluate the toughness of an engineering material that determines the amount of energy absorbed by it during fracture. Initially, measurements were estimated manually and later...
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ISBN:
(纸本)9780819473301
The charpy impact is a technique used to evaluate the toughness of an engineering material that determines the amount of energy absorbed by it during fracture. Initially, measurements were estimated manually and later replaced by a PC version. This study reports the development of the field programmable gate array (FPGA) portable version. The FPGA based version allows easy analysis of samples without the need of sending them to a, lab for analysis. The process, presented here,as the original, is based on measuring the percent of crystal in the test sample after impact, to determine if the material is ductile or brittle. The FPGA version, adapted under the MATLAB Simulink environment, shows a graphical block representation of the charpy impact PC version. An important asset of the FPGA version is its portability, it has to be easily modified and downloaded onto a device to estimate the percent of brittle fracture of the broken Charpy surface. The beauty of the DSP Builder programme is that it allows the model to be compiled to various types of optimise code for any Altera FPCA device. To provide a firm basis for scientific comparison to the new FPGA system, images already analysed via the PC based Java system were also used for testing and comparison purposes. The FPGA system converts the image into an 8 bit grayscale image and analyses it in a 5x5 sampling window. This produces texture features that can be used in a comparison system, similar to the Support Vector Machine (SVM) used in the original. The output is a signal that, states the material being tested is brittle or not via, an output of '1' for brittle and a '0' for ductile. A detailed pixel by pixel analysis of the various output images is then investigated to state the percentage difference between the PC and FPGA based systems.
This paper describes a non-IQ controller for digital Low Level RF （LLRF） feedback control. Based on this non-IQ sampling method, arbitrary frequency relationship between ADC/DAC sampling clocks and IF signals can be...
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This paper describes a non-IQ controller for digital Low Level RF （LLRF） feedback control. Based on this non-IQ sampling method, arbitrary frequency relationship between ADC/DAC sampling clocks and IF signals can be employed. The nonlinearity in digital conversion can be reduced and the system dynamic performance improved. This paper analyzes the nonlinearity in conventional IQ sampling, gives the state variable description of the non-IQ algorithm, presents an implementation and its synchronization, and compares its performances with IQ sampling.
A cost-effective approach for initialisation of an adaptive antenna based on the constant modulus algorithm (CMA) is proposed. The technique utilises 1 bit phase shifters and a power detector, which are normally integ...
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A cost-effective approach for initialisation of an adaptive antenna based on the constant modulus algorithm (CMA) is proposed. The technique utilises 1 bit phase shifters and a power detector, which are normally integrated with a multibeam antenna, to determine the maximum power beam direction. Consequently, the beam is exploited as an initial beam for CMA. Development of hardware-assisted initialisation is discussed. In addition field programmable gate array implementation of a CMA processor and associated control circuitry is presented. Several simulations are performed to evaluate the performance of the proposed initialisation technique. In addition, the developed prototype is tested with a phase array antenna designed for operation at the IMT2000 frequency of 1.95 GHz. Experimental results confirm superiority of the proposed technique.
Application-driven computers for Lattice Gauge Theory simulations have often been based on system-on-chip designs, but the development costs can be prohibitive for academic project budgets. An alternative approach use...
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Application-driven computers for Lattice Gauge Theory simulations have often been based on system-on-chip designs, but the development costs can be prohibitive for academic project budgets. An alternative approach uses compute nodes based on a commercial processor tightly coupled to a custom-designed network processor. Preliminary analysis shows that this solution offers good performance, but it also entails several challenges, including those arising from the processor's multicore structure and from implementing the network processor on a field-programmablegatearray.
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