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15th IEEE International Conference on Image Processing (ICIP 2008)

作者： Hassan, Firas Carletta, Joan Univ Akron Dept Elect & Comp Engn Akron OH 44325 USA

ISBN: (纸本)9781424417650

This paper describes a high throughput encoder for high dynamic range (HDR) images that is compatible with the JPEG2000 engine. A nine-level Reinhard-like tone mapping operator is used to calculate a local illumination estimate around each pixel in the image. Both, the local illumination estimate and the tone mapped pixel streams are sent to the JPEG2000 engine for compression. When tested with HDR images and video, the encoder gave high quality output images with high peak signal-to-noise ratios for a compression rate of 4.8 bits per pixel (bpp). The encoder was implemented on a field programmable gate array (FPGA), and has high enough throughput to support a system processing 1024x768 images of 96 bpp at a rate of 60 frames per second.

关键词： high dynamic range local tone mapping operators field programmable gate array JPEG2000

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Near infrared missile warning testbed sensor

Near infrared missile warning testbed sensor

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Airborne Intelligence, Surveillance, Reconnaissance (ISR) Systems and Applications

作者： McDermott, D. J. Johnson, R. S. Montgomery, J. B. Sanderson, R. B. McCalmont, J. F. Taylor, Mt USAF Res Lab RYJT Wright Patterson AFB OH 45433 USA M&M Aviat Xenia OH 45385 USA MacAulay Brown Inc Dayton OH USA Gen Dynam Corp Dayton OH USA

ISBN: (纸本)9780819471376

Multicolor discrimination is one of the most effective ways of improving the performance of infrared missile warning sensors, particularly for heavy clutter situations. A new tactical airborne multicolor missile warning testbed was developed and fielded as part of a continuing Air Force Research Laboratory (AFRL) initiative focusing on clutter and missile signature measurements for effective missile warning algorithms. The developed sensor test bed is a multi-camera system 1004x 1004 FPA coupled with optimized spectral filters integrated with the optics;a reduced form factor microprocessor-based video data recording system operating at 48 Hz;and a real time field programmable gate array processor for algorithm and video data processing capable of 800B Multiply/Accumulates operations per second. A detailed radiometric calibration procedure was developed to overcome severe photon-limited operating conditions due to the sub-nanometer bandwidth of the spectral filters. This configuration allows the collection and real-time processing of temporally correlated, radiometrically calibrated video data in multiple spectral bands. The testbed was utilized to collect false alarm sources spectra and Man-Portable Air Defense System (MANPADS) signatures under a variety of atmospheric and solar illuminating conditions. Signatures of approximately 100 missiles have been recorded.

关键词： missile warning threat detection algorithms near infrared sensors high speed recorders real time processing field programmable gate array

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Design of a robust adaptive CMAC system for BLDC motors with PI type parameter adaptation

Design of a robust adaptive CMAC system for BLDC motors with...

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7th International Conference on Machine Learning and Cybernetics

作者： Chung, Chao-Ming Hsu, Chun-Fei Lin, Chih-Min Hsu, Chia-Yu Yuan Ze Univ Dept Elect Engn Tao Yuan 320 Taiwan Chung Hua Univ Dept Elect Engn Hsinchu 300 Taiwan

ISBN: (纸本)9781424420957

The main advantage of cerebellar model articulation controller (CMAC) is its fast learning rate compared to other neural networks since it can provide more potential to enrich the mapping relationship between inputs and outputs. This paper proposes a robust adaptive CMAC system for brushless DC motors with PI type parameter adaptation. CMAC is used to mimic an ideal controller based on the Lyapunov stability theory, and the robust controller is designed to achieve L-2 tracking performance with desired attenuation level. The robust adaptive CMAC system is implemented on a field programmable gate array chip and is applied to brushless DC (BLDC) motor control. Some experimental results verify that the proposed robust adaptive CMAC method can achieve good parameter adaptation and favorable tracking performance.

关键词： adaptive control robust control CMAC BLDC motor field programmable gate array

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Lowering power consumption using run-time reconfiguration for stereo rectification

Lowering power consumption using run-time reconfiguration fo...

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Canadian Conference on Electrical and Computer Engineering

作者： Islam, Jamin Chun, Pil Woo MacLean, W. James Kirischian, Lev Ryerson Univ Dept Elect & Comp Engn 350 Victoria St Toronto ON M5B 2K3 Canada Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada

ISBN: (纸本)9781424416424

Trends of high power usage in portable consumer electronics and high speed designs is an important factor that biases the selection of an ASIC over a FPGA. ASICs are optimized to minimize the amount of logics used for a particular application;reductions in power are noticed when compared against FPGAs design for the same application. On the other hand, some FPGAs equipped with run-time reconfiguration, allow portions of the design to be changed on the fly. Having an appropriate methodology which creates a micro-level static architecture and reduces the reconfiguration overhead is used to lower the power consumption. This can allow the FPGA designs to be somewhat competitive against ASIC designs. This paper explores the reconfiguration methodology to lower the power consumption for the application of stereo rectification. The results obtained show significant savings in logical resources and power consumption when compared to ASIC-like FPGA implementations.

关键词： stereo rectification field programmable gate array power consumption run-time reconfiguration micro-level static architecture multi-mode

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Real-time processing of a phase-sensitive distributed fiber optic perimeter sensor

Real-time processing of a phase-sensitive distributed fiber ...

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Conference on Sensors, and Command, Control, Communications and Intelligence (C31) Technologies for Homeland Security and Homeland Defense VI

作者： Madsen, C. K. Snider, T. Atkins, R. Simcik, J. Texas A&M Univ 3128 TAMU College Stn TX 77843 USA BCS Adv Technol LLC Elm Mott TX 76640 USA

ISBN: (纸本)9780819471345

This paper reports on recent advances made in real-time intruder detection for an intrusion system utilizing a phase-sensitive optical time-domain reflectometer developed at Texas A&M University. The system uses light pulses from a highly coherent laser to interrogate an optical fiber. The Rayleigh backscattered light is detected, and real-time processing of the received signal is implemented using an FPGA-based system. Signatures from a single human on foot and automobile have been obtained, and are comparable to results obtained with previous signal processing techniques. Individual footsteps are clearly identified for the single human intruder. With the introduction of real-time signal processing, the system can be run continuously, only triggering intrusions when they are detected. These recent advancements allow us to process intruder signatures more effectively. With these advancements, this technology is a prime candidate for low-cost perimeter monitoring of high-value and high-security targets such as nuclear power plants, military bases, and national borders.

关键词： perimeter security intrusion sensor fiber sensor distributed sensor optical phase sensor optical time domain reflectometer field programmable gate array

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A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications

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ACM Transactions on Reconfigurable Technology and Systems 2008年第1期1卷 1-25页

作者： Wilton, Steven J.E. Quinton, Bradley Ho, Chun Hok Luk, Wayne Leong, Philip H.W. University of British Columbia Vancouver 2332 Main Mall BC Canada V6T 1Z4 Canada Imperial College London 434 Huxley Building South Kensington Campus London SW7 2AZ United Kingdom Department of Computer Science and Engineering The Chinese University of Hong Kong Hong Kong

We present an architecture for a synthesizable datapath-oriented FPGA core that can be used to provide post-fabrication flexibility to an SoC. Our architecture is optimized for bus-based operations and employs a directional routing architecture, which allows it to be synthesized using standard ASIC design tools and flows. The primary motivation for this architecture is to provide an efficient mechanism to support on-chip debugging. The fabric can also be used to implement other datapath-oriented circuits such as those needed in signal processing and computation-intensive applications. We evaluate our architecture using a set of benchmark circuits and compare it to previous fabrics in terms of area, speed, and power. © 2008, ACM. All rights reserved.

关键词： Design field programmable gate array integrated circuit silicon debug system-on-chip Verification

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HIGH-PERFORMANCE SIGNAL PROCESSING ON RECONFIGURABLE PLATFORMS

HIGH-PERFORMANCE SIGNAL PROCESSING ON RECONFIGURABLE PLATFOR...

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作者： Kim, Jung Sub PennState University Libraries

学位级别：Doctor of Philosophy

Reconfigurable platforms have become a promising solution for highperformance signal processing applications due to their flexibleresources, high operating frequency, and low power. However, therequired knowledge of such a reconfigurable platform is growing asthe complexities to use these platforms continue to increase. Thiswork simplifies the use of reconfigurable platforms for targetedsignal processing applications. The first contribution is the designof TANOR, a tool for accelerating applications utilizing numericalalgorithms with large-size data sets. TANOR is targeted at solving arange of N-body interaction problems spanning from astrophysics tomolecular dynamics. The TANOR design flow starts with a MATLABdescription of a particular interaction function and parameterselection from a graphical user interface. Subsequently, TANORautomatically generates a configuration bitstream for a target FPGAalong with associated drivers and control software necessary toexecute the application on a host computer. Architecturalexploration is facilitated through support for standard numberrepresentations such as single precision floating point in additionto support for fully custom fixed-point and floating pointrepresentations. Moreover, TANOR enables joint exploration ofalgorithmic and architectural variations in realizing efficienthardware accelerators. TANOR's effectiveness and adaptability isdemonstrated by generating kernels for three different applications:namely, the gravitational kernel (used in astrophysics), theGaussian kernel (common in image processing applications), and aforce calculation kernel (applied in molecular dynamics). Theresults show that TANOR is capable of achieving identical accuracywith lower resource utilization, making it competitive with existingmanually-designed custom *** second contribution focuses on designing an accelerator for FastFourier Transforms (FFT), which are used extensively in signal anddigital image processing. Since FFT

关键词： Two Dimensional Decomposition field programmable gate array Fast Fourier Transform Numerical algorithms System Generator Hierarchical Memory Controller

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Accelerating string set matching in FPGA hardware for Bioinformatics research

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BMC BIOINFORMATICS 2008年第1期9卷 197-197页

作者： Dandass, Yoginder S. Burgess, Shane C. Lawrence, Mark Bridges, Susan M. Mississippi State Univ Inst Digital Biol Mississippi State MS 39762 USA Mississippi State Univ Dept Comp Sci & Engn Mississippi State MS 39762 USA Mississippi State Univ Life Sci & Biotechnol Inst Coll Vet Med Mississippi State MS 39762 USA Mississippi State Univ Dept Basic Sci Mississippi State MS 39762 USA

Background: This paper describes techniques for accelerating the performance of the string set matching problem with particular emphasis on applications in computational proteomics. The process of matching peptide sequences against a genome translated in six reading frames is part of a proteogenomic mapping pipeline that is used as a case-study. The Aho-Corasick algorithm is adapted for execution in field programmable gate array (FPGA) devices in a manner that optimizes space and performance. In this approach, the traditional Aho-Corasick finite state machine (FSM) is split into smaller FSMs, operating in parallel, each of which matches up to 20 peptides in the input translated genome. Each of the smaller FSMs is further divided into five simpler FSMs such that each simple FSM operates on a single bit position in the input (five bits are sufficient for representing all amino acids and special symbols in protein sequences). Results: This bit-split organization of the Aho-Corasick implementation enables efficient utilization of the limited random access memory (RAM) resources available in typical FPGAs. The use of on-chip RAM as opposed to FPGA logic resources for FSM implementation also enables rapid reconfiguration of the FPGA without the place and routing delays associated with complex digital designs. Conclusion: Experimental results show storage efficiencies of over 80% for several data sets. Furthermore, the FPGA implementation executing at 100 MHz is nearly 20 times faster than an implementation of the traditional Aho-Corasick algorithm executing on a 2.67 GHz workstation.

关键词： field programmable gate array Finite State Machine Random Access Memory Peptide Match Deterministic Finite Automaton

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Microelectronic Implementations of Fractional-Order Integrodifferential Operators

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JOURNAL OF COMPUTATIONAL AND NONLINEAR DYNAMICS 2008年第2期3卷 21301-21301页

作者： Santamaria, Guillermo E. Valverde, Jose V. Perez-Aloe, Raquel Vinagre, Bias M. Univ Extremadura Sch Ind Engn E-06071 Badajoz Spain

For practical applications, the fractional-order integral and differential operators require to be approximated as stable, causal, minimum-phase integer-order systems, which usually leads, in both continuous and discrete domains, to high order transfer functions. Assuming that art approximation of good quality is available for the fractional operator, efficient implementations, in both cost and speed, are required. The fast development of the microelectronics gives us the opportunity of using cheap, accurate, programmable, and fast devices for implementing reconfigurable analog and digital circuits. Among these devices, field programmable gate arrays, switched capacitor circuits, and field programmable analog arrays are used in this paper for the implementation of a fractional-order integrator, previously approximated by recursive Oustaloups method. The fundamentals of the devices as well as the design procedures are given, and the implementations are compared considering their simulated frequency responses, the design efforts, and other important issues.

关键词： fractional order operator field programmable gate array field programmable analog array switched capacitor active filter

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Implementation of a Real-Time FPGA-Based Intelligent Parallel Parking System

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JOURNAL OF ADVANCED COMPUTATIONAL INTELLIGENCE AND INTELLIGENT INFORMATICS 2008年第4期12卷 348-354页

作者： Masmoudi, Mohamed Slim Tsui, Willie Song, Insop Karray, Fakhreddine Masmoudi, Mohamed Derbel, Nabil Ecole Natl Ingenieurs Sfax Elect Engn Dept BP W Sfax 3038 Tunisia Univ Waterloo Elect & Comp Engn Dept Waterloo ON N2L 3G1 Canada Ericsson Inc Warrendale PA 15086 USA

Parallel parking is a challenging maneuver for many drivers, especially in crowded cities with heavy traffic congestion and limited parking spaces. This research focuses on the development of an intelligent parallel parking system. Conventional vehicular control techniques generally require the use of analytical models. However, complexities due to nonlinear car dynamics create multiple challenges when modeling car motion. As fuzzy logic control is appropriate for nonlinear and complex systems where human expert knowledge is available, it is well-suited for the parking application. This paper presents the design and implementation of a real-time fuzzy logic based parallel parking system. Two control units consisting of a main controller and a secondary fuzzy logic controller are utilized. The latter controller is employed for the realization of the wall following task, which has an important role in the parking system. Based on performance and flexibility considerations, the control units are implemented onto a reconfigurable hardware platform, namely a field programmable gate array (FPGA). A prototype vehicle is developed to ensure the proposed algorithm provides vehicular systems with the parallel parking ability.

关键词： field programmable gate array fuzzy logic controller intelligent parking system real-time system

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