For practical applications, the fractional-order integral and differential operators require to be approximated as stable, causal, minimum-phase integer-order systems, which usually leads, in both continuous and discr...
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For practical applications, the fractional-order integral and differential operators require to be approximated as stable, causal, minimum-phase integer-order systems, which usually leads, in both continuous and discrete domains, to high order transfer functions. Assuming that art approximation of good quality is available for the fractional operator, efficient implementations, in both cost and speed, are required. The fast development of the microelectronics gives us the opportunity of using cheap, accurate, programmable, and fast devices for implementing reconfigurable analog and digital circuits. Among these devices, field programmable gate arrays, switched capacitor circuits, and fieldprogrammable analog arrays are used in this paper for the implementation of a fractional-order integrator, previously approximated by recursive Oustaloups method. The fundamentals of the devices as well as the design procedures are given, and the implementations are compared considering their simulated frequency responses, the design efforts, and other important issues.
The prerequisite of data security on network has turned out to be more important. Cryptography is a technique to give data privacy, acceptability and integrity. There are such significant number of difficulties to rea...
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The prerequisite of data security on network has turned out to be more important. Cryptography is a technique to give data privacy, acceptability and integrity. There are such significant number of difficulties to realize cryptography algorithm, for example, execution time, memory requirement, and intention control. In this work, a high secure and low power use of cache memory is implemented for utilizing a new cryptography method specifically named as Undeviating Adaptive Sheltered Cryptography (UASC) algorithm. The outline of the proposed memory has been altered by the expansion of all validation supervisors required by the equipment usage of Advanced Encryption Standard (AES). In addition, UASC has been incorporated into real time application to permit a self-encryption based on full self-rule. Therefore, compared with the conventional design comprising of a crypto-block and an isolated memory, this new method will prompt an imperative decrease of data interactions among the encryption procedure. The proposed work is depicted utilizing Verilog language, synthesized and actualized utilizing Xilinx ISE suite based field programmable gate array (FPGA) devices. Synthesis results demonstrate that the proposed configuration accomplishes higher efficiency than the previous executions by decreasing area while keeping up a moderate throughput/Look UpTable (LUT) ratio. The proposed configuration is additionally more productive as far as power utilization is concerned. As compared with conventional method, the proposed Undeviating Adaptive Sheltered Cryptography achieves low power consumption for 23.02 mu w and execution time is 9.5 s. (C) 2019 Elsevier B.V. All rights reserved.
In the state-of-the-art field-programmablegatearrays (FPGAs), logic circuits are synthesized and mapped on clusters of look-up tables. However, arithmetic operations benefit from an existing dedicated adder along wi...
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In the state-of-the-art field-programmablegatearrays (FPGAs), logic circuits are synthesized and mapped on clusters of look-up tables. However, arithmetic operations benefit from an existing dedicated adder along with a carry chain used to ensure a fast carry propagation. This carry chain is a dedicated wire available in the architecture of the FPGA and is as such independent of the external programmable routing resources. In this paper, we propose a variable-structure Boolean matching technology mapper with embedded decomposition techniques to map nonarithmetic logic functions on carry chains. Previously synthesized and mapped logic functions are adapted so that their outputs are routed using the dedicated carry chains instead of the external programmable interconnects. The experimental results show a reduction in the used routing resources as well as the circuit area when using this Boolean matching-based mapper on the Altera Stratix-III FPGA.
Based on the adaptive logic module structure implemented in a 28 nm field programmable gate array (FPGA), we propose an interleaved sampling method, together with bin realignment operation, to enable time-to-digital c...
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Based on the adaptive logic module structure implemented in a 28 nm field programmable gate array (FPGA), we propose an interleaved sampling method, together with bin realignment operation, to enable time-to-digital converter (TDC) implementation. The tap status is sampled twice in a single physical channel, meaning that TDC precision beyond the cell delay limit can be anticipated. Two TDC channels were implemented in a 28 nm Cyclone-V FPGA, and the effectiveness of the proposed method was evaluated. After calibration, the TDC produced a timing resolution of 6.6 ps root mean square or 5.8 ps per least significant bit. Published under license by AIP Publishing.
Recent advances in power converter applications with highly demanding control goals require the efficient implementation of superior control strategies. However, the real-time application of such control strategies de...
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Recent advances in power converter applications with highly demanding control goals require the efficient implementation of superior control strategies. However, the real-time application of such control strategies demands high computational power that necessitates efficient digital controllers like field programmable gate array (FPGA). The inherent parallelism offered by FPGAs minimizes the execution time and exhibits an excellent cost-performance trade-off. In addition, rapid advancements in FPGA technology with a broad portfolio of intellectual property (IP) cores, design tools, and robust embedded processors resulted in a design paradigm shift. This article proposes a low-cost solution for the resource-optimized implementation of dynamic, highly accurate, and computationally intensive finite state-predictive direct current control (FS-PDCC). The challenges for implementing complex control algorithms for power converters are discussed in detail, and the control is implemented in Intel's low-cost non-volatile FPGA-MAX (R) 10. An efficient design methodology using finite state machine (FSM) is adopted to achieve time/resource-efficient implementation. The parallel and pipelined architecture of FPGA provides better resource utilization with high execution speed. The experimental results prove the efficiency of FPGA-based cost-effective solutions that offer superior performance with better output quality.
This paper presents a theory for disjoint and non-disjoint multi-output Boolean function decomposition. This method is dedicated for FPGAs with embedded memory blocks (EMB). Proposed technique is an extension of known...
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This paper presents a theory for disjoint and non-disjoint multi-output Boolean function decomposition. This method is dedicated for FPGAs with embedded memory blocks (EMB). Proposed technique is an extension of known approach commonly used for LUT-based FPGA structures. A scheme for generating the set of bound variables that make the function decomposable is presented. Experiments that were carried out show significant area reduction.
The conception of the hardware-software platform is presented in the paper. Presented platform is designed in order to test different constructions of the central processing units dedicated to programmable logic contr...
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The conception of the hardware-software platform is presented in the paper. Presented platform is designed in order to test different constructions of the central processing units dedicated to programmable logic controllers. Selected hardware solutions for the PLC dual processor bit-byte (word) CPUs, which are oriented for optimised maximum utilization of capabilities of the two-processor architecture of the CPU are presented in the paper. The key point is preserving high speed of instruction processing by the bit-processor, and high speed and functionality of the byte (word)-processor. The structure should enable the processors to work in concurrent mode as far as it is possible, and minimize the situations, when one processor has to wait for the other. Designed platform is based on the development board equipped with Xilinx Virtex-4 FPGA. Software tool for testing possibilities of the selected units and testing utilization of the programmable structure was also developed.
Discrete cosine transform (DCT) is frequently used in image and video signal processing due to its high energy compaction property. Humans are able to perceive and identify the information from slightly erroneous imag...
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Discrete cosine transform (DCT) is frequently used in image and video signal processing due to its high energy compaction property. Humans are able to perceive and identify the information from slightly erroneous images. It is enough to produce approximate outputs rather than absolute outputs which in turn reduce the circuit complexity. Numbers of applications like image and video processing need higher dimensional DCT algorithms. So the existing architectures of one dimensional (1D) approximate DCTs are reviewed and extended to two dimensional (2D) approximate DCTs. Approximate 2D multiplier-free DCT architectures are coded in Verilog, simulated in Modelsim to evaluate the correctness, synthesized to evaluate the performance and implemented in virtexE field programmable gate array (FPGA) kit. A comparative analysis of approximate 2D DCT architectures is carried out in terms of speed and area.
In this manuscript, previously trained Convolutional neural network (CNN), Quantum Neural Network (QNN), and Binarized Neural Network (BNN) models performed employing Tensor Flow's Application Programming Interfac...
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In this manuscript, previously trained Convolutional neural network (CNN), Quantum Neural Network (QNN), and Binarized Neural Network (BNN) models performed employing Tensor Flow's Application Programming Interface (API) for real-time object detection and implemented on FPGA. Then, the proposed real time objects detection based on CNN, QNN and BNN Deep Neural Networks classifier mode activated on python, and then the dataset taken from PASCAL VOC. For an accuracy analysis of real time objection detection, this real time objects detection based on CNN Deep Neural Networks classifier provide 3.458% and 1.600% higher accuracy value than proposed real time objects detection. Then, the proposed real time objects detection based on CNN, QNN and BNN Deep Neural Networks classifier model verified by using the Verilog programming language in the Xilinx ISE 14.5 design tools in the ZYNQ FPGA development team. These results show the FPGA implementation of this real time objects detection based on CNN Deep Neural Networks classifier model meets the objective efficiently.
Intensity modulation/direct detection (IM/DD) orthogonal frequency division multiplexing (OFDM) is very suitable for high-speed cost-sensitive passive optical network (PON) applications. However, real-time OFDM system...
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Intensity modulation/direct detection (IM/DD) orthogonal frequency division multiplexing (OFDM) is very suitable for high-speed cost-sensitive passive optical network (PON) applications. However, real-time OFDM systems are sensitive to synchronization bias, and thus symbol timing synchronization (STS) becomes a critical issue. We proposed a proportional-sign cross-correlation (PS-CC) STS algorithm with the advantages of distance-independence and low resource utilization. In the proposed PS-CC STS algorithm, the sign operation is applied instead of the multiplication operation with high computational complexity to decrease the resource utilization and the characteristic of low resource utilization will drive its application in real-time systems. Meanwhile, we use field programmable gate array (FPGA) to design a baseband IM/DD OFDM receiver with pipeline structure and built a universal loop test system, which is applied to implement the proposed PS-CC STS algorithm and evaluate its performance. In the experiment of a 16-QAM OFDM-PON system, a 30-km fiber transmission only results in 1.98% ripple on the peak amplitude of correlation, which verifies the distance-independence of the proposed method.
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