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Simulation and development environment for mobile 3D graphics architectures

IET COMPUTERS AND DIGITAL TECHNIQUES 2007年第5期1卷 501-507页

作者： Lee, W.-J. Park, W.-C. Srini, V. P. Han, T.-D. Yonsei Univ Coll Engn Dept Comp Sci Media Syst Lab Seoul 120749 South Korea Sejong Univ Sch Comp Engn Dept Internet Comp Seoul 143747 South Korea Data Flux Syst Inc Berkeley CA USA

This paper describes a simulation and development environment for designing mobile three-dimensional (3D) graphics architectures. The proposed simulation and verification environment (SVE) uses glTrace's ability to intercept and redirect an OpenGL vertical bar ES streams. The SVE simulates the behaviour of mobile 3D graphics pipeline during the playback of traces and produces the second geometry trace that can be used as a test vector for the Verilog/hardware discription language RT-level model. An architectural verification can be conducted by comparing the frame-by-frame results. The functionality of the SVE is demonstrated by designing a mobile 3D graphics architecture and implementing the verified architecture on field programmable gate array (FPGA) boards. An application development environment (ADE) is also presented that includes a mobile graphics application programming interface and a device driver interface. The proposed SVE and the ADE could be efficiently used for developing and testing mobile applications, architectural analysis and hardware designs.

关键词： device drivers FPGA application development environment verification environment rendering (computer graphics) computer graphic equipment application program interfaces RT-level model mobile 3D graphics architecture application programming interface mobile computing graphics rendering device driver interface hardware discription language Verilog field programmable gate array simulation

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A novel envelope detector for high-frame rate, high-frequency ultrasound imaging

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IEEE TRANSACTIONS ON ULTRASONICS FERROELECTRICS AND FREQUENCY CONTROL 2007年第9期54卷 1792-1801页

作者： Chang, Jin Ho Yen, Jesse T. Shung, K. Kirk Ctr Med Ultrasonic Transducer Technol NIH Transducer Resource Dept Biomed Engn Los Angeles CA USA

This paper proposes a novel design of envelope detectors capable of supporting a small animal cardiac imaging system requiring a temporal resolution of more than 150 frames per second. The proposed envelope de tector adopts the quadrature demodulation and the look-up table (LUT) method to compute the magnitude of the complex baseband components of received echo signals. Because the direct use of the LUT method for a square root function is not feasible due to a large memory size, this paper presents a new LUT strategy dramatically reducing its size by using binary logarithmic number system (BLNS). Due to the nature of BLNS, the proposed design does not require an individual LOG-compression functional block. In the implementation using a field programmable gate array (FPGA), a total of 166.56 Kbytes memories were used for computing the magnitude of 16-bit in-phase and quadrature components instead of 4 Gbytes in the case of the direct use of the LUT method. The experimental results show that the proposed envelope detector is capable of generating LOG-compressed envelope data at every clock cycle after 32 clock cycle latency, and its maximum error is less than 0.5 (i.e., within the rounding error), compared with the arithmetic results of square root function and LOG compression.

关键词： biomedical ultrasonics cardiology demodulation field programmable gate arrays medical image processing LOG-compression functional block binary logarithmic number system echo signals envelope detector field programmable gate array look up table method qua clock cycle Medical image processing Square root field programmable gate arrays Envelope detectors Cardiology biomedical ultrasonics quadrature demodulation Demodulation ECHO SIGNAL

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DESIGN OF A SIMPLIFIED FUZZY INFERENCE ENGINE USING FPGA

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CONTROL AND INTELLIGENT SYSTEMS 2007年第2期35卷 175-182页

作者： Ahmad, N. Pottathuparambil, R. Marine Biomedicine and Environmental Sciences Medical University of South Carolina 221 Fort Johnson Road Charleston South Carolina 29412

This paper presents the design of a simplified version of fuzzy inference engine (FIE) built on an Altera Flex 10K field programmable gate array (FPGA). This approach uses a modified center of area method. By introducing some constraints on the defined fuzzy subsets the computational speed of the FIE is made faster. The approach discussed in this paper removes the division bottleneck and keeps the fuzzy look-up tables small, thereby reducing the computational complexity of the FPGA. Parallelism is introduced in accessing the memory, thereby increasing the computational speed. A speed of 2.5 M FLIPS is achieved with a speed grade of 25 MHz.

关键词： field programmable gate array fuzzy inference real-time window target

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3D vision: Developing an embedded stereo-vision system

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COMPUTER 2007年第5期40卷 106-108页

作者： Woodfill, John Iselin Buck, Ron Jurasek, Dave Gordon, Gaile Brown, Terrance Tyzx

The DeepSea G2 stereo vision system that Tyzx developed features an embedded stereo camera consisting of two CMOS imagers, a Tyzx DeepSea 2 stereo application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a DSP/coprocessor, a PowerPC running Linux, and an Ethernet connection. About the size of a hardback book, the G2 delivers real-time - 30 frames per second (fps) - interpretations of visual data even in challenging environments and has been deployed in a variety of applications, including person-tracking and autonomous-vehicle navigation.

关键词： Application Specific Integrated Circuits CMOS Image Sensors Computer Vision Digital Signal Processing Chips Linux Local Area Networks Stereo Image Processing 3 D Vision Embedded Stereo Vision System Tyzx Deep Sea G 2 Stereo Vision System Embedded Stereo Camera CMOS Imager Tyzx Deep Sea 2 Stereo Application Specific Integrated Circuit field programmable gate array DSP Coprocessor Linux Ethernet Person Tracking Application Autonomous Vehicle Navigation Application Application Specific Integrated Circuits field programmable gate arrays Stereo Vision CMOS Image Sensors Cameras Digital Signal Processing Coprocessors Linux Ethernet Networks Books Embedded Computing Stereo Vision Systems 3 D Vision

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Generic data acquisition system for multi-dimensional radiation detectors

Generic data acquisition system for multi-dimensional radiat...

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IEEE Nuclear Science Symposium/Medical Imaging Conference

作者： Lynch, Adam W. Berry, Andrew Panjkovic, Goran Lewis, Rob Monash Univ Monash Ctr Synchrotron Sci Melbourne Vic 3004 Australia

ISBN: (纸本)9781424409228

The instrumentation group at the Monash Centre for Synchrotron Science have developed a low cost generic data acquisition system. This system is to be used in a variety of applications and to assist in the design and testing of emerging detectors. The system utilises a desktop PC which interfaces to a detector via one or more custom 64-bit PCI cards, each equipped with an Altera CycloneII (TM) FPGA (200) and plug-in daughter boards, this provides flexibility to easily customise analogue and digital signal processing. A GUI application controls the system via variables and scripts, renders and analyses real-time data, and supports importing and exporting in a variety of formats. This paper presents an overview of the data acquisition system and the process of interfacing with a two-dimension multi-wire proportional chamber with delay-line readout with an expected timing resolution of 10 ps.

关键词： data acquisition field programmable gate array nuclear electronics instrumentation computing readout electronics x-ray detectors

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Code generator implementation on FPGA for an optical ZCZ code using a Sylvester type Hadamard matrix

Code generator implementation on FPGA for an optical ZCZ cod...

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3rd International Workshop on Signal Design and Its Applications in Communications (IWSDA 07)

作者： Matsumoto, Takahiro Matsufuji, Shinya Yamaguchi Univ Grad Sch Sci & Engn Ube Yamaguchi 7558611 Japan

ISBN: (纸本)9781424410736

The optical ZCZ code is a set of pairs of binary and bi-phase sequences with zero correlation zone. An optical code division multiple access (CDMA) system using this code can remove co-channel interference and influence of multi-path. We proposed the compact construction of a bank of matched filters for this code in a receiver. But we have not proposed the construction of a code generator for this code in a transmitter yet. In this paper, we propose the construction of two code generators for an optical ZCZ code using a Sylvester-type Hadamard matrix, which are called ROM-type and non ROM-type code generators. This ROM-type code generator can be constructed by a ROM and a up-counter. Similarly, this non ROM-type code generator can be constructed by a up-counter, flip-flops and logic gates. The ROM-type and non ROM-type code generators are implemented on a field programmable gate array (FPGA) corresponding to 400, 000 logic gates, and the non ROM-type code generator can reduce logic elements than the ROM-type code generator.

关键词： optical communication optical ZCZ code optical CDMA system code generator field programmable gate array

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A high throughput encoder for high dynamic range images

A high throughput encoder for high dynamic range images

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IEEE International Conference on Image Processing (ICIP 2007)

作者： Hassan, Firas Carletta, Joan Univ Akron Dept Elect & Comp Engn Akron OH 44325 USA

ISBN: (纸本)9781424414369

An encoder for high dynamic range (HDR) images is proposed that is compatible with the JPEG2000 compression engine and can provide three different versions of the image to the user at the receiver end depending on his needs. The first version is a gray scale HDR image. The second is a local tone-mapped version of the color HDR image suitable for display on conventional devices. By combining data from the first two versions, the original color HDR image can be reconstructed. The proposed HDR encoder was implemented on a field programmable gate array, and has high enough throughput to support a system processing 1024x768 images at a rate of 60 frames per second.

关键词： high dynamic range field programmable gate array JPEG2000

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Experimental considerations on adjustable dead-time control scheme for resonant snubber inverter

Experimental considerations on adjustable dead-time control ...

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4th Power Conversion Conference (PCC-Nagoya 2007)

作者： Hoshi, Nobukazu Hachiga, Yuki Kurihara, Hiroko Ibaraki Univ 4-12-1 Nakanarusawa Cho Ibaraki 3168511 Japan

ISBN: (纸本)9781424408436

This paper proposes adjustable dead-time control scheme, which avoid the failure of natural zero voltage switching (ZVS) turn-on in low output current in auxiliary resonant snubber inverters (RSIs). RSI achieves ZVS in the inverter main switches using auxiliary circuit;however, additional conduction loss is caused by using the auxiliary circuit simultaneously. The additional conduction loss can be suppressed by decrease of the operating frequency of the auxiliary circuit using natural ZVS, in which ZVS can be achieved without using the auxiliary circuit by using the output current. However, natural ZVS turn-on is failed near zero output current when the dead-time was constant. This paper describes the basic concept of the proposed control scheme and the developed controller using a FPGA (field programmable gate array). In addition, it was confirmed that the control scheme is effective for the natural ZVS failure problem by PSpice simulations and experiments in single-phase RSI.

关键词： soft switching inverter zero voltage switching field programmable gate array power conversion efficiency

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A high speed block convolution using ancient Indian vedic mathematics

A high speed block convolution using ancient Indian vedic ma...

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7th International Conference on Computational Intelligence and Multimedia Applications

作者： Hanumantharaju, M. C. Jayalaxmi, H. Renuka, R. K. Ravishankar, M. Acharya Inst Technol Dept E&C Bangalore 560090 Karnataka India Dayanand Sagar Coll Engn Dept ISE Bangalore 560078 Karnataka India

ISBN: (纸本)9780769530505;0769530508

In Digital Signal Processing applications, the convolution with a very long sequence is often required. In order to compute convolution of long sequence, Overlap-Add method (OLA) and Overlap-Save method (OLS) method can be considered The OLA and OLS are well know efficient schemes for high-order filtering. The most commonly used implementation for digital filtering algorithms are Digital Signal Processors, special purpose Digital Filtering chips and Application Specific Integrated Circuits (ASICs) for large volumes. In this paper, a high performance, high throughput and area efficient architecture for the field programmable gate array (FPGAs) implementation of block convolution process is proposed The most significant aspect of the proposed method is the development of a multiplier architecture based on vertical and crosswise structure of Ancient Indian Vedic Mathematics and embedding if in OLA and OLS methods for improved efficiency. The coding is done ill VHDL (Very High Speed Integrated Circuits Hardware Description Language) and the FPGA synthesis is done using Xilinx Spartan library. The results shows that OLA and OLS method of block convolution implemented using Vedic multiplication is efficient in terms of area/speed compared to its implementation using conventional multiplier architectures.

关键词： convolution digital filters field programmable gate arrays hardware description languages FPGA VHDL ancient Indian Vedic mathematics digital filtering algorithms digital signal processing field programmable gate array high speed block convolution process field programmable gate arrays Convolution Digital filters

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A Synthesizable Datapath-Oriented Embedded FPGA Fabric 07

A Synthesizable Datapath-Oriented Embedded FPGA Fabric

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15th ACM/SIGDA International Symposium on field-programmable gate arrays

作者： Wilton, Steve J. E. Ho, C. H. Leong, Philip H. W. Luk, Wayne Quinton, Brad Univ British Columbia Dept Elect & Comp Engn Vancouver BC V5Z 1M9 Canada

ISBN: (纸本)9781595936004

We present an architecture for a synthesizable datapath-oriented field programmable gate array (FPGA) core which can be used to provide post-fabrication flexibility to a System-on-Chip (SoC). Our architecture is optimized for bus-based operations that are common in signal processing and computation intensive applications. It employs a directional routing architecture, which allows it to be synthesized using standard ASIC design tools and flows. We also describe a proof-of-concept layout of our core. It is shown that the proposed architecture is significantly more area efficient than the best previously reported synthesizable programmable logic core.

关键词： field programmable gate array Datapath Synthesis Integrated Circuit System-on-Chip Embedded Block

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