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International Core Journal of Engineering 2023年第11期9卷 71-75页

作者： Wenbin Mu Hao Wu

This article uses the subway traction power supply model as a simulation model to study the efficient and accurate real-time simulation of power systems with limited computing resources and real-time constraints. It focuses on the resource optimization configuration method for multi-hardware real-time simulators. Firstly, the article distinguishes the tasks suitable for different hardware based on their different computing characteristics, the generality of CPU, and the inherent high parallelism and stronger computing capabilities of FPGA. Then, it adopts a physics-decoupled method to perform fine-grained partitioning of the resource occupation rate required for processing tasks on each hardware, so that each module can operate with the minimum resource occupation rate on the hardware, maximizing hardware resource savings and computational *** multi-level parallel real-time simulation architecture is formed through the coordination allocation of the coarse-grained and fine-grained partitioned model on the hardware, from hardware level, module level, to element level.

关键词： Real-time Simulator field programmable gate array Resource Optimization Allocation

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An Application Specific Reconfigurable Architecture with Reduced Area and Static Memory Cells

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2021年第4期30卷

作者： Iqbal, Muhammad Mazher Parvez, Husain Hussain, Fasahat Rashid, Muhammad Karachi Inst Econ & Technol Karachi 75190 Pakistan Digitek Engn Karachi Pakistan Umm Al Qura Univ Coll Comp & Informat Syst Comp Engn Dept Mecca Saudi Arabia

An Application Specific Inflexible FPGA (ASIF) is a tailored design, for a given group of known circuits, which is generated by extensively reducing the routing resources of an FPGA. In an ASIF, different dynamically reconfigurable application circuits are initially mapped and tested on an FPGA fabric. Subsequently, the FPGA fabric is reduced to achieve an efficient architecture for known application circuits. However, a large portion of ASIF is still occupied by fully flexible logic blocks, containing the same amount of area and SRAM memory cells, as found in a traditional FPGA. Thus, here lies a potential to further optimize the logic blocks of an ASIF at the expense of removing or reducing their reconfigurability. This work optimizes the logic blocks of an ASIF through the SRAM-Table sharing technique, without compromising their reconfigurability. Moreover, the routing channels of ASIF are further optimized by applying the Boolean functions (gates) insertion technique. The applied techniques (SRAM-Table sharing and Boolean functions insertion) not only reduce the area, delay and power, but also minimize the reconfiguration time, bitstream size and the size of external memory required to store the bitstream of circuits. This optimized version of ASIF is termed as ASIF++. Furthermore, an embedded FPGA in a System-on-Chip that requires the partial dynamic reconfiguration for known circuits, can be automatically reduced to an ASIF++. It is found through experimental results that an ASIF++ is 4-9% area-efficient and requires 36% lesser number of SRAM cells, as compared to the previously proposed ASIF for a group of 2-5 circuits. It also achieves 34-53% area saving as compared to a traditional FPGA.

关键词： Application specific FPGA reconfigurable ASIC NPN SRAM-Table sharing field programmable gate array reconfiguration overheads

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A Disturbance Suppression Zeroing Neural Network for Robust Synchronization of Chaotic Systems and Its FPGA Implementation

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INTERNATIONAL JOURNAL OF BIFURCATION AND CHAOS 2022年第14期32卷 2250210-2250210页

作者： Chen, Weijie Jin, Jie Chen, Chaoyang Yu, Fei Wang, Chunhua Hunan Univ Sci & Technol Sch Informat & Elect Engn Xiangtan 411201 Peoples R China Changsha Univ Sci & Technol Sch Comp & Commun Engn Changsha 410114 Peoples R China Hunan Univ Sch Comp Sci & Elect Engn Changsha 410082 Peoples R China

The synchronization of chaotic systems plays an extremely imperative and fundamental role in the fields of science and engineering. Notably, various external noise disturbances have a great impact on the synchronization of chaotic systems because chaotic systems are quite sensitive to the change of their initial values. Consequently, the robustness of chaotic system synchronization must be considered in practical applications. From this viewpoint, the present paper proposes a disturbance suppression zeroing neural network (DSZNN) for robust synchronization of chaotic and hyperchaotic systems, and the DSZNN is implemented on field programmable gate array (FPGA) for further hardware validation. The distinctive features of the proposed DSZNN controller have the ability to suppress disturbance with faster convergent speed and higher accuracy compared with super-exponential zeroing neural network (SEZNN) and conventional zeroing neural network (CZNN). Moreover, theoretical analysis, comparative numerical simulations and hardware validations for the synchronization of a hyperchaotic system are presented to demonstrate the superior performance of the proposed DSZNN.

关键词： Zeroing neural network chaotic system synchronization field programmable gate array noise disturbances

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Microelectronic Implementations of Fractional-Order Integrodifferential Operators

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JOURNAL OF COMPUTATIONAL AND NONLINEAR DYNAMICS 2008年第2期3卷 21301-21301页

作者： Santamaria, Guillermo E. Valverde, Jose V. Perez-Aloe, Raquel Vinagre, Bias M. Univ Extremadura Sch Ind Engn E-06071 Badajoz Spain

For practical applications, the fractional-order integral and differential operators require to be approximated as stable, causal, minimum-phase integer-order systems, which usually leads, in both continuous and discrete domains, to high order transfer functions. Assuming that art approximation of good quality is available for the fractional operator, efficient implementations, in both cost and speed, are required. The fast development of the microelectronics gives us the opportunity of using cheap, accurate, programmable, and fast devices for implementing reconfigurable analog and digital circuits. Among these devices, field programmable gate arrays, switched capacitor circuits, and field programmable analog arrays are used in this paper for the implementation of a fractional-order integrator, previously approximated by recursive Oustaloups method. The fundamentals of the devices as well as the design procedures are given, and the implementations are compared considering their simulated frequency responses, the design efforts, and other important issues.

关键词： fractional order operator field programmable gate array field programmable analog array switched capacitor active filter

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A 6.6 ps RMS resolution time-to-digital converter using interleaved sampling method in a 28 nm FPGA

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REVIEW OF SCIENTIFIC INSTRUMENTS 2019年第4期90卷 044706-044706页

作者： Xia, Haojie Cao, Guiping Dong, Ning Hefei Univ Technol Sch Instrument Sci & Optoelect Engn Hefei 230009 Anhui Peoples R China Hefei I Tek OptoElect Co Ltd China Res Ctr High Speed Machine Vis Hefei 230088 Anhui Peoples R China

Based on the adaptive logic module structure implemented in a 28 nm field programmable gate array (FPGA), we propose an interleaved sampling method, together with bin realignment operation, to enable time-to-digital converter (TDC) implementation. The tap status is sampled twice in a single physical channel, meaning that TDC precision beyond the cell delay limit can be anticipated. Two TDC channels were implemented in a 28 nm Cyclone-V FPGA, and the effectiveness of the proposed method was evaluated. After calibration, the TDC produced a timing resolution of 6.6 ps root mean square or 5.8 ps per least significant bit. Published under license by AIP Publishing.

关键词： Digital circuits Interpolation Time-to-digital converter field programmable gate array Delay lines Electronic circuits

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Undeviating Adaptive Sheltered Cryptography (UASC) method based low power and high secure cache memory design

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MICROPROCESSORS AND MICROSYSTEMS 2019年 71卷 102876-000页

作者： Sai, R. Vijay Upadhyay, Har Narayan Prabhu, M. Saravanan, S. SASTRA Deemed Univ Sch Comp Thanjavur Tamil Nadu India SASTRA Deemed Univ Sch Elect & Elect Engn Thanjavur Tamil Nadu India

The prerequisite of data security on network has turned out to be more important. Cryptography is a technique to give data privacy, acceptability and integrity. There are such significant number of difficulties to realize cryptography algorithm, for example, execution time, memory requirement, and intention control. In this work, a high secure and low power use of cache memory is implemented for utilizing a new cryptography method specifically named as Undeviating Adaptive Sheltered Cryptography (UASC) algorithm. The outline of the proposed memory has been altered by the expansion of all validation supervisors required by the equipment usage of Advanced Encryption Standard (AES). In addition, UASC has been incorporated into real time application to permit a self-encryption based on full self-rule. Therefore, compared with the conventional design comprising of a crypto-block and an isolated memory, this new method will prompt an imperative decrease of data interactions among the encryption procedure. The proposed work is depicted utilizing Verilog language, synthesized and actualized utilizing Xilinx ISE suite based field programmable gate array (FPGA) devices. Synthesis results demonstrate that the proposed configuration accomplishes higher efficiency than the previous executions by decreasing area while keeping up a moderate throughput/Look UpTable (LUT) ratio. The proposed configuration is additionally more productive as far as power utilization is concerned. As compared with conventional method, the proposed Undeviating Adaptive Sheltered Cryptography achieves low power consumption for 23.02 mu w and execution time is 9.5 s. (C) 2019 Elsevier B.V. All rights reserved.

关键词： Cache memory Encryption Decryption Undeviating Adaptive Sheltered Cryptography field programmable gate array

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Enhanced Technology Mapping for FPGAs with Exploration of Cell Configurations

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2015年第3期24卷 1550039-1550039页

作者： Zgheib, Grace Ouaiss, Iyad Lebanese Amer Univ Dept Elect & Comp Engn Byblos Lebanon

In the state-of-the-art field-programmable gate arrays (FPGAs), logic circuits are synthesized and mapped on clusters of look-up tables. However, arithmetic operations benefit from an existing dedicated adder along with a carry chain used to ensure a fast carry propagation. This carry chain is a dedicated wire available in the architecture of the FPGA and is as such independent of the external programmable routing resources. In this paper, we propose a variable-structure Boolean matching technology mapper with embedded decomposition techniques to map nonarithmetic logic functions on carry chains. Previously synthesized and mapped logic functions are adapted so that their outputs are routed using the dedicated carry chains instead of the external programmable interconnects. The experimental results show a reduction in the used routing resources as well as the circuit area when using this Boolean matching-based mapper on the Altera Stratix-III FPGA.

关键词： field programmable gate array technology mapping Boolean matching decomposition carry chain cell configuration

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FPGA-Based Cost-Effective and Resource Optimized Solution of Predictive Direct Current Control for Power Converters

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ENERGIES 2021年第22期14卷 7669页

作者： Sankar, Deepa Syamala, Lakshmi Ayyappan, Babu Chembathu Kallarackal, Mathew Cochin Univ Sci & Technol Div Elect Engn Ernakulam 682022 India Mar Athanasius Coll Engn Dept Elect & Commun Engn Kothamangalam 686666 India

Recent advances in power converter applications with highly demanding control goals require the efficient implementation of superior control strategies. However, the real-time application of such control strategies demands high computational power that necessitates efficient digital controllers like field programmable gate array (FPGA). The inherent parallelism offered by FPGAs minimizes the execution time and exhibits an excellent cost-performance trade-off. In addition, rapid advancements in FPGA technology with a broad portfolio of intellectual property (IP) cores, design tools, and robust embedded processors resulted in a design paradigm shift. This article proposes a low-cost solution for the resource-optimized implementation of dynamic, highly accurate, and computationally intensive finite state-predictive direct current control (FS-PDCC). The challenges for implementing complex control algorithms for power converters are discussed in detail, and the control is implemented in Intel's low-cost non-volatile FPGA-MAX (R) 10. An efficient design methodology using finite state machine (FSM) is adopted to achieve time/resource-efficient implementation. The parallel and pipelined architecture of FPGA provides better resource utilization with high execution speed. The experimental results prove the efficiency of FPGA-based cost-effective solutions that offer superior performance with better output quality.

关键词： field programmable gate array intellectual property core finite control set model predictive control finite state machine resource optimization voltage source inverter analog to digital converter

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A notion of r -admissibility and its application in logic synthesis

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IFAC Proceedings Volumes 2009年第21期42卷 172-177页

作者： Grzegorz Borowik Tadeusz Łuba Paweł Tomaszewicz Institute of Telecommunications Warsaw University of Technology Warsaw Poland

This paper presents a theory for disjoint and non-disjoint multi-output Boolean function decomposition. This method is dedicated for FPGAs with embedded memory blocks (EMB). Proposed technique is an extension of known approach commonly used for LUT-based FPGA structures. A scheme for generating the set of bound variables that make the function decomposable is presented. Experiments that were carried out show significant area reduction.

关键词： Boolean logic Logic synthesis Decomposition field programmable gate array Logic cell Embedded memory block

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A FPGA-Based Bit-Word PLC CPUs Development Platform

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IFAC Proceedings Volumes 2010年第24期43卷 132-137页

作者： Miroslaw Chmiel Jan Mocha Edward Hrynkiewicz University of Technology Institute of Electronics Gliwice Poland

The conception of the hardware-software platform is presented in the paper. Presented platform is designed in order to test different constructions of the central processing units dedicated to programmable logic controllers. Selected hardware solutions for the PLC dual processor bit-byte (word) CPUs, which are oriented for optimised maximum utilization of capabilities of the two-processor architecture of the CPU are presented in the paper. The key point is preserving high speed of instruction processing by the bit-processor, and high speed and functionality of the byte (word)-processor. The structure should enable the processors to work in concurrent mode as far as it is possible, and minimize the situations, when one processor has to wait for the other. Designed platform is based on the development board equipped with Xilinx Virtex-4 FPGA. Software tool for testing possibilities of the selected units and testing utilization of the programmable structure was also developed.

关键词： programmable Logic Controller Central Processing Unit Bit-Byte (Word) Structure of CPU Scan Time Throughput Time Concurrent Operation field programmable gate array

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