检索结果-内蒙古大学图书馆

Design and implementation of the MMC simulation system in the heterogeneous FPGA-CPU platform

JOURNAL OF ENGINEERING-JOE 2019年第16期2019卷 1721-1725页

作者： Li, Xiongfei Mu, Qing Zhang, Xing Xiang, Yinxing Li, Qiao He, Guanghui Shanghai Jiao Tong Univ Sch Elect Informat & Elect Engn Shanghai Peoples R China China Elect Power Res Inst 15 Xiaoyingdonglu Beijing Peoples R China Fujian Elect Power Res Inst Fuzhou Fujian Peoples R China

Real-time simulation of a modular multilevel converter (MMC) plays an important role on the area of large-scale power electronics research. The authors propose a real-time MMC simulation system in a heterogeneous computing platform containing the central processing unit (CPU) and field programmable gate array (FPGA). This system decouples the MMC circuits from the grid based on the alternative circuit equivalent model of the MMC bridge arm. Furthermore, the parallel calculation of the equivalent circuits is achieved when the peripheral circuit is realised on the CPU and the MMC arms are realised on FPGA. In addition, a timing optimisation strategy is discussed to reach the timing target requirement. To validate the MMC simulation system, a case study of a grid with 12 MMC bridges and 640 sub-modules per bridge at 2s time step on Xilinx Virtex-7 XC7VX690T FPGA is simulated in real time. The real-time simulation results demonstrate high accuracy of the simulation system in comparison to the offline simulation of the original system in the electromagnetic transient program and our design is competitive to recent published works.

关键词： field programmable gate arrays voltage-source convertors microprocessor chips equivalent circuits circuit optimisation offline simulation heterogeneous FPGA-CPU platform modular multilevel converter large-scale power electronics research real-time MMC simulation system heterogeneous computing platform field programmable gate array MMC circuits alternative circuit equivalent model MMC bridge arm peripheral circuit timing optimisation strategy timing target requirement central processing unit Xilinx Virtex-7 XC7VX690T FPGA electromagnetic transient program time 2 0 mus

来源：评论

学校读者我要写书评

暂无评论

Design, FEM analysis and development of switched reluctance motor electric drive for TRI-wheeler E-vehicle application

引用

AUTOMATIKA 2024年第3期65卷 813-829页

作者： Anand, M. Jebarani Evangeline, S. Deva Priya, W. Chitra Selvi, S. PSG Coll Technol Dept Elect & Elect Engn Coimbatore India SNS Coll Engn Dept Elect & Elect Engn Coimbatore India Saveetha Univ Saveetha Inst Med & Tech Sci SIMATS Univ Saveetha Sch Engn Dept Comp Sci & Engn Chennai India Anna Univ Chennai Univ Coll Engn Dindigul Constituent Coll Dept Elect & Elect Engn Dindigul India PSG Coll Technol Dept Elect & Elect Engn Coimbatore Tamilnadu India

Electric vehicles have seen substantial growth in recent years in the emerging economies of the world. The current market scenario of E-vehicles is dominated by PMSM or BLDC motors due to their higher torque-to-power density, and efficiency with added performance metrics of the motor. However, the higher capital cost of permanent magnets makes the motor designers to consider an alternative to magnetic motors, the so-called Switched Reluctance Motors (SRM). With proper FEM analysis and controller design, if SRMs can able to achieve the performance metrics of a PMSM/BLDC, it will be a breakthrough in the automotive sector with affordable prices. Based on the aforementioned facts, this research work focuses on SRM as a viable alternative to the existing PMSM/BLDC motor. The work concentrates on the design and development of an 8/6 SRM for a Tri-wheeler E-vehicle application. The designed motor is fabricated, tested and controlled by WAVECT, an FPGA-based real-time digital controller which is used to control the commutation of the 8/6 SRM. The yielded response satisfactorily proves that the designed 8/6 SRM can be effectively used for the Tri-wheeler E-vehicle application, thereby paving the way for sustainable energy conservation in the automotive sector.

关键词： Electric vehicle switched reluctance motor permanent magnet synchronous motor brushless direct current motor WAVECT field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Hardware Implementation of a Robust Adaptive Filter: Two Approaches based in High-Level Synthesis Design Tools

引用

IFAC Proceedings Volumes 2009年第21期42卷 190-194页

作者： M. Bataller-Mompean A. Rosado-Muñoz E. Soria-Olivas J. Guerrero-Martínez J. Vila-Francés Electronic Engineering Department University of Valencia Valencia Spain

Adaptive filters are used in a wide range of applications. Impulsive noise affects the proper operation of the filter and the adaptation process. This noise is one of the most damaging types of signal distortion, not always considered when implementing algorithms. field programmable gate array (FPGA) are widely used for applications where timing requirements are strict. Nowadays, two main design processes can be followed, namely, Hardware Description Language (HDL) and a High Level Synthesis (HLS) design tool for embedded system design. This paper describes the FPGA implementation of an adaptive filter robust to impulsive noise using two approaches based in HLS and the implementation has been carried out on the Xilinx ISE development system for FPGA prototyping. In order to test the system for functionality and implementation results, a widely used standard system identification problem is implemented. Results are provided in order to test accuracy, performance and logic occupation.

关键词： Adaptive Systems Impulsive Noise field programmable gate array High Level Synthesis System Generator

来源：评论

学校读者我要写书评

暂无评论

A design method of digital deconvolution filter for on-line compensation of system dynamic characteristic

A design method of digital deconvolution filter for on-line ...

引用

IEEE International Instrumentation and Measurement Technology Conference (I2MTC) - Discovering New Horizons in Instrumentation and Measurement

作者： Zhao Chenyang Zhang Zhijie North Univ China Sch Instrument & Elect Taiyuan 030051 Shanxi Peoples R China North Univ China Key Lab Instrumentat Sci & Dynam Measurement Minist Educ Taiyuan 030051 Shanxi Peoples R China North Univ China Automat Test Equipment & Syst Engn Res Ctr Shanxi Taiyuan Shanxi Peoples R China

ISBN: (纸本)9781538622223

The traditional digital deconvolution filter which is influenced by its structure has some problems in online compensation of the test system, such as instability, slow speed, and low precision. So we design a digital BR deconvolution filter which can be realized on field programmable gate array to compensate the dynamic characteristics of the test system quickly and use the cascaded structures which is easy to realize zeros and poles to design 4-stage cascaded differential compensation module which is assigned for the zero-pole. The Xilinx Spartan 6 platform is used to verify the stability and real-time performance of the module whose parameters are quantified, through dynamic calibration experiment to analyze dynamic compensation effect of Endevco 8530c pressure sensor and its test system of dynamic compensation effect on the time and frequency domain characteristics. Compare the result of compensation by direct type I structure, this kind of digital filter design method has the advantages of small quantitative impact, fast calculation speed, and configurable parameters, to some extent make up for the defect of the online compensation system characteristics.

关键词： digital deconvolution filter dynamic compensation cascaded IIR pole-zero assignment field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Simulation of Bi-directional DC-DC Converter Using FPGA

引用

Procedia Computer Science 2016年 79卷 708-714页

作者： P. Karthigeyan M Senthil Raja T Siva Kumar S.R Sivaa Ganesh J. Lavanya Research Scientist I.I.T Madraschennai-600036 India Assistant Professor VI Institute of technology chennai-603108 India UG scholar KS Rangaswamy college of arts and sciencechennai-600119 UG scholar Sathyabama Universitychennai-600119

The basic idea of proposed system is to utilize the renewable resources by digital PWM control of Bi-directional DC – DC converter. Usually PWM pulse is being generated through a digital system such as microcontroller or Digital signal controller. In stand – alone application these controllers increases the cost but XILINX FPGA based PWM generation reduces the cost. XILINX FPGA is programmable device developed by XILINX which is being considered as an efficient device for rapid prototyping and also to perform concurrent operations. In this paper two PWM signals was generated to control the switch duty cycles in Bi-directional DC-DC Converter. In addition to that different modes of operation of the proposed circuit are verified by MATLAB / SIMULINK.

关键词： Bi-directional dc-dc converter pulse width modulation field programmable gate array XILINX duty cycle.

来源：评论

学校读者我要写书评

暂无评论

The Research and Implementation of Sobel Calculatory based on FPGA

World Scientific Research Journal

引用

World Scientific Research Journal 2021年第4期7卷 444-447页

作者： Xi Gao Liyan Zhang

The edge of the image carries a lot of important image information. When extracting the edge of the image, it can effectively reduce the amount of data while retaining most of the graphic information. And edge recognition is also the basic technology of image processing and machine vision, especially in the field of image feature extraction. The Sobel operator is an important processing method in the field of image processing, which is mainly used to obtain a degree of digital image. This article uses the dual-core ARM Cortex-A9 processor embedded in the ZYNQ platform to perfectly combine the software programmability with the hardware programmability of the FPGA, uses HLS to achieve Sobel detection, and introduces a new VDMA operation method. The image is displayed in the memory mode, and the system advantages of low power consumption and low cost realize the unparalleled system performance, flexibility, and scalability of a single chip, and accelerate the time to market of graphics processing products.

关键词： Sobel operator field programmable gate array HLS

来源：评论

学校读者我要写书评

暂无评论

Dynamic partial reconfiguration scheme for fault-tolerant FFT processor based on FPGA

引用

JOURNAL OF ENGINEERING-JOE 2019年第21期2019卷 7424-7427页

作者： Wei, Xin Xie, Yi Z. Xie, Yu Chen, He Beijing Inst Technol Beijing Key Lab Embedded Real Time Informat Proc Beijing 100081 Peoples R China

The fast Fourier transform FFT processor is an important part of the space real-time signal processing system based on field programmable gate array (FPGA). Since occupying a large amount of logical resources and storage resources, FFT processor is more vulnerable to high-energy particles in space, resulting in single event upset (SEU). This paper presents a novel FPGA scrubbing framework base on dynamic partial reconfiguration technique for a FFT processor to mitigate SEU. The proposed scheme is compared with the blind scrubbing, the reconfiguration time is reduced by 78%. Then, the resource utilisation is 61.5% less than triple modular redundancy scheme. This paper also presents a DPR controller for FFT processor, which is evaluated in terms of hardware resources and reconfiguration time. A comparison to the Xilinx PRC IP shows that multipath delay feedback FFT controller saves 38.6% resources.

关键词： field programmable gate arrays fault tolerant computing fast Fourier transforms redundancy radiation hardening (electronics) microprocessor chips reconfiguration time multipath delay feedback FFT controller dynamic partial reconfiguration scheme fault-tolerant FFT processor field programmable gate array logical resources storage resources dynamic partial reconfiguration technique fast Fourier transform FFT processor novel FPGA scrubbing framework high-energy particles triple modular redundancy scheme DPR controller blind scrubbing Xilinx PRC IP single event upset

来源：评论

学校读者我要写书评

暂无评论

A Stochastic Computing Method For Generating Activation Functions in Multilayer Feedforward Neural Networks

ELECTRICA

引用

ELECTRICA 2021年第3期21卷 376-+页

作者： Ersoy, Durmus Erkmen, Burcu Istanbul Esenyurt Univ Dept Elect & Elect Engn Istanbul Turkey Yildiz Tech Univ Dept Elect & Commun Engn Istanbul Turkey

Stochastic computing using basic arithmetic logic elements based on stochastic bit sequences provides very beneficial solutions in terms of speed and hardware cost, relative to deterministic calculation. Studies for the realization of tangent hyperbolic and exponential functions used in the development of activation functions in Artificial Neural Networks by stochastic methods exist in the literature. The techniques presented using state transitions on finite state machines were constructed on the basis of two different forms of finite state machines, one-dimensional (Linear) and two-dimensional. In this analysis, in terms of both error rate and circuit cost, the advantageous two-dimensional finite state machines based stochastic computing approach for tangent hyperbolic and exponential functions is presented. The presented approach is implemented on field programmable gate array and the results are given for hardware simulation. The dataset used for the classification process in a decentralized smart grid control has been applied to the multilayer feedforward neural network and deterministic computing, for the stability classification which is carried out separately with the linear finite state machines based stochastic computing and the proposed 2D finite state machines based stochastic computing methods.

关键词： field programmable gate array finite state machine multilayer feedforward neural networks stochastic activation function stochastic computing

来源：评论

学校读者我要写书评

暂无评论

Implementation of Shunt Active Filter for Harmonic Compensation in a 3 Phase 3 Wire Distribution Network

引用

Energy Procedia 2017年 117卷 172-179页

作者： V.K. Arun Shankar N. Senthil Kumar Research Scholar School of Electrical Engineering VIT University Vellore 632014 India Associate Professor School of Electrical Engineering VIT University Chennai Campus India

This paper explores the modeling of a Proportional Integral (PI) and fuzzy logic controller (FLC) based, shunt active power filter (SAPF) for a three wire network to compensate current harmonics fed to a nonlinear load. In the fuzzy logic controlled SAPF mathematical model of the system is not required since it is based on an inference system incorporating intelligence derived through human expertise. The PI controlled and fuzzy logic based (SAPF) have been developed using the Simulink tool box of MATLAB. Simulation results illustrate that the fuzzy logic based active filter outperforms the PI based shunt active filter. To validate the simulation results a hardware setup is developed making using of the instantaneous Id-Iq theory using for a three phase three wire system. The hardware results were found to match closely with simulation outputs.

关键词： Shunt active filter PQ Theory dq Theory field programmable gate array Total harmonic distortion(THD)

来源：评论

学校读者我要写书评

暂无评论

IRIS: An embedded secure boot for IoT devices

引用

INTERNET OF THINGS 2023年 23卷

作者： Cano-Quiveu, G. Ruiz-de-Clavijo-Vazquez, P. Bellido, M. J. Juan-Chico, J. Viejo-Cortes, J. Univ Seville Dept Tecnol Elect Av Reina Mercedes S-N Sevilla Andalucia 41012 Spain

This study proposes a hardware secure boot solution, an instant retrieval information system (IRIS) that is suitable for integrating Internet of Things (IoT) devices. IRIS can boot a Linux kernel image pre-stores in removable media and comprises a data verifier securing the authenticity, integrity, and confidentiality of the boot process. IRIS is fully developed as a hardware module and the results reveal short boot-up times and a small hardware footprint when implemented on field programmable gate array chips. In addition, IRIS is an open-source generic solution that can be adapted to multiple architectures and includes a crypto-core called E-LUKS that can be used outside the boot-loading process to add confidentiality, integrity, and authenticity to data stored on off-chip storage like a flash *** shows a reduction in lookup tables footprint when compared to other IoT solutions consuming from 90% to 750% less resources and only slightly greater, around 30%, with solutions that only cover authentication and integrity.

关键词： field programmable gate array Secure boot Internet of Things (IoT) Bootloader Hardware Embedded device

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：