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FPGA-Based Implementation of Stochastic Configuration Networks for Regression Prediction

SENSORS 2020年第15期20卷 4191.-4191页

作者： Gao, Yunqi Luan, Feng Pan, Jiaqi Li, Xu He, Yaodong Northeastern Univ Sch Comp Sci & Engn Shenyang 110819 Peoples R China Northeastern Univ Key Lab Intelligent Comp Med Image Minist Educ Shenyang 110819 Peoples R China Northeastern Univ State Key Lab Rolling & Automat Shenyang 110819 Peoples R China

The implementation of neural network regression prediction based on digital circuits is one of the challenging problems in the field of machine learning and cognitive recognition, and it is also an effective way to relieve the pressure of the Internet in the era of intelligence. As a nonlinear network, the stochastic configuration network (SCN) is considered to be an effective method for regression prediction due to its good performance in learning and generalization. Therefore, in this paper, we adapt the SCN to regression analysis, and design and verify the field programmable gate array (FPGA) framework to implement SCN model for the first time. In addition, in order to improve the performance of the SCN model based on the FPGA, the implementation of the nonlinear activation function on the FPGA is optimized, which effectively improves the prediction accuracy while considering the utilization rate of hardware resources. Experimental results based on the simulation data set and the real data set prove that the proposed FPGA framework successfully implements the SCN regression prediction model, and the improved SCN model has higher accuracy and a more stable performance. Compared with the extreme learning machine (ELM), the prediction performance of the proposed SCN implementation model based on the FPGA for the simulation data set and the real data set is improved by 56.37% and 17.35%, respectively.

关键词： field programmable gate array hardware neural networks regression prediction stochastic configuration networks

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A Modular and programmable Development Platform for Capsule Endoscopy System

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JOURNAL OF MEDICAL SYSTEMS 2014年第6期38卷 1-12页

作者： Khan, Tareq Hasan Shrestha, Ravi Wahid, Khan A. Univ Saskatchewan Dept Elect & Comp Engn Saskatoon SK S7N5A9 Canada

The state-of-the-art capsule endoscopy (CE) technology offers painless examination for the patients and the ability to examine the interior of the gastrointestinal tract by a noninvasive procedure for the gastroenterologists. In this work, a modular and flexible CE development system platform consisting of a miniature field programmable gate array (FPGA) based electronic capsule, a microcontroller based portable data recorder unit and computer software is designed and developed. Due to the flexible and reprogrammable nature of the system, various image processing and compression algorithms can be tested in the design without requiring any hardware change. The designed capsule prototype supports various imaging modes including white light imaging (WLI) and narrow band imaging (NBI), and communicates with the data recorder in full duplex fashion, which enables configuring the image size and imaging mode in real time during examination. A low complexity image compressor based on a novel color-space is implemented inside the capsule to reduce the amount of RF transmission data. The data recorder contains graphical LCD for real time image viewing and SD cards for storing image data. Data can be uploaded to a computer or Smartphone by SD card, USB interface or by wireless Bluetooth link. Computer software is developed that decompresses and reconstructs images. The fabricated capsule PCBs have a diameter of 16 mm. An ex-vivo animal testing has also been conducted to validate the results.

关键词： Endoscopy field programmable gate array Finite sate machine Compressor Ex-vivo testing

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A Fault Tolerant Design Methodology for a FPGA-based Softcore Processor

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IFAC Proceedings Volumes 2012年第4期45卷 145-150页

作者： P. Garcia T. Gomes F. Salgado J. Cabral P. Cardoso M. Ekpanyapong A. Tavares Centro Algoritmi – University of Minho Portugal Asian Institute of Technology Thailand

The susceptibility of digital systems to faults requires the implementation of Fault Tolerant architectures to ensure high-reliability and availability. field programmable gate arrays are especially sensitive to Single-Event Upsets and Single-Event Transients, since the configuration memory of the chip can be affected, resulting in permanent error; thus, special care must be taken when implementing Fault Tolerant architectures for FPGAs. This paper describes the architecture of a Fault Tolerant softcore processor using triplication of all units as well as using a parity protection scheme for on-chip caches, presenting the impact on area, clock frequency and I/O requirements of both implementations, targeting FPGAs. Experiments show a high fault tolerance and demonstrate the relationship of cache hit rates with fault propagation.

关键词： Fault Tolerance field programmable gate array Microprocessor Dynamic Reconfiguration

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A HW/SW Co-Verification Technique for FPGA Test

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Journal of Electronic Science and Technology of China 2009年第4期7卷 390-394页

作者： Yong-Bo Liao Ping Li Ai-Wu Ruan Yi-Wen Wang Wen-Chang Li Key Laboratory of Electronic Thin Fills and Integrated Devices University of Electronic Science ＆ Technology of China Chengdu 610054 China

field programmable gate arrays （FPGAs） have wide and extensive applications in many areas. Due to programmable feature of FPGAs, faults of FPGAs can be easily tolerated if fault sites can be located. A hardware/software （HW/SW） co-verification technique for FPGA test is proposed in this paper. Taking advantage of flexibility and observability of software in conjunction with high-speed simulation of hardware, this technique is capable of testing each input/output block （IOB） and configurable logic block （CLB） of FPGA automatically, exhaustively and repeatedly. Fault cells of FPGA can be positioned automatically by the proposed approach. As a result, test efficiency and reliability can be enhanced without manual work.

关键词： Configurable logic block field programmable gate array hardware/software co-verification input/output block.

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Investigating hardware acceleration for simulation of CFD quantum circuits

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FRONTIERS IN MECHANICAL ENGINEERING-SWITZERLAND 2022年 8卷

作者： Moawad, Youssef Vanderbauwhede, Wim Steijl, Rene Univ Glasgow Glasgow Scotland

Among the many computational models for quantum computing, the Quantum Circuit Model is the most well-known and used model for interacting with current quantum hardware. The practical implementation of quantum computers is a very active research field. Despite this progress, access to physical quantum computers remains relatively limited. Furthermore, the existing machines are susceptible to random errors due to quantum decoherence, as well as being limited in number of qubits, connectivity and built-in error correction. Simulation on classical hardware is therefore essential to allow quantum algorithm researchers to test and validate new algorithms in a simulated-error environment. Computing systems are becoming increasingly heterogeneous, using a variety of hardware accelerators to speed up computational tasks. One such type of accelerators, field programmable gate arrays (FPGAs), are reconfigurable circuits that can be programmed using standardized high-level programming models such as OpenCL and SYCL. FPGAs allow to create specialized highly-parallel circuits capable of mimicking the quantum parallelism properties of quantum gates, in particular for the class of quantum algorithms where many different computations can be performed concurrently or as part of a deep pipeline. They also benefit from very high internal memory bandwidth. This paper focuses on the analysis of quantum algorithms for applications in computational fluid dynamics. In this work we introduce novel quantum-circuit implementations of model lattice-based formulations for fluid dynamics, specifically the D1Q3 model using quantum computational basis encoding, as well as, efficient simulation of the circuits using FPGAs. This work forms a step toward quantum circuit formulation of the Lattice Boltzmann Method (LBM). For the quantum circuits implementing the nonlinear equilibrium distribution function in the D1Q3 lattice model, it is shown how circuit transformations can be introduced that facilit

关键词： quantum circuit simulation Lattice Boltzmann Method (LBM) FPGA field programmable gate array quantum circuit transformation hardware acceleration

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Design and Implementation of Hardware Search Algorithm Based on FPGA

Frontiers in Economics and Management

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Frontiers in Economics and Management 2021年第5期2卷 317-320页

作者： Xi Gao Liyan Zhang

In the design of the switch, the search algorithm is one of the most critical core modules. There are many traditional table entry search methods, mainly: linear search method, binary tree search method, hash table search, etc. These search methods are software search methods based on SRAM, and the common feature is slow search speed. The linear lookup table method needs to traverse all entries in the table; the binary tree search method needs to traverse most nodes in the tree, and the search speed is greatly affected by the depth of the tree; the hash table search method is relatively fast, but with the network speed requirement As it gets higher and higher, hash search still cannot meet the demand for extremely fast search. This text designs and realizes a kind of hardware search algorithm, utilizes the characteristic of FPGA to process the data in parallel, speed up the data search ability greatly, further shorten the switch forwarding delay.

关键词： field programmable gate array Media Access Control Address TCAM

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Development of a reconfigurable platform for manufacturing equipment control

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Wuhan Ligong Daxue Xuebao/Journal of Wuhan University of Technology 2006年第SUPPL. 1期28卷 810-814页

作者： Feng, Shouting Li, Di Cheng, Xiangyu College of Mechanical Engineering South China University of Technology Guangzhou 510640 China

In modern manufacturing equipment control area , controller is required to deliver higher computing capability for adopting advanced algorithms to meet speed and accuracy requirements, and reconfigurabilities for changing or (and) adding features or functions. This paper presents a methodology in design and implementation of a high performance and reconfigurable platform for manufacturing equipment control. This methodology is in virtue of system on a programmable chip (SoPC) technology but replacing the on-chip processor by an external high performance, floating-point digital signal processor (DSP). The application of the DSP is designed as a multi-threaded framework, which has more flexibilities than a traditional single-loop one. Furthermore, the field programmable gate array (FPGA) system can be reconfigured easily and quickly to meet a new requirement by dragging and dropping pre-built components in a SoPC building environment. As a result, the controller platform is more reconfigurable in terms of algorithms and functions. This platform is implemented in a 3-axis milling machine control and the result indicates that the design and implementation presented in this paper is feasible.

关键词： Digital signal processor field programmable gate array Machine tool control System on a programmable chip

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To retrieve biomedical signals in single channel by FPGA-WeICA platform

影像处理暨通讯期刊

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影像处理暨通讯期刊 2021年第1期13卷 1-5页

作者： Ming-Yen Chen Chung-Young Chen Wei-Lung Geng

Wearable devices were becoming more popular nowadays. Thus, multi-channel measurement of physiological signals had become an inevitable trend. As for traditional technology, time division multiplexing (TDM) cannot achieve real-time measurement using time slots, while frequency division multiplexing (FDM) required additional high-cost hardware and software to in cooperate, since utilized the fundamental frequency signal and the carrier to modulate onto different central frequencies. This research will develop an identification platform to transmit multiple physiological signals on a single channel. A low cost and high retrieval in biomedical signals platform consisted of two parts, one was field programmable gate array (FPGA) as the core processor, and another was wavelet enhanced independent component analysis (WeICA) as a post-signal processing unit. Its advantages can not only remove noise and improve the signal-to-noise ratio (SNR), but also improve noise immunity and reduce costs. For the purpose to evaluate platform in flexibility, reproducibility, and stability, we adopted MIT/BIH ECG normal database as source signals. The absolute correlation coefficient between original and estimated groups, which separated by WeICA results, were 98.3%, 97.8%, 99.5% and 96.8% respectively. Again, we real-time recorded 10 healthy volunteers by 4 physiological measurements experiments, i.e., EMG, ECG, blood pressure and EEG. According to the cost function and correlation coefficient estimation, FPGA and WeICA physiological measurement platform had a high decimation in separating signals blindly and achieved similar ＂multiplexing＂ through single USB 3.0 connection.

关键词： field programmable gate array retrieve biomedical signals independent component analysis

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Implementation of access controller for Ethernet passive optical network

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Journal of Shanghai University(English Edition) 2006年第5期10卷 425-430页

作者：邹君妮陈健林如俭 School of Communication and Information Engineering Shanghai University Shanghai 200072 P.R. China

This paper presents the design and implementation of access controller used for Ethernet passive optical network （ EPON）. As a first step to develop an ASIC product, the entire system is designed on a field programmable gate array （FPGA） with an embedded CPU. To reduce working frequency of the FPGA, the byte-to-word conversion is proposed. Propagation delays are equalized by ranging procedure so as to avoid data collision. Implementations of synchronization, classification, as well as Linux porting are illustrated in detail. The interface between the FPGA and CPU are also presented. Experimental results show that the proposed system can properly function in a relatively low cost FPGA.

关键词： Ethernet passive optical network broadband access field programmable gate array embedded system.

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Single-Image Visibility Restoration: A Machine Learning Approach and Its 4K-Capable Hardware Accelerator

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SENSORS 2020年第20期20卷 5795.-5795.页

作者： Ngo, Dat Lee, Seungmin Lee, Gi-Dong Kang, Bongsoon Dong A Univ Dept Elect Engn Busan 49315 South Korea

In recent years, machine vision algorithms have played an influential role as core technologies in several practical applications, such as surveillance, autonomous driving, and object recognition/localization. However, as almost all such algorithms are applicable to clear weather conditions, their performance is severely affected by any atmospheric turbidity. Several image visibility restoration algorithms have been proposed to address this issue, and they have proven to be a highly efficient solution. This paper proposes a novel method to recover clear images from degraded ones. To this end, the proposed algorithm uses a supervised machine learning-based technique to estimate the pixel-wise extinction coefficients of the transmission medium and a novel compensation scheme to rectify the post-dehazing false enlargement of white objects. Also, a corresponding hardware accelerator implemented on a field programmable gate array chip is in order for facilitating real-time processing, a critical requirement of practical camera-based systems. Experimental results on both synthetic and real image datasets verified the proposed method's superiority over existing benchmark approaches. Furthermore, the hardware synthesis results revealed that the accelerator exhibits a processing rate of nearly 271.67 Mpixel/s, enabling it to process 4K videos at 30.7 frames per second in real time.

关键词： haze removal machine learning supervised learning hardware accelerator field programmable gate array

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