Optical community has expressed a wide consensus over the idea that 1 mm poly-methil-meta-acrilate step-index fibres (PMMA SI-POF) can be a good candidate in future domotic networks and in edge networks, that is in th...
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Optical community has expressed a wide consensus over the idea that 1 mm poly-methil-meta-acrilate step-index fibres (PMMA SI-POF) can be a good candidate in future domotic networks and in edge networks, that is in the last part of access networks, due to their better mechanical behaviour and lower installation and handling costs with respect to conventional 50/125 or 62.5/125 multi-mode glass fibres. Current applications are anyway limited by relatively low transmission performances: up to now, the best performing commercial Ethernet transceivers using PMMA SI-POF are able to reach at the most 200 m at 10 Mb/s or 70 m at 100 Mb/s, thereby keeping these fibres in the niche of very-short reach applications, such as in the automotive market. A Prototype of a media converter for fully compliant 10 Mb/s Ethernet transmissions over PMMA SI-POF experimentally demonstrated the feasibility of >400 m long link, this length may open new applications to PMMA SI-POF. The 425-m record distance presented here has been achieved by both introducing a proprietary protocol implemented over a field programmable gate array platform and by a careful selection of (commercial) optoelectronic components. The prototype is to be considered as a proof-of-concept that PMMA SI-POF can be introduced in new areas such as the last part of access/edge networks or datacom applications in industrial automation or aircrafts/ships cabling. The 400-m distance is, for instance, the specification of an Italian fibre to the home operator for the last part of its access network architecture.
Partial dynamic reconfiguration is an emerging area in field programmable gate arrays (FPGA) designs, which is used for saving device area and cost. In order to reduce the reconfiguration overhead, two consecutive sim...
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Partial dynamic reconfiguration is an emerging area in field programmable gate arrays (FPGA) designs, which is used for saving device area and cost. In order to reduce the reconfiguration overhead, two consecutive similar sub-designs should be placed in the same locations to get the maximum reuse of common components. This requires that all the future designs be considered while floorplanning for any given design. A comprehensive framework for floorplanning designs on partial reconfigurable architecture is provided. Several reconfiguration-specific floorplanning cost functions and moves that aim to reduce the reconfiguration overhead are introduced. A new multi-layer sequence pair-representation-based floorplanner that allows overlap of static and nonstatic components of multiple designs and guarantees a feasible overlapping floor-plan with minimal area packing is introduced. A new matching algorithm that covers all possible matchings of static blocks during floorplanning for multiple designs is presented. In our experiments, it is shown that the proposed floorplanner gives more than 50% savings in reconfiguration frames compared with the scheme where no reuse is done. Further, compared with a traditional sequential floorplanner, our floorplanner removes infeasibility in many designs, achieves an improvement of clock period by 12% on average and reduces the place and route time significantly. The proposed floorplanner could be used for finding high-quality floorplans;for applications that use partial reconfiguration.
This paper describes a simulation and development environment for designing mobile three-dimensional (3D) graphics architectures. The proposed simulation and verification environment (SVE) uses glTrace's ability t...
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This paper describes a simulation and development environment for designing mobile three-dimensional (3D) graphics architectures. The proposed simulation and verification environment (SVE) uses glTrace's ability to intercept and redirect an OpenGL vertical bar ES streams. The SVE simulates the behaviour of mobile 3D graphics pipeline during the playback of traces and produces the second geometry trace that can be used as a test vector for the Verilog/hardware discription language RT-level model. An architectural verification can be conducted by comparing the frame-by-frame results. The functionality of the SVE is demonstrated by designing a mobile 3D graphics architecture and implementing the verified architecture on field programmable gate array (FPGA) boards. An application development environment (ADE) is also presented that includes a mobile graphics application programming interface and a device driver interface. The proposed SVE and the ADE could be efficiently used for developing and testing mobile applications, architectural analysis and hardware designs.
This paper presents an FPGA-based architecture for local tone mapping of gray scale high dynamic range images. The architecture is described in VHDL and has been synthesized using Altera Quartus tools. It achieves an ...
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This paper presents an FPGA-based architecture for local tone mapping of gray scale high dynamic range images. The architecture is described in VHDL and has been synthesized using Altera Quartus tools. It achieves an operating frequency consistent with a video rate of 60 frames per second for a frame of 1,024 x 768 pixels. The proposed architecture is a modification of the nine-scale Reinhard operator. Approximations to the original Reinhard operator ensure that the operator is amenable to implementation in hardware. A peak signal-to-noise ratio study shows that our fixed-point hardware approximation produces results similar to a floating-point original.
Numerous application areas, including bioinformatics and computational biology, demand increasing amounts of processing capability. In many cases, the computation cores and data types are suited to field-programmable ...
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Numerous application areas, including bioinformatics and computational biology, demand increasing amounts of processing capability. In many cases, the computation cores and data types are suited to field-programmablegatearrays. The challenge is identifying the design techniques that can extract high performance potential from the FPGA fabric.
A field programmable gate array (FPGA)-based implementation of a physical random number generator (PRNG) is presented. The PRNG uses an alternating step generator construction to decorrelate an oscillator-phase-noise-...
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A field programmable gate array (FPGA)-based implementation of a physical random number generator (PRNG) is presented. The PRNG uses an alternating step generator construction to decorrelate an oscillator-phase-noise-based physical random source. The resulting design can be implemented completely in digital technology, requires no external components, is very small in area, achieves very high throughput and has good statistical proper-ties. The PRNG was implemented on an FPGA device and tested using the NIST, Diehard and TestU01 random number test suites.
A four-input adder structure for the FPGA implementation of a sigma-delta bit-stream multiplier is proposed. Conventional bit-stream multiplier implementations involve two-input adder circuits. It is shown that the fo...
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A four-input adder structure for the FPGA implementation of a sigma-delta bit-stream multiplier is proposed. Conventional bit-stream multiplier implementations involve two-input adder circuits. It is shown that the four-input adder structure is more resource-efficient (over 40% hardware savings) and faster (over 20% higher clock frequency) when implemented using state-of-the-art FPGA architecture featuring six-input look-up tables.
This paper presents the design of a simplified version of fuzzy inference engine (FIE) built on an Altera Flex 10K field programmable gate array (FPGA). This approach uses a modified center of area method. By introduc...
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This paper presents the design of a simplified version of fuzzy inference engine (FIE) built on an Altera Flex 10K field programmable gate array (FPGA). This approach uses a modified center of area method. By introducing some constraints on the defined fuzzy subsets the computational speed of the FIE is made faster. The approach discussed in this paper removes the division bottleneck and keeps the fuzzy look-up tables small, thereby reducing the computational complexity of the FPGA. Parallelism is introduced in accessing the memory, thereby increasing the computational speed. A speed of 2.5 M FLIPS is achieved with a speed grade of 25 MHz.
The DeepSea G2 stereo vision system that Tyzx developed features an embedded stereo camera consisting of two CMOS imagers, a Tyzx DeepSea 2 stereo application-specific integrated circuit (ASIC), a field-programmable g...
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The DeepSea G2 stereo vision system that Tyzx developed features an embedded stereo camera consisting of two CMOS imagers, a Tyzx DeepSea 2 stereo application-specific integrated circuit (ASIC), a field-programmablegatearray (FPGA), a DSP/coprocessor, a PowerPC running Linux, and an Ethernet connection. About the size of a hardback book, the G2 delivers real-time - 30 frames per second (fps) - interpretations of visual data even in challenging environments and has been deployed in a variety of applications, including person-tracking and autonomous-vehicle navigation.
The optical ZCZ code is a set of pairs of binary and bi-phase sequences with zero correlation zone. An optical code division multiple access (CDMA) system using this code can remove co-channel interference and influen...
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ISBN:
(纸本)9781424410736
The optical ZCZ code is a set of pairs of binary and bi-phase sequences with zero correlation zone. An optical code division multiple access (CDMA) system using this code can remove co-channel interference and influence of multi-path. We proposed the compact construction of a bank of matched filters for this code in a receiver. But we have not proposed the construction of a code generator for this code in a transmitter yet. In this paper, we propose the construction of two code generators for an optical ZCZ code using a Sylvester-type Hadamard matrix, which are called ROM-type and non ROM-type code generators. This ROM-type code generator can be constructed by a ROM and a up-counter. Similarly, this non ROM-type code generator can be constructed by a up-counter, flip-flops and logic gates. The ROM-type and non ROM-type code generators are implemented on a field programmable gate array (FPGA) corresponding to 400, 000 logic gates, and the non ROM-type code generator can reduce logic elements than the ROM-type code generator.
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