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Conference on Digital Wireless Communications VII and Space Communication Technologies

作者： Hicks, JE Clark, JS Stocker, J Mitchell, GS Wyckoff, P Aerosp Corp Chantilly VA 20151 USA

ISBN: (纸本)081945804X

The automatic identification system (AIS) signal is of particular interest to the defense and security community because of its capability to identify and classify ships in U.S. waters. Placing an AIS receiver on a satellite provides a low cost solution to enhance security over a wide region. This paper describes the development of an AIS burst-acquisition receiver on a software radio consisting of a field programmable gate array (FPGA) and general purpose processor (GPP). A simple hybrid 1-bit/2-bit differential receiver can be easily implemented on such a software radio platform, and is sufficient to reliably demodulate collision free bursts in a space-borne signal environment.

关键词： AIS automatic identification system differential receiver FPGA field programmable gate array GMSK Gaussian minimum shift keying satellite

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A domain specific reconfigurable Viterbi fabric for system-on-chip applications 05

A domain specific reconfigurable Viterbi fabric for system-o...

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10th Asia and South Pacific Design Automation Conference

作者： Zhan, Cheng Arslan, Tughrul Khawam, Sami Lindsay, Iain Univ Edinburgh Sch Electron & Engn Edinburgh EH9 3JL Midlothian Scotland

ISBN: (纸本)0780387368

A novel embedded dynamically reconfigurable fabric for implementing the Viterbi algorithm in a System-on-Chip device is presented in this paper. The proposed reconfigurable fabric can support Viterbi implementations for different standards, such as GSM, IS-95, CDMA and Wireless LAN. Our results illustrate that the proposed architecture has superior power consumption and throughput characteristics and it is demonstrated a 80% reduction in power consumption over generic field programmable gate array (FPGA) and 40 times improvement in throughput over digital signal processor (DSP), respectively. Thus, the reconfigurable system-on-chip platform based on this kind of domain specific reconfigurable fabrics is an efficient solution for the high-performance portable communication systems.

关键词： reconfigurable architectures system-on-chip digital signal processing chips Viterbi decoding mobile communication wireless LAN code division multiple access reconfigurable fabric Viterbi algorithm system-on-chip device GSM IS-95 CDMA power consumption field programmable gate array digital signal processor communication systems wireless local area network (WLAN) Code division multiple access system-on-chip field programmable gate arrays Power consumption digital signal processing chips Viterbi algorithm COMMUNICATION SYSTEMS Viterbi decoding Reconfigurable architectures mobile communication configurability

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Design methodology for optimal hardware implementation of wavelet transform domain algorithms

Design methodology for optimal hardware implementation of wa...

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Conference on Visual Information Processing XIV

作者： Johnson-Bey, C Mickens, LP Morgan State Univ ARCADE Res Ctr Baltimore MD 21251 USA

ISBN: (纸本)0819458023

The work presented in this paper lays the foundation for the development of an end-to-end system design methodology for implementing wavelet domain image/video processing algorithms in hardware using Xilinx field programmable gate arrays (FPGAs). With the integration of the Xilinx System Generator toolbox, this methodology will allow algorithm developers to design and implement their code using the familiar MATLAB/Simulink development environment. By using this methodology, algorithm developers will not be required to become proficient in the intricacies of hardware design, thus reducing the design cycle and time-to-market.

关键词： wavelet transform domain processing field programmable gate array FPGA Xilinx System Generator

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A novel FPGA implementation of a welding control using a new bus architecture

A novel FPGA implementation of a welding control using a new...

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International Conference on Reconfigurable Computing and FPGAs

作者： Rauma, K Luukko, J Härkönen, T Pajari, I Pyrhönen, O Lappeenranta Univ Technol Lappeenranta 53850 Finland

ISBN: (纸本)0769524567

Development of PLDs (programmable Logic Device) like large FPGA (field programmable Gale array) circuits allow those to be used as modern control platforms for power electronics. Using FPGAs and efficient control algorithms better response times can be gained compared to processor implementations. When using a large FPGA circuit an efficient structure has to be used to get a short lime to market time and to handle the whole software structure. In this paper a switch-mode, welding machine control implementation in FPGA circuit is presented using a new bus structure called OKITO as a base. Also results of fast response times in current control are shown.

关键词： electric current control field programmable gate arrays power electronics programmable logic devices welding FPGA circuits FPGA implementation OKITO PLD bus architecture current control field programmable gate array programmable logic d field programmable gate arrays Power electronics bus architecture Current control electric current control Welding Reaction Time

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Estimating the Dynamic Sensitive Cross Section of an FPGA Design through Fault Injection

Estimating the Dynamic Sensitive Cross Section of an FPGA De...

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作者： Johnson, D. Eric Brigham Young University

学位级别：M.Sc.

A fault injection tool has been created to emulate single event upset (SEU) behavior within the configuration memory of an FPGA. This tool is able to rapidly and accurately determine the dynamic sensitive cross section of the configuration memory for a given FPGA design. This tool enables the reliability of FPGA designs and fault tolerance schemes to be quickly and accurately tested. The validity of testing performed with this fault injection tool has been confirmed through radiation testing. A radiation test was conducted at Crocker Nuclear Laboratory using a proton accelerator in order to determine the actual dynamic sensitive cross section for specific FPGA designs. The results of this radiation testing were then analyzed and compared with similar fault injection tests, with results suggesting that the fault injection tool behavior is indeed accurate and valid. The fault injection tool can be used to determine the sensitivity of an FPGA design to configuration memory upsets. Additionally, fault mitigation techniques designed to increase the reliability of an FPGA design in spite of upsets within the configuration memory, can be thoroughly tested through fault injection. Fault injection testing should help to increase the feasibility of reconfigurable computing in space. FPGAs are well suited to the computational demands of space based signal processing applications; however, without appropriate mitigation or redundancy techniques, FPGAs are unreliable in a radiation environment. Because the fault injection tool has been shown to reliably model the effects of single event upsets within the configuration memory, it can be used to accurately evaluate the effectiveness of fault tolerance techniques in FPGAs.

关键词： FPGA reliability fault injection field programmable gate array SEU Single Event Upset radiation fault tolerance dynamic sensitive cross section sensitivity fault modeling

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TOOLS AND TECHNOLOGIES FOR DESIGNING CONTROL SYSTEMS USING programmable LOGIC DEVICES

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IFAC Proceedings Volumes 2005年第1期38卷 38-43页

作者： Adam MILIK Mariusz DYKIEREK Aldec-ADT Sp. z o.o. Widok 23 40-118 Katowice Poland

The paper presents modern programmable logic devices and design methodologies with appropriate tools reference. It briefly shows enhancements introduced in the architecture of FPGA and its influence on circuit capabilities. The paper presents also the design process from idea to functional implementation. It discusses algorithmic and functional approaches to design. Abstraction level and transaction mechanisms are shown as a method of hiding details without compromising design functionality. Finally tools for different design approaches and design environment requirements are presented.

关键词： programmable Logic Device PLD field programmable gate array FPGA Complex programmable Logic Device CPLD VHDL Verilog ®

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Design and implementation of an RNS-based 2-D DWT processor

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IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2004年第1期50卷 376-385页

作者： Liu, Y Lai, EMK Nanyang Technol Univ Sch Comp Engn Ctr Multimedia & Network Technol Singapore 639798 Singapore

Discrete wavelet transform has been incorporated as part of the JPEG2000 image compression standard and is used in many consumer imaging products. This paper presents a 2-dimensional biorthogonal DWT processor design based on the residue number system. The symmetric extension scheme is employed to reduce distortion at image boundaries. Hardware complexity reduction and utilization improvement are achieved by hardware sharing. Our implementation results show that the design is able to fit into a 1,000,000-gate FPGA device and is able to complete a first level 2-D DWT decomposition of a 32x32-pixel image in 205mus(1).

关键词： discrete wavelet transform residue number system field programmable gate array

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Compact energetic light particle detector and spectrometer

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JOURNAL OF SPACECRAFT AND ROCKETS 2004年第5期41卷 862-867页

作者： Green, BD Galica, GE Nakamura, T Sullivan, JD Abe, T Matsumoto, H Koshiishi, H Goka, T Kimoto, Y Phys Sci Inc Andover MA 01810 USA Phys Sci Inc San Ramon CA 94583 USA Boston Univ Boston MA 02215 USA Mitsubishi Electr Corp Kanagawa 247 Japan Mitsubishi Electr Corp Hyogo 6618661 Japan Natl Space Dev Agcy Japan Ibaraki 305 Japan

We have developed a megaelectron-volt class energetic charged-particle spectrometer based on a novel configuration and processing algorithm. The National Space Development Agency of Japan has undertaken a program to develop a particle monitor capable of discriminating and measuring protons in the range from 0.9 to 150 MeV, electrons in the range from 0.5 to >10 MeV and alpha particles >8 MeV, all within a single sensor called the standard dose monitor. The goal is to utilize sensors with nearly identical design and performance on several simultaneous missions to develop a clearer understanding of particle energies and their variability as a function of solar activity, latitude, and altitude. To date, four flight model sensors have been delivered. The sensors are designed to detect accurately the higher-energy particles and high count rates present during active solar periods. In addition, this sensor exhibits extremely efficient discrimination between low-energy electrons and protons. The sensors have been calibrated over nearly their entire particle-energy range. The design is described and calibration data are compared with the results of a Monte Carlo sensor performance model.

关键词： Spectrometers Photomultiplier Tube National Space Development Agency Solar Activity Geostationary Operational Environmental Satellite Combined Release and Radiation Effects Satellite Japanese Experiment Module field programmable gate array Earth Magnetosphere ISS

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Synthesis and time partitioning for reconfigurable systems

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DESIGN AUTOMATION FOR EMBEDDED SYSTEMS 2004年第3期9卷 177-191页

作者： Ouni, B Mtibaa, A Abid, M Fac Sci Monastir Lab Elect & Microelect Monastir 5000 Tunisia Natl Engn Sch Fax CES ENIS Sfax 3038 Tunisia

This paper aims to introduce a time partitioning algorithm which is an important step during the design process for fully reconfigurable systems. This algorithm is used to solve the time partitioning problem. It divides the input task graph model to an optimal number of partitions and puts each task in the appropriate partition so that the latency of the input task graph is optimal. Also a part of this paper is consecrated for implementation of some examples on a fully reconfigurable architecture following our approach.

关键词： time partitioning synthesis fully reconfigurable systems field programmable gate array design flow framework dynamic algorithm run time reconfiguration

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An evolvable combinational unit for FPGAs

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COMPUTING AND INFORMATICS 2004年第5-6期23卷 461-486页

作者： Sekanina, L Friedl, S Brno Univ Technol Fac Informat Technol Brno 61266 Czech Republic

A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evolutionary algorithm was described in VHDL independently of a target platform, i.e. as a soft IP core, and realized in the COMB06 card. In many cases the unit is able to evolve (i.e. to design) the required function automatically and autonomously, in a few seconds, only on the basis of interactions with an environment. A number of circuits were successfully evolved directly in the FPGA, in particular, 3-bit multipliers, adders, multiplexers and parity encoders. The evolvable unit was also tested in a simulated dynamic environment and used to design various circuits specified by randomly generated truth tables.

关键词： combinational circuit evolutionary design evolvable hardware field programmable gate array

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