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High-performance digital replica of analogue peak current mode control for DC-DC converter

IET POWER ELECTRONICS 2016年第4期9卷 809-816页

作者： Taeed, Fazel Nymand, Morten Univ Southern Denmark Maersk Mc Kinney Moller Inst Fac Engn Odense Denmark

A simple and robust digital peak current mode controller is proposed in this study. The controller replicates an analogue peak current mode control in the discrete domain. The inner current loop has negligible delay, which results in a high controller bandwidth. The controller structure allows the compensation slope to be updated in each switching cycle;therefore, the controller can maintain a high bandwidth over a wide range of operating points. The modelling principles of an analogue peak current mode controller are used to model the proposed controller. For experimental verification, the controller is implemented in a field programmable gate array to control a 100 W buck converter. The measured loop gain of the system correlates very well with the modelling results. The achieved controller crossover frequency is similar to 1/10 of the switching frequency which is close to the crossover frequency of analogue peak current mode controllers.

关键词： DC-DC power convertors electric current control field programmable gate arrays high-performance digital replica analogue peak current mode control DC-DC converter digital peak current mode controller inner current loop buck converter field programmable gate array power 100 W

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FPGA fabric conscious architecture design and automation of speed-area efficient Margolus neighborhood based cellular automata with variegated scan path insertion

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JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 2022年 167卷 50-63页

作者： Palchaudhuri, Ayan Anand, Digvijay Dhar, Anindya Sundar Indian Inst Technol Kharagpur Dept Elect & Elect Commun Engn Kharagpur 721302 West Bengal India

Optimized field programmable gate array (FPGA) implementation of Cellular Automata (CA) for high speed design requires knowledge of the platform specific logic cell architecture. In this paper, we have proposed architectures and design automation of a particular class of CA, essentially a Finite State Machine (FSM), which obey rules governed by principles of Margolus neighborhood. Under this proposition, the inputs to the next state function of the FSM for every CA cell alternates between two sets of data in every successive clock cycle. Careful choice of logic elements and their compact placement was ensured for speed-area efficient implementation. Variants of scan insertion were carried out for fault localization by properly utilizing the logic cells realizing the original Margolus CA, so that area-delay overhead is minimized. We outperform behavioral or register transfer level (RTL) based descriptions for CA implementations, expressed through conventional higher levels of abstraction, with respect to delay and occupancy count of logic slices. (c) 2022 Elsevier Inc. All rights reserved.

关键词： Cellular automata Margolus neighborhood field programmable gate array Primitive instantiation Scan insertion

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Predictive Motion Planning with Pipelined Feature-Based Obstacle Avoidance

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JOURNAL OF GUIDANCE CONTROL AND DYNAMICS 2016年第4期39卷 967-975页

作者： Seiferth, Christoph Joos, Alexander Frangenberg, Michael Fichter, Walter Univ Stuttgart Inst Flight Mech & Control D-70569 Stuttgart Germany

An efficient method for the approximate solution of a finite-horizon constrained optimal control problem was proposed that uses quantized and discretized control candidates in such a way that a real-time implementation on a small onboard computer is feasible. For obstacle or collision avoidance, an algorithm using predicted trajectory points and visible three-dimensional features in a point cloud was presented that is suitable for a parallel and pipelined implementation on a field-programmable gate array. This allows for a very large number of obstacles to be checked by using raw sensor data only without further processing. The second option of an obstacle cost function uses a barrier function approach. It is designed so that the cost tends to infinity if the distance between a predicted trajectory point and an obstacle approaches the minimum distance. Choosing this approach helps to influence the flown trajectory, even when the vehicle has a much greater distance to possible obstacles than the minimum distance, since features always introduce costs on a trajectory and not only if the predicted trajectory violates the minimum distance requirement.

关键词： Model Predictive Control Motion Planning field programmable gate array Flight Testing Optimal Control Quaternions Onboard Computing Navigation Algorithm LIDAR VTOL

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Interlaced switch boxes placement for three-dimensional FPGA architecture design

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2012年第5期40卷 489-502页

作者： Hsu, Chun-Lung Huang, Yu-Sheng Lee, Fong-Chao Natl Dong Hwa Univ Dept Elect Engn Hualien Taiwan

Three-dimensional (3D) field programmable gate array (FPGA) has evoked significant interest in wire-length reduction for routing requirement. However, the complex design of the 3D switch boxes will limit the performance improvement and suffer from the area efficiency problems. This paper proposed a systematic graph model (SGM) for 3D switch boxes design to simplify the design process and reduce the storage memory for path programming. An interlaced 3D switch boxes and two-dimensional (2D) switch boxes placement topology is also presented in this paper to design the 3D FPGA architecture for area efficiency purpose. The 3D place and route tool and TSMC 0.18-mu m CMOS process parameters are used to support building the experimental flow for verification. Performance evaluation shows that about 50% storage memory reduction can be obtained by using the proposed SGM-based switch design approach. Additionally, compared with conventional architectures of 2D FPGA, the proposed scheme based on interlaced switch boxes placement approach can approximately achieve 20% delay-power product improvement and 43% area-delay product reduction. Copyright (c) 2010 John Wiley & Sons, Ltd.

关键词： field programmable gate array interlaced delay-power product area-delay product

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Architecture synthesis methodology for cost-effective run-time reconfigurable systems

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INTERNATIONAL JOURNAL OF EMBEDDED SYSTEMS 2010年第3-4期4卷 225-234页

作者： Chun, Pil Woo (Peter) Kirischian, Lev MDA Corp Space Mission 9445 Airport Rd Brampton ON L6S 4J3 Canada Ryerson Univ Elect & Comp Engn Toronto ON M5B 2K3 Canada

Run-time reconfiguration of field programmable devices can change their internal structure and behaviour in response to dynamic requests. Thus, reconfigurable systems with programmable fabrics can offer a cost effective solution to address the multi functionalities of today's applications. This paper recognises the cost benefits that such run-time adaptability can provide and proposes a novel reconfigurable architecture synthesis methodology to achieve a cost-effective reconfigurable system solution. The proposed architecture synthesis methodology converts a recognised dynamic environment into an assembled micro-level system. New design steps of the methodology identify a multi-task and multi-mode workload, determine an appropriate reconfiguration granularity and synthesise a workload-specific static architecture for a run-time reconfigurable system that enables on-chip assembly of pre-constructed components. The experimental results show the cost benefits of the proposed methodology which saves 73% of area and 29.8% of power compared to fixed design approach for implementing multiple visual processors.

关键词： reconfigurable systems field programmable gate array FPGA architecture synthesis run-time reconfigurability stream applications multi-task systems

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FPGA-Based Robust Wireless Speech Motion Control for Home Service Robot Subject to Environmental Noises

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INTERNATIONAL JOURNAL OF FUZZY SYSTEMS 2017年第3期19卷 925-941页

作者： Pan, Shing-Tai Chang, Cheng-Yuan Tsai, Yi-Heng Natl Univ Kaohsiung Dept Comp Sci & Informat Engn 700 KaohsiungUniv Rd Kaohsiung 811 Taiwan Chung Yuan Christian Univ Dept Elect Engn Jhongli 320 Taiwan Natl Univ Kaohsiung Grad Inst Comp Sci & Informat Engn Kaohsiung 811 Taiwan

In this paper, a robust speech recognition system for the recognition of the speeches subjected to environmental noise is designed and implemented on FPGA to control a home service robot wirelessly. An empirical mode decomposition is used to separate the clean speeches from the speech signals contaminated by environmental noise. To improve the recognition speed, instead of continuous hidden Markov model (CHMM), Discrete HMM (DHMM) is used here to reduce the computation load during speech recognition. However, to compensate the decreased speech recognition rate using DHMM, this paper uses fuzzy vector quantization (FVQ) on the modeling of DHMM to improve the speech recognition rates. It will be shown that the computation time just increases a little, while the speech recognition rates increase much when the FVQ is applied. Finally, combining a wireless module, a FPGA-based speech recognition system is designed to control the motions of a home service robot wirelessly via speech commands under some environmental noises. The performance of the designed system will be demonstrated in the end of this paper.

关键词： Home service robot Fuzzy vector quantization Robust speech recognition Empirical mode decomposition Genetic algorithm field programmable gate array

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Implementation of wideband digital transmitting beamformer based on LFM waveforms

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IET SIGNAL PROCESSING 2017年第2期11卷 205-212页

作者： Fu, Wei Jiang, Defu Su, Yu Qian, Rong Gao, Yang Hohai Univ Coll Comp & Informat Nanjing Jiangsu Peoples R China

A wideband digital transmitting beamformer based on linear frequency modulation (LFM) signals is presented in this study. The wideband beamformer is realised as a combination of direct digital synthesisers and fractional delay (FD) filters in polyphase structure. By using coordinate rotation digital computer algorithm, high intermediate frequency wideband LFM signal is generated and phase compensation for beamforming is accomplished in field programmable gate array. The impact of different number of quantisation bits on signal generation is analysed. The results of waveform generation and FD filter design are given. At last, the transmitting beam pattern is simulated.

关键词： array signal processing modulation delays compensation field programmable gate arrays quantisation (signal) wideband digital transmitting beamformer LFM waveforms linear frequency modulation signals wideband beamformer direct digital synthesisers fractional delay filters polyphase structure digital computer algorithm intermediate frequency wideband LFM signal field programmable gate array quantisation signal generation FD filter design

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Fighting stochastic variability in a D-type flip-flop with transistor-level reconfiguration

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IET COMPUTERS AND DIGITAL TECHNIQUES 2015年第4期9卷 190-196页

作者： Trefzer, Martin A. Walker, James A. Bale, Simon J. Tyrrell, Andy M. Univ York Dept Elect York YO10 5DD N Yorkshire England

In this study, the authors present a design optimisation case study of D-type flip-flop timing characteristics that are degraded as a result of intrinsic stochastic variability in a 25 nm technology process. What makes this work unique is that the design is mapped onto a multi-reconfigurable architecture, which is, like a field programmable gate array (FPGA), configurable at the gate level but can then be optimised using transistor level configuration options that are additionally built into the architecture. While a hardware VLSI prototype of this architecture is currently being fabricated, the results presented here are obtained from a virtual prototype implemented in SPICE using statistically enhanced 25 nm high performance metal gate MOSFET compact models from gold standard simulations for pre-fabrication verification. A D-type flip-flop is chosen as a benchmark in this study, and it is shown that timing characteristics that are degraded because of stochastic variability can be recovered and improved. This study highlights significant potential of the programmable analogue and digital array architecture to represent a next-generation FPGA architecture that can recover yield using post-fabrication transistor-level optimisation in addition to adjusting the operating point of mapped designs.

关键词： flip-flops MOSFET field programmable gate arrays D-type flip-flop timing characteristics intrinsic stochastic variability design optimisation case study technology process multireconfigurable architecture field programmable gate array next-generation FPGA architecture gate level transistor level configuration options hardware VLSI prototype virtual prototype simulation program integrated circuit emphasis statistically enhanced high performance metal gate MOSFET compact models gold standard simulations prefabrication verification programmable analogue architecture digital array architecture post-fabrication transistor-level optimisation operating point size 25 nm

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Hardware and software integrated coursework as a way of engineering ability training in the learning of digital electronics

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INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING EDUCATION 2019年第3期58卷 726-742页

作者： Zhang, Chengchang Gong, Yuwen Luo, Yuan Zhang, Huayu Yan, Dangui Chongqing Univ Posts & Telecommun Coll Electroning Engn 2 Chongwen Rd Chongqing 400065 Peoples R China

A new way oriented to engineering ability training by field programmable gate array-based hardware and software integrated coursework in the learning of digital electronics course in communication engineering is presented. This coursework is implemented in two stages during six weeks, the task of the first stage is hardware design, and the second stage task is the software design;all students are divided into several small teams with three or four persons in the process. A scheme for storing and configuring four different programs by a single programmable read-only memory (PROM)is given in hardware design. In the software design, it emphasizes the selection of the optimization scheme for different design schemes. Through competitive and engineering oriented design evaluation, the students are guided to combine theory with practice more closely to solve the actual engineering problems in the design.

关键词： Digital electronics education coursework field programmable gate array sequence signal generator

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Deep Neural Network-Based Cigarette Filter Defect Detection System with FPGA Acceleration for Online Recognition

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SENSORS 2024年第20期24卷 6752页

作者： Huang, Liang Shen, Qiongxia Jiang, Chao Yang, You Huazhong Univ Sci & Technol Sch Elect Informat & Commun Wuhan 430074 Peoples R China Fiberhome Telecommun Technol Co LTD Wuhan 430205 Peoples R China

In the cigarette manufacturing industry, machine vision and artificial intelligence algorithms have been employed to improve production efficiency by detecting product defects. However, achieving both high accuracy and real-time defect detection for cigarettes with complex patterns remains a challenge. To address these issues, this study proposes a model based on RESNET18, combined with a feature enhancement algorithm, to improve detection accuracy. Additionally, a method is designed to deploy the model on a field-programmable gate array (FPGA) with high parallel processing capabilities to achieve high-speed detection. Experimental results demonstrate that the proposed detection model achieves a detection accuracy of 95.88% on a cigarette filter defect dataset with an end-to-end detection speed of only 9.38 ms.

关键词： defect detection deep neural network field programmable gate array real-time

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