The control performance of converter directly affects the drive efficiency of electric vehicle（EV）.This paper studies on the model predictive control（MPC） based controller design of battery integrated modular mult...
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The control performance of converter directly affects the drive efficiency of electric vehicle（EV）.This paper studies on the model predictive control（MPC） based controller design of battery integrated modular multilevel converter（B-MMC）.Aiming at the goal of three-phase current tracking and battery balancing control of B-MMC,three-layer controllers are *** first controller is the finite control set model predictive control（FCS-MPC）,which realizes the motor drive by tracking the phase *** second controller is the circulation controller for the active balance control of *** is composed of multiple proportional controllers to realize the battery balance between the bridge *** third controller is the battery sorting algorithm to achieve the passive balance control of the battery in the same bridge *** the same time,field programmable gate array（FPGA） is used to accelerate the controller to meet the real-time requirements of ***,the simulation results of the B-MMC control system validates the effectiveness of the control algorithm.
The optical ZCZ code is a set of pairs of binary and bi-phase sequences with zero correlation zone. An optical code division multiple access (CDMA) system using this code can remove co-channel interference and influen...
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The optical ZCZ code is a set of pairs of binary and bi-phase sequences with zero correlation zone. An optical code division multiple access (CDMA) system using this code can remove co-channel interference and influence of multi-path. We proposed the compact construction of a bank of matched filters for this code in a receiver. But we have not proposed the construction of a code generator for this code in a transmitter yet.
In this paper, we propose the construction of two code generators for an optical ZCZ code using a Sylvester-type Hadamard matrix, which are called ROM-type and non ROM- type code generators. This ROM-type code generator can be constructed by a ROM and a up-counter. Similarly,this non ROM-type code generator can be constructed by a up-counter, flip-flops and logic gates. The ROM-type and non ROM-type code generators are implemented on a field programmable gate array (FPGA) corresponding to 400,000 logic gates, and the non ROM-type code generator can reduce logic elements than the ROM-type code generator.
This paper presents the TURTLE fault injection platform for inserting faults into SRAM FPGAs. The TURTLE system is designed to gather significant fault injection data to test and validate radiation-induced single-even...
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ISBN:
(纸本)9781728119588
This paper presents the TURTLE fault injection platform for inserting faults into SRAM FPGAs. The TURTLE system is designed to gather significant fault injection data to test and validate radiation-induced single-event upset (SEU) mitigation techniques for FPGAs. The TURTLE is a low-cost fault injection platform that emulates upsets within the configuration memory (CRAM) of an FPGA through partial reconfiguration. This work successfully implemented the proposed architecture and performed several successful fault injection campaigns on multiple designs and SEU mitigation techniques. Results in this paper show large amounts of data collected from a fault injection campaign used to validate the PCMF SEU mitigation technique. Over 170 million injections were performed using the TURTLE for this campaign.
Explain the factors which affect the performance of optical current transformer (OCT) and Solutions. Signal processing measure is the key to the application of optical current transformer. Therefore the signal process...
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Explain the factors which affect the performance of optical current transformer (OCT) and Solutions. Signal processing measure is the key to the application of optical current transformer. Therefore the signal processing system’s improved method of optical current transformer was introduced, and prospects the future development of optical current transformers.
The hippocampus in human brain is responsible for memory processing and tasks learning, which has long been one of the main interests of many researchers. In this paper, a spiking neural network of the hippocampus is ...
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The hippocampus in human brain is responsible for memory processing and tasks learning, which has long been one of the main interests of many researchers. In this paper, a spiking neural network of the hippocampus is realized based on a designed task. In the task, the model rat firstly gets familiar with the environment and finds item in one of the pots and finally gets a reward for making the correct response. Through the network, the feature of the hippocampal neurons can be simulated in software successfully. The three-layer network was built based on the spike-timing dependent synaptic plasticity and the synaptic weights will be modified between layers during task which can finally achieve the memory-related behavior of the model rat. Besides software realization, we also utilize field programmable gate array(FPGA) to reproduce the characteristics of the network in real time. The results show that the spiking neural network of the hippocampus can mimic the memory-related behavior of the model rat.
The instrumentation group at the Monash Centre for Synchrotron Science have developed a low cost generic data acquisition system. This system is to be used in a variety of applications and to assist in the design and ...
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The instrumentation group at the Monash Centre for Synchrotron Science have developed a low cost generic data acquisition system. This system is to be used in a variety of applications and to assist in the design and testing of emerging detectors. The system utilises a desktop PC which interfaces to a detector via one or more custom 64-bit PCI cards, each equipped with an Altera CycloneII FPGA (2c70) and plug-in daughter boards, this provides flexibility to easily customise analogue and digital signal processing. A GUI application controls the system via variables and scripts, renders and analyses real-time data, and supports importing and exporting in a variety of formats. This paper presents an overview of the data acquisition system and the process of interfacing with a two-dimension multi-wire proportional chamber with delay-line readout with an expected timing resolution of 10 ρs.
In the present study, a data acquisition system for a GEM one-dimensional array detector is presented. The detector system is to measure the trajectory of photoelectrons produced by cosmic rays. The GEM array detector...
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In the present study, a data acquisition system for a GEM one-dimensional array detector is presented. The detector system is to measure the trajectory of photoelectrons produced by cosmic rays. The GEM array detector for the present project has 16 signal channels. The front-end unit provides timing signals from trigger units and energy signals from charge sensitive amplifies and pulse shapers. The timing signals and the energy signals are fed to the time-to-digital converter (TDC) units and analog-to-digital converter (ADC) units respectively. The TDC is to measure the time interval between time marks provided by the front-end unit for trajectory information. The measurement of the pulse height for particle energy information is using an amplitude to time convertor (ATC). The designed TDC has a resolution about 2 ns with good linearity.
Aiming at the problem of high power consumption and slow operation speed of neural network in embedded system, this paper presents an automatic design method of convolutional neural network(CNN) accelerator based on f...
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Aiming at the problem of high power consumption and slow operation speed of neural network in embedded system, this paper presents an automatic design method of convolutional neural network(CNN) accelerator based on field programmable gate array(FPGA) to meet the requirements of embedded terminal for operation performance and power consumption. Firstly, in order to reduce the storage resources of the FPGA and the time required for network computing, the weight quantization method is used to convert network parameters from floating-point data to binary data. Secondly, in order to improve the speed and throughput of the whole system, coarse-grained and fine-grained parallel computing optimization methods are used. In this paper, the above acceleration scheme will be applied to the scene of unmanned aerial vehicle(UAV) object detection. The test results shows that the power consumption of the system is 2.38 W and the calculated power consumption ratio is 29.3 GOPS/W. Compared with the work of related literature in recent years, the proposed scheme can provide higher speed and efficiency. The experimental results show that the accuracy of the IOU is 21% and the speed is 7 FPS.
Nowadays the weak signal detection technology is necessary in scientific research field, in which the phase-locked amplifying technology is widely used in the field of weak signal detection because it can meet the req...
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Nowadays the weak signal detection technology is necessary in scientific research field, in which the phase-locked amplifying technology is widely used in the field of weak signal detection because it can meet the requirements of high speed and high *** Generator software is adopted as a tool since System Generator can make the design more conveniently and *** design of each module in orthogonal vector type digital phase-locked amplifier is introduced in this *** overall design was *** simulation results confirm that the design is feasible.
In today's technological era, SOC has undergone rapid evolution and is still processing at a swift pace. But due to this explosive evolution of semiconductor industry, the devices are scaling down at a rapid rate ...
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In today's technological era, SOC has undergone rapid evolution and is still processing at a swift pace. But due to this explosive evolution of semiconductor industry, the devices are scaling down at a rapid rate and hence, SOC today have become communication-centric. However, the existing bus architectures comprising of wires for global interconnection in SOC design are undergoing design crises as they are not able to keep up with the rate of scaling down of devices. To overcome bottleneck of communication system, NOC is an upcoming archetype. In on-chip network, router is considered as an important component. This paper proposes router, its components and parameters which affects the entire design. Thus, to validate the functioning of NOC on hardware, router has been designed in VHDL and simulated in Xilinx ISE 14.1 targeting Xilinx XC5VLX30-3 FPGA.
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