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field programmable gate array-based PCI interface for a coprocessor system

MICROPROCESSORS AND MICROSYSTEMS 1999年第7期22卷 373-388页

作者： Kuusilinna, K Hämäläinen, T Saarinen, J Tampere Univ Technol Signal Proc Lab FIN-33101 Tampere Finland

This paper presents the design and implementation of a field programmable gate array (FPGA)-based PCI bus interface for a general purpose parallel neurocomputer, which is hosted by a personal computer. The basic background of the PCI bus and a detailed discussion of applicable FPGA design considerations are given. With FPGA, critical implementation factors are the realization of fast-enough state machines and efficient resource allocation. Emphasis is placed on presenting how to allocate resources efficiently from the VHDL hardware description language. Related to the overall implementation, PCI bus agent initialization and configuration from the operating system are considered. (C) 1999 Elsevier Science Ltd. All rights reserved.

关键词： PCI field programmable gate array VHDL synthesis

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Comment on "Generic universal switch blocks"

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IEEE TRANSACTIONS ON COMPUTERS 2002年第1期51卷 93-95页

作者： Fan, HB Wu, YL Chang, YW Univ Victoria Dept Comp Sci Victoria BC V8W 3P6 Canada Chinese Univ Hong Kong Dept Comp Sci & Engn Shatin Hong Kong Peoples R China Natl Chiao Tung Univ Dept Comp & Informat Sci Hsinchu 300 Taiwan

In the paper [5], the authors defined the well-structured symmetric switch block M-N,M-W and showed that M-N,M-W is universal for any pair of positive integers N and W, However, we find that this result is partially correct. Here, we show that, when N greater than or equal to 7, M-N,M-W is not universal for odd Ws (greater than or equal to 3) and it is universal for any even W.

关键词： field programmable gate array universal switch block design FPGA routing

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An uncooled infrared sensor of dielectric bolometer mode using a new detection technique of operation bias voltage

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SENSORS AND ACTUATORS A-PHYSICAL 2002年 97-8卷 329-336页

作者： Noda, M Inoue, K Ogura, M Xu, HP Murakami, S Kishihara, K Okuyama, M Osaka Univ Grad Sch Engn Dept Phys Sci Area Mat & Device Phys Toyonaka Osaka 5608531 Japan Technol Res Inst Osaka Prefecture Izumi 5941157 Japan Sanyo Elect Co Ltd New Mat Res Ctr Funct Mat Dept Hirakata Osaka 5738534 Japan Shimadzu Co Ltd Technol Res Lab Kyoto 6190237 Japan

A new operation technique of dielectric bolometer (DB) mode infrared (IR) image sensor has been developed to ensure both highly sensitive IR detection and uniform IR sensitivity in every detector pixel. After calculating and adjusting the optimum amplitude and phase of supply voltage to the pixel circuit, the voltage waveform with individually adjusted amplitude and phase is supplied to every detector pixel for compensation of the output offset. A key technique is to use a field programmable gate array (FPGA) to feed the adjusted supply voltage to detector pixels when applying the compensation method to a pixel array. A program was also developed to make the adjusted supply voltage and induce the output of the detector pixels with data communication between the FPGA and a controlling personal computer. It was found that the compensation technique enables the I x 4 array to have nearly zero-offset level in all the pixels and therefore high and uniform IR detectivity. Finally, with this technique, we have fabricated several IR sensor arrays of 4 x 4, 8 x 8, and 16 x 16 pixels, where high IR sensitivities such as R-v and D* of 1.2 kV/W and 2.9 x 10(8) cm, Hz(1/2)/W, respectively, and a resultant two-dimensional image of an IR source were successfully obtained. (C) 2002 Published by Elsevier Science B.V.

关键词： infrared sensor dielectric bolometer detector pixel compensation field programmable gate array uncooled focal plane array

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An uncooled infrared sensor of dielectric bolometer mode using a new detection technique of operation bias voltage

An uncooled infrared sensor of dielectric bolometer mode usi...

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Transducers 2001 Conference/Eurosensor XVth Conference

ISBN: (纸本)3540421505

关键词： infrared sensor dielectric bolometer detector pixel compensation field programmable gate array uncooled focal plane array

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Autonomous Genetic Machine

Autonomous Genetic Machine

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IEEE Canadian Conference on Electrical and Computer Engineering

作者： Karnik, G Reformat, M Pedrycz, W Univ Alberta Edmonton AB T6G 2M7 Canada

ISBN: (纸本)0780375149

Research in evolvable hardware includes application of evolutionary, methods in a process of system design and on-line system adaptation. Building a hardware system capable of performing adaptation processes without external computing resources is a necessary step towards achieving a high level autonomy. Such a system, called Autonomous Genetic Machine (AGM), is presented in this paper. It represents a hardware realization of a Genetic Algorithm. Modular architecture of the AGM ensures its ease for modifications and suitability for different applications. A detailed description of design stages and implementation issues is included with emphasis focused on performance-related topics. The elaborate on the role of crucial parameters of genetic optimization such as population size, chromosome length as well as discuss various possibilities in the formation of the fitness function. In particular, we show how to design AGM for Altera's FPGAs.

关键词： Genetic Algorithms hardware implementation field programmable gate array autonomous systems evolvable hardware

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Arithmetic implementation techniques and methodologies for 3G uplink reception in Xilinx FPGAs

Arithmetic implementation techniques and methodologies for 3...

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3rd International Conference on 3G Mobile Communication Technologies

作者： Macpherson, K Stirling, I Rice, G García-Alís, D Stewart, R Univ Strathclyde Glasgow G1 1XQ Lanark Scotland

ISBN: (纸本)0852967497

DSP system-level design decisions can have significant effects on field programmable gate array (FPGA) hardware cost and efficiency. In this paper we demonstrate how modifying filter coefficients and taking advantage of non-canonical implementation techniques can yield reduced FPGA hardware cost. Using the Root-Raised Cosine (RRC) pulse shaping filters required in the 3G uplink reception chain as an example, different implementation techniques are compared in terms of DSP system performance and FPGA cost. RRC filter performance is evaluated through simulation of the Adjacent Channel Selectivity (ACS) test. Simulation results are presented and the differing hardware structures are evaluated.

关键词： field programmable gate arrays noncanonical implementation techniques filter coefficients FPGA hardware cost field programmable gate array DSP system-level design decisions FIR filters digital signal processing chips 3G mobile communication

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Third Military and Aerospace programmable-Logic Devices International Conference (MAPLD'2000)

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JOURNAL OF SPACECRAFT AND ROCKETS 2002年第4期39卷 473-473页

作者： Vladimirova, T Katz, R Univ Surrey Surrey Space Ctr Guildford GU2 5XH Surrey England NASA Goddard Space Flight Ctr Greenbelt MD 20771 USA

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A routability driven technology mapping algorithm for LUT based FPGA designs

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2001年第11期E84A卷 2690-2696页

作者： Kao, CC Lai, YT Natl Cheng Kung Univ Dept Elect Engn Tainan 701 Taiwan

This paper presents a CAD technology mapping algorithm for LUT-based FPGAs. Since interconnections in an FPGA must be accomplished with limited routing resources, routability is the most important objective in a technology mapping algorithm. To optimize routability, the goal of the algorithm is the production of a design with a minimum interconnection. The Min-cut algorithm [1]-[3] is first used to partition a graph representing a Boolean network into clusters so that the total number of interconnections between clusters is minimum. To decrease further the number of interconnect ions needed, clusters are then merged into larger clusters by a pairing technique. This algorithm has been tested on the MCNC benchmark circuits. Compared with other LUT-based FPGA mapping algorithms, the algorithm produces better routability characteristics.

关键词： technology mapping routability min-cut field programmable gate array

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Evolving a spatio-spectral network on reconfigurable computers for multi-spectral feature identification

Evolving a spatio-spectral network on reconfigurable compute...

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Conference on Imaging Spectrometry VII

作者： Porter, R Gokhale, M Harvey, N Perkins, S Young, C Los Alamos Natl Lab Los Alamos NM 87545 USA

ISBN: (纸本)0819441945

Feature identification attempts to find algorithms that can consistently separate a feature of interest from the background in the presence of noise and uncertain conditions. This paper describes the development of a high-throughput, reconfigurable computer based, feature identification system known as POOKA. POOKA is based on a novel spatio-spectral network, which can be optimized with an evolutionary algorithm on a problem-by-problem basis. The reconfigurable computer provides speed up in two places: 1) in the training environment to accelerate the computationally intensive search for new feature identification algorithms, and 2) in the application of trained networks to accelerate content based search in large multi-spectral image databases. The network is applied to several broad area features relevant to scene classification. The results are compared to those found with traditional remote sensing techniques as well as an advanced software system known as GENIE. The hardware efficiency and performance gains compared to software are also reported.

关键词： field programmable gate array reconfigurable computer evolutionary algorithm evolvable hardware feature extraction classification feature identification pattern recognition multi-spectral

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Designing a Java microprocessor core using FPGA technology

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COMPUTING & CONTROL ENGINEERING JOURNAL 2000年第3期11卷 135-141页

作者： Kim, A Chang, M Lucent Techol Murray Hill NJ 07974 USA IIT Chicago IL 60616 USA

Ever since its introduction from Sun Microsystems four years ago, Java has been widely accepted in the computing and Internet industry. However, the runtime performance is still not good enough for Java to become a general-purpose programming language. This article shows how to implement a Java microprocessor core in silicon to speed up the execution of Java. For a reconfigurable and flexible design, the field programmable gate array is chosen as a target technology for the Java microprocessor. By applying a top-down hardware design methodology to the FPGA design process, it becomes easier and more flexible to implement Java in a FPGA. The DFT technique is added for better testability.

关键词： Computer architecture Microprocessor chips FPGA design process Microprocessors and microcomputers Sun Microsystems flexible design field programmable gate array general-purpose programming language Java microprocessor core design silicon implementation Digital circuit design, modelling and testing Object-oriented programming target technology Distributed systems software field programmable gate arrays Logic circuits Logic and switching circuits Java Logic design methods microprocessor chips High level languages reconfigurable architectures design for testability FPGA technology top-down hardware design methodology runtime performance DFT technique

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