In the paper [5], the authors defined the well-structured symmetric switch block M-N,M-W and showed that M-N,M-W is universal for any pair of positive integers N and W, However, we find that this result is partially c...
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In the paper [5], the authors defined the well-structured symmetric switch block M-N,M-W and showed that M-N,M-W is universal for any pair of positive integers N and W, However, we find that this result is partially correct. Here, we show that, when N greater than or equal to 7, M-N,M-W is not universal for odd Ws (greater than or equal to 3) and it is universal for any even W.
A new operation technique of dielectric bolometer (DB) mode infrared (IR) image sensor has been developed to ensure both highly sensitive IR detection and uniform IR sensitivity in every detector pixel. After calculat...
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A new operation technique of dielectric bolometer (DB) mode infrared (IR) image sensor has been developed to ensure both highly sensitive IR detection and uniform IR sensitivity in every detector pixel. After calculating and adjusting the optimum amplitude and phase of supply voltage to the pixel circuit, the voltage waveform with individually adjusted amplitude and phase is supplied to every detector pixel for compensation of the output offset. A key technique is to use a field programmable gate array (FPGA) to feed the adjusted supply voltage to detector pixels when applying the compensation method to a pixel array. A program was also developed to make the adjusted supply voltage and induce the output of the detector pixels with data communication between the FPGA and a controlling personal computer. It was found that the compensation technique enables the I x 4 array to have nearly zero-offset level in all the pixels and therefore high and uniform IR detectivity. Finally, with this technique, we have fabricated several IR sensor arrays of 4 x 4, 8 x 8, and 16 x 16 pixels, where high IR sensitivities such as R-v and D* of 1.2 kV/W and 2.9 x 10(8) cm, Hz(1/2)/W, respectively, and a resultant two-dimensional image of an IR source were successfully obtained. (C) 2002 Published by Elsevier Science B.V.
A new operation technique of dielectric bolometer (DB) mode infrared (IR) image sensor has been developed to ensure both highly sensitive IR detection and uniform IR sensitivity in every detector pixel. After calculat...
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ISBN:
(纸本)3540421505
A new operation technique of dielectric bolometer (DB) mode infrared (IR) image sensor has been developed to ensure both highly sensitive IR detection and uniform IR sensitivity in every detector pixel. After calculating and adjusting the optimum amplitude and phase of supply voltage to the pixel circuit, the voltage waveform with individually adjusted amplitude and phase is supplied to every detector pixel for compensation of the output offset. A key technique is to use a field programmable gate array (FPGA) to feed the adjusted supply voltage to detector pixels when applying the compensation method to a pixel array. A program was also developed to make the adjusted supply voltage and induce the output of the detector pixels with data communication between the FPGA and a controlling personal computer. It was found that the compensation technique enables the I x 4 array to have nearly zero-offset level in all the pixels and therefore high and uniform IR detectivity. Finally, with this technique, we have fabricated several IR sensor arrays of 4 x 4, 8 x 8, and 16 x 16 pixels, where high IR sensitivities such as R-v and D* of 1.2 kV/W and 2.9 x 10(8) cm, Hz(1/2)/W, respectively, and a resultant two-dimensional image of an IR source were successfully obtained. (C) 2002 Published by Elsevier Science B.V.
Research in evolvable hardware includes application of evolutionary, methods in a process of system design and on-line system adaptation. Building a hardware system capable of performing adaptation processes without e...
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ISBN:
(纸本)0780375149
Research in evolvable hardware includes application of evolutionary, methods in a process of system design and on-line system adaptation. Building a hardware system capable of performing adaptation processes without external computing resources is a necessary step towards achieving a high level autonomy. Such a system, called Autonomous Genetic Machine (AGM), is presented in this paper. It represents a hardware realization of a Genetic Algorithm. Modular architecture of the AGM ensures its ease for modifications and suitability for different applications. A detailed description of design stages and implementation issues is included with emphasis focused on performance-related topics. The elaborate on the role of crucial parameters of genetic optimization such as population size, chromosome length as well as discuss various possibilities in the formation of the fitness function. In particular, we show how to design AGM for Altera's FPGAs.
DSP system-level design decisions can have significant effects on field programmable gate array (FPGA) hardware cost and efficiency. In this paper we demonstrate how modifying filter coefficients and taking advantage ...
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ISBN:
(纸本)0852967497
DSP system-level design decisions can have significant effects on field programmable gate array (FPGA) hardware cost and efficiency. In this paper we demonstrate how modifying filter coefficients and taking advantage of non-canonical implementation techniques can yield reduced FPGA hardware cost. Using the Root-Raised Cosine (RRC) pulse shaping filters required in the 3G uplink reception chain as an example, different implementation techniques are compared in terms of DSP system performance and FPGA cost. RRC filter performance is evaluated through simulation of the Adjacent Channel Selectivity (ACS) test. Simulation results are presented and the differing hardware structures are evaluated.
This paper presents a CAD technology mapping algorithm for LUT-based FPGAs. Since interconnections in an FPGA must be accomplished with limited routing resources, routability is the most important objective in a techn...
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This paper presents a CAD technology mapping algorithm for LUT-based FPGAs. Since interconnections in an FPGA must be accomplished with limited routing resources, routability is the most important objective in a technology mapping algorithm. To optimize routability, the goal of the algorithm is the production of a design with a minimum interconnection. The Min-cut algorithm [1]-[3] is first used to partition a graph representing a Boolean network into clusters so that the total number of interconnections between clusters is minimum. To decrease further the number of interconnect ions needed, clusters are then merged into larger clusters by a pairing technique. This algorithm has been tested on the MCNC benchmark circuits. Compared with other LUT-based FPGA mapping algorithms, the algorithm produces better routability characteristics.
Feature identification attempts to find algorithms that can consistently separate a feature of interest from the background in the presence of noise and uncertain conditions. This paper describes the development of a ...
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ISBN:
(纸本)0819441945
Feature identification attempts to find algorithms that can consistently separate a feature of interest from the background in the presence of noise and uncertain conditions. This paper describes the development of a high-throughput, reconfigurable computer based, feature identification system known as POOKA. POOKA is based on a novel spatio-spectral network, which can be optimized with an evolutionary algorithm on a problem-by-problem basis. The reconfigurable computer provides speed up in two places: 1) in the training environment to accelerate the computationally intensive search for new feature identification algorithms, and 2) in the application of trained networks to accelerate content based search in large multi-spectral image databases. The network is applied to several broad area features relevant to scene classification. The results are compared to those found with traditional remote sensing techniques as well as an advanced software system known as GENIE. The hardware efficiency and performance gains compared to software are also reported.
Ever since its introduction from Sun Microsystems four years ago, Java has been widely accepted in the computing and Internet industry. However, the runtime performance is still not good enough for Java to become a ge...
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Ever since its introduction from Sun Microsystems four years ago, Java has been widely accepted in the computing and Internet industry. However, the runtime performance is still not good enough for Java to become a general-purpose programming language. This article shows how to implement a Java microprocessor core in silicon to speed up the execution of Java. For a reconfigurable and flexible design, the field programmable gate array is chosen as a target technology for the Java microprocessor. By applying a top-down hardware design methodology to the FPGA design process, it becomes easier and more flexible to implement Java in a FPGA. The DFT technique is added for better testability.
Synchronisation is a requirement of all digital communication systems, while signal-to-noise ratio estimation is a particular requirement when using the maximum a posteriori probability algorithm for the iterative sta...
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Synchronisation is a requirement of all digital communication systems, while signal-to-noise ratio estimation is a particular requirement when using the maximum a posteriori probability algorithm for the iterative stage of a turbo code. The authors address these requirements and provide novel digital algorithms using the trellis structure of the component codes in a turbo code system. The results show that the algorithms provide the necessary functionality without degradation of performance and, as they are purely digital solutions, they are suitable for implementation on a digital signal processor or field programmable gate array.
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