This paper presents the design and implementation of access controller used for Ethernet passive optical network （ EPON）. As a first step to develop an ASIC product, the entire system is designed on a field programm...
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This paper presents the design and implementation of access controller used for Ethernet passive optical network （ EPON）. As a first step to develop an ASIC product, the entire system is designed on a field programmable gate array （FPGA） with an embedded CPU. To reduce working frequency of the FPGA, the byte-to-word conversion is proposed. Propagation delays are equalized by ranging procedure so as to avoid data collision. Implementations of synchronization, classification, as well as Linux porting are illustrated in detail. The interface between the FPGA and CPU are also presented. Experimental results show that the proposed system can properly function in a relatively low cost FPGA.
Based on the concept of graph pattern-matching, a universal FPGA logic cell mapping algorithm (FDUMap) was studied by adding graph constraints to subgraph isomorphism algorithm according to circuit character. In the e...
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Based on the concept of graph pattern-matching, a universal FPGA logic cell mapping algorithm (FDUMap) was studied by adding graph constraints to subgraph isomorphism algorithm according to circuit character. In the experiment, FDUMap can successfully map the benchmarks to logic cells of different structures. Compared with existing logic cell specific mapping algorithms, FDUMap is better in universality and only 3% worse in average performance.
A new real-time contrast enhancement algorithm for infrared images is presented. By analyzing the histogram of image and self-adaptively selecting threshold value, the modified histogram is gotten. This algorithm can ...
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A new real-time contrast enhancement algorithm for infrared images is presented. By analyzing the histogram of image and self-adaptively selecting threshold value, the modified histogram is gotten. This algorithm can greatly enhance the contrast of infrared images by histogram equalization using the modified histogram. It has advantages of enhancing targets and suppressing backgrounds over general histogram equalization. The contrast of images enhanced by this algorithm is improved approximately 1.8 times than that of images enhanced by general histogram equalization. And it can be easily implemented by in FPGA for real-time imaging applications. This paper describes a simple and effective implementation of this algorithm by using pipeline and parallel computation architecture. It can process 25 frames images of 128 × 128 × 8 bits per second.
Small nuclear physics laboratories of all kinds traditionally have processed the signals from radiation detectors with a variety of discrete NIM- or CAMAC-based electronic modules. The logic signals associated with si...
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Small nuclear physics laboratories of all kinds traditionally have processed the signals from radiation detectors with a variety of discrete NIM- or CAMAC-based electronic modules. The logic signals associated with signal processing are often passed through gate generators, coincidence modules, fan-in/fan-out modules, delay units, counters, and other assorted logic modules. These multi-component systems generate gates for acquisition systems, gates for specific linear electronics modules (ADCs and TDCs), or measure count rates and dead times. This can involve a significant number of individual modules each of which can be quite costly and each of which provides only limited functions. We describe here an upgrade to our acquisition system where all the needed logic functions are performed in just a single unit: a Universal Logic Module based on a field programmable gate array (FPGA) from JTEC Corporation. This module also contains flash memory that holds three separate configurations allowing for rapid changes from one electronics configuration to a different one. Both CAMAC and VME versions of the unit are available. The system described here is just one example of the huge variety of functionality that can be programmed into this single module. It can accommodate very complicated circuits and is easily reprogrammed. In the small nuclear physics laboratory the Universal Logic Module can save cost when upgrading systems and reduce the number of instances where one has an insufficient number of channels of a particular function. (c) 2005 Elsevier B.V. All rights reserved.
Colour space conversion is very important in many types of image processing applications including video compression. This operation consumes up to 40% of the entire processing power of a highly optimised decoder. The...
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Colour space conversion is very important in many types of image processing applications including video compression. This operation consumes up to 40% of the entire processing power of a highly optimised decoder. Therefore, techniques which efficiently implement this conversion are desired. This paper presents two novel architectures for efficient implementation of a Colour Space Converter (CSC) suitable for field programmable gate array (FPGAs) and VLSI. The proposed architectures are based on Distributed Arithmetic (DA) ROM accumulator principles. The architectures have been implemented and verified using the Celoxica RC1000 FPGA development board. In addition, they are platform independent and have a low latency (eight cycles). The first architecture has a throughput of height, while the second one is fully pipelined and has a throughput of one and capable of sustained data rate of over 234 mega-conversions/s. (c) 2005 Elsevier B.V. All rights reserved.
This paper presents a new multiplexer based FPGA, which can operate at a clock frequency of 5-10 GHz. Redundant switches on the original signal paths are removed improving the performance. The configurable logic block...
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This paper presents a new multiplexer based FPGA, which can operate at a clock frequency of 5-10 GHz. Redundant switches on the original signal paths are removed improving the performance. The configurable logic blocks (CLBs) power is greatly reduced by using a revised multiplexer structure and turning off unused cells dynamically. More routing capabilities are provided with more inputs/outputs in each direction than similar designs. A chip consisting of four FPGA ring oscillators was fabricated. The Spice simulation results and chip measurement, are presented, (C) 2004 Elsevier B.V. All rights reserved.
A new methodology for realising efficient multiply architectures for FPGAs is presented. The proposed strategy can be recursively applied to realise larger multipliers. Compared to proprietary macroblocks usually furn...
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A new methodology for realising efficient multiply architectures for FPGAs is presented. The proposed strategy can be recursively applied to realise larger multipliers. Compared to proprietary macroblocks usually furnished within FPGA development tools, the new approach is more than 45% cheaper and more than 25% faster.
In this paper, we present an efficient approach to HW/SW partitioning of applications targeted for embedded soft-core SoPC and programmable logic. The methodology is based on the iterative performance analysis of the ...
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In this paper, we present an efficient approach to HW/SW partitioning of applications targeted for embedded soft-core SoPC and programmable logic. The methodology is based on the iterative performance analysis of the initial functional SW description and performance estimation of various HW/SW partitioning configurations. The main focus is on adequate profiling of arbitrary SW code regions (function or single instruction level) with clock-cycle accuracy without introducing additional execution overhead. In order to support the profiling for partitioning, we have developed the COMET Profiler tool. The performance analysis and estimation in the simulation and implementation domains are supported, necessitating no design and implementation of HW co-processing blocks for the partitioning evaluation. The design process is illustrated with two case studies. (c) 2004 Elsevier B.V. All rights reserved.
This paper examines and describes the processes of designing a hardware-based rendering engine for a multiple-colour LED display board. A proposed procedure for generating more shades of multiple colours from the LEDs...
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This paper examines and describes the processes of designing a hardware-based rendering engine for a multiple-colour LED display board. A proposed procedure for generating more shades of multiple colours from the LEDs is described. The weaknesses of the software-based image-rendering algorithm are examined. It is proposed that the software-based image-rendering component be replaced by a more robust hardware-based image generation module. (C) 2005 Elsevier B.V. All rights reserved.
In this paper a novel field programmable gate array (FPGA) implementation of differential space vector pulse width modulator (DSVPWM) is presented. FPGA circuit was chosen because DSVPWM requires high computational po...
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ISBN:
(纸本)0769524567
In this paper a novel field programmable gate array (FPGA) implementation of differential space vector pulse width modulator (DSVPWM) is presented. FPGA circuit was chosen because DSVPWM requires high computational power and its algorithms can be easily parallelized. The use of traditional sequential processor would need very last and expensive hardware compared to the FPGA implementation. DSVPWM enables more accurate flux linkage formation than traditional modulators. DSVPWM is completely new modulation method and this paper presents its first implementation.
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