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Annual Conference of the IEEE Industrial Electronics Society

作者： M. Dagbagi A. Hemdani L. Idkhajine M. W. Naouar E. Monmasson I. Slama-Belkhodja Universite de Tunis El Manar ENIT SATIE-IUP GEII

ISBN: (纸本)9781479902255

The proposed paper deals with Hardware-In-the-Loop (HIL) validation of a 3-phase PWM boost rectifier controller. This validation has been made using field programmable gate array (FPGA) target. The development of the Real-Time Emulator (RTE) of the power system is firstly discussed. All voltage sources from the grid, filters, power switches and the load real-time models are implemented in hardware using a Xilinx Spartan-6 FPGA device. As for the controller, a PI-based strategy has been chosen to control the DC-link voltage and a Hysteresis-based one for the control of 3-phase line currents. This controller has been implemented in software using the embedded Cortex-M3 processor of SmartFusion FPGA from MicroSemi. Real-time HIL simulation results, as well as offline simulation results are presented and compared.

关键词： Real time Hardware-In-the-Loop PWM boost rectifier field programmable gate array Real-Time Emulator Associate Discrete Circuit Processor-based controller

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Area Efficient Vernier Time to Digital Converter(TDC) with Improved Resolution using Identical Ring Oscillators on FPGA

Area Efficient Vernier Time to Digital Converter(TDC) with I...

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IEEE International Conference on Smart Structures and Systems

作者： Mahantesh P Mattada Hansraj Guhilot Department of Electronics &Telecommunication Sanjay Godawat Group of Institutions Kolhapur INDIA Department of Electronics & Communication K.L.E. Society's College of Engineering & Technology Belgaum INDIA

ISBN: (纸本)9781467362429

We present an area efficient Time to Digital Converter (TDC) based on Vernier Principle yielding a high resolution of nearly 5ps. The TDC architecture reported in this paper uses Nutt Interpolation method i.e. comprises of coarse measurement using system clock and two controllable ring oscillators for fine measurement. Ring oscillators used in this work are identical and designed using fast carry logic. The reported improved resolution is attributed to the difference in their frequencies. The novel technique of obtaining difference in their period reduces manual efforts of designer. Two main features of this work are prototyping on a low-cost general purpose FPGA and new low cost verification methodology.

关键词： Time to Digital Converter TOF Tapped Delay Line field programmable gate array Fluorescence Vernier Delay Line Ring oscillator Ring oscillators field programmable gate arrays FEZF2 gene tapped delay line Fluorescence system clock Identical

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基于FPGA与流比器的损耗电流谐波分量测试系统开发

基于FPGA与流比器的损耗电流谐波分量测试系统开发

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作者：韩加佳哈尔滨理工大学

学位级别：硕士

交联聚乙烯绝缘电力电缆在输配电线路中的应用越来越广泛,已经成为城市电网的主体。水树老化一直是影响交联聚乙烯绝缘电力电缆线路长期运行可靠性的关键因素。为了保证交联聚乙烯绝缘电力电缆的安全运行,有必要开发适应工业现场应用、... 详细信息

交联聚乙烯绝缘电力电缆在输配电线路中的应用越来越广泛,已经成为城市电网的主体。水树老化一直是影响交联聚乙烯绝缘电力电缆线路长期运行可靠性的关键因素。为了保证交联聚乙烯绝缘电力电缆的安全运行,有必要开发适应工业现场应用、操作简单方便的绝缘状态测试系统对其绝缘状态进行诊断。课题组开发的损耗电流谐波分量测试系统,在工程实际应用中被证明是一套有效的测试系统。然而,该设备操作复杂、耗时给操作者带来了不小的麻烦。为此,有必要在该测试系统的基础之上,开发出一套简单易操作的测试系统。本文首先提出了利用可控补偿电流方法实现流比器电桥自动平衡的设计方案,可大大简化设备的操作。在该方案中,由信号采集模块将电压信号和流比器不平衡电流信号同步采集至控制系统中,利用确定的算法计算出需要补偿的电流信号大小,而后通过电压控制电流源产生流经流比器补偿线圈的电流对被测电流进行补偿。补偿效果通过检测线圈的输出来判断,通过不断修正补偿电流信号实现电流比较器的平衡。然后根据安匝平衡原理计算出试品电流的真实信息,此过程通过控制系统自动完成,进而实现谐波分量的自动化测试。确定测试系统设计方案后,对可控补偿电流的算法进行了研究。提出了基于试品非线性模型的可控补偿电流算法,即在FPGA内构建与试品非线性模型相对应的非线性模型,激励电压信号作为FPGA中非线性模型的输入,通过实时操作系统输出补偿电流信号。FPGA中非线性模型系数通过多元线性拟合求得,通过模拟仿真验证了该计算方法的正确性。在软件算法制定好之后,通过LabVIEW软件开发平台,对FPGA和实时控制器进行了软件编程。而后,软件系统与硬件结合搭建了测试系统。最后,以标准介质损耗器作为试品,对测试系统进行了验证性试验。验证性试验证实了测试系统的设计方案是可行的,但测试误差较大,测试系统还有待于进一步修正和完善。

关键词： field programmable gate array 实时测试系统非线性模型

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FPGA Implementation of Real-Time Soldier Activity Detection based on Neural Network Classifier in Smart Military Suit

FPGA Implementation of Real-Time Soldier Activity Detection ...

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IEEE Bombay Section Signature Conference (IBSSC)

作者： Nikhil B. Gaikwad Avinash G. Keskar Varun Tiwari NC Shivaprakash Electronics and Communication Department Visvesvaraya National Institute of Technology (VNIT) Nagpur India Department of Instrumentation and Applied Physics Indian Institute of Science (IISc) C V Raman Ave Bengaluru India

ISBN: (纸本)9781538674765

The wearable technology carries sufficient potential to incorporate smartness into working of the military workforces like the Military Control Unit, Medical Responders, Backup Unit and War Strategist. The proposed work focuses on real-time soldier activity detection, which is essential for the operation of the smart military suit. The customized Artificial Neural Network (ANN) IP core is developed for the soldier activity classification, which is an integral component of suit gateway design. The multilayer perceptron (7-5-4) classification algorithm is implemented on the low-cost (99$) FPGA evaluation platform by using Xilinx vivado and system generator development tools. The training (70%) and testing (30%) of this ANN design is performed on the UCI human activity dataset. The LabVIEW GUI and IP test design completed the hardware testing of this IP. The presented ANN IP is able to achieve 98.5% classification accuracy by utilizing minimal FPGA (Artix-7 xc7a35t) resources. The implemented ANN design requires only 285 nanoseconds for a classification and consumes 103 milliwatts of dynamic power. The system's accuracy at different development levels is also studied in this work.

关键词： Smart military suit Soldier activity detection Artificial neural network Smart sensor gateway Network centric warfare field programmable gate array field programmable gate arrays Artificial neural networks Soldiers Activity Detection Military Personnel Hardware Test brightness EIS IMPLEMENTATION PLANS Bayesian classifier Sorting algorithm

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The Study on Real-time Data Processing Based on CCD Scanning and Detecting Device on FPGA

The Study on Real-time Data Processing Based on CCD Scanning...

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2009 IEEE International Conference on Intelligent Computing and Intelligent Systems(ICIS2009)

作者： XU Guo-sheng I.Information and Control Engineering College Weifang University 261061 Weifang China

To solve the crossing-linkable polyethylene （XLPE） insulation compound purity evaluation problem,a high speed scanning measurement system was designed according to *** the updated information technology and advanced electronic devices,it is possible to develop a new inspecting technology for sorting,checking and evaluating material quality,by which defects microscopic images can be real-time recorded,processed and *** experimental results demonstrated that defects within 70μm～1000μm were inspected effectively by the CCD scanning defects inspection instrument,and Good agreement was shown between defects images real-time reconstructed and optical microscopic images not only in shape but also in gray.

关键词： data processing defects inspection field programmable gate array charge coupled device

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Multiple parallel branch with folding architecture for multichannel filtered-x least mean square algorithm

Multiple parallel branch with folding architecture for multi...

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IEEE International Conference on Acoustics, Speech and Signal Processing

作者： Dongyuan Shi Jianjun He Chuang Shi Tatsuya Murao Woon-Seng Gan Digital Signal Processing Lab School of Electrical & Electronic Engineering Nanyang Technological University Singapore

ISBN: (纸本)9781509041183

Multichannel active noise control (MCANC) systems are commonly used in acoustic noise or vibration control, such as large-dimension ventilation ducts, open windows and mechanical structures. However, its computational load far exceeds the capabilities of digital signal processors (DSPs) and microcontrollers. Even the field programmable gate array (FPGA) cannot straightforwardly cope with the exponential increase in the computation load of MCANC systems. A novel architecture, called the multiple parallel branch with folding, is proposed for the J × J × M (J reference microphones, J secondary sources and Merror microphones) MCANC implementation with the floating-point arithmetic. This architecture addresses the tradeoff between throughput and hardware resource consumption by using parallel execution and folding. The proposed architecture is validated in an experimental setup that carries out a 4 × 4 × 4 multichannel filtered-x least mean square (FxLMS) algorithm achieving the sampling rate and throughput of 24 KHz and 18.4 Mbps, respectively.

关键词： Filtered-x least mean square algorithm multichannel active noise control field programmable gate array field programmable gate arrays Active noise control Least mean square algorithm FOLDING Throughput Building construction ARCHITECTURE iodine MULTICHANNEL parallel execution Acoustic noise Microphone Device Component sampling rate

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The safety review and formal verification on FPGA

The safety review and formal verification on FPGA

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作者： ZUO Jiaxu YU Wenzhuo LI Sen ZENG Hai ZHANG Chunming Department of Nuclear and Radiation Safety Research Nuclear and Radiation Safety Center MEP Special Risk Insurance Division PICC Property and Casualty Company Limited Engineering Center State Nuclear Power Automation System Engineering Corp

The FPGA technology is researched and developed in the reactor protection system. The FPGA system is developed by the software tools, and applications in the hardware. The safety review points of FPGA from NRC are introduced and some key points of FPGA's safety are discussed. The verification and validation, quality assurance and software tools seem more important for FPGA development. There are some disadvantages in the simulations of FPGA and the formal verification could be the usefully supplement for those disadvantages. Base on the SVA method in model checking of formal verification, the overpower ΔT trip chips were verified. And some bugs in ALU multiply modular were checked out and updated. Base on the SVA method, the formal verification makes the design and verification to take attentions on the function definition.

关键词： nuclear safety review simulation verification formal verification field programmable gate array

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Fully Digital 1-D, 2-D and 3-D Multiscroll Chaos as Hardware Pseudo Random Number Generators

Fully Digital 1-D, 2-D and 3-D Multiscroll Chaos as Hardware...

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IEEE International Midwest Symposium on Circuits and Systems

作者： Abhinav S. Mansingka Ahmed G. Radwan Khaled N. Salama Electrical Engineering Program King Abdullah University of Science and Technology Department of Engineering Mathematics Faculty of Engineering Cairo University

ISBN: (纸本)9781467325264

This paper introduces the first fully digital implementation of 1-D, 2-D and 3-D multiscroll chaos using the sawtooth nonlinearity in a 3rd order ODE with the Euler approximation. Systems indicate chaotic behaviour through phase space boundedness and positive Lyapunov exponent. Low-significance bits form a PRNG and pass all tests in the NIST SP. 800-22 suite without post-processing. Real-time control of the number of scrolls allows distinct output streams with 2-D and 3-D multiscroll chaos enabling greater controllability. The proposed PRNGs are experimentally verified on a Xilinx Virtex 4 FPGA with logic utilization less than 1.25%, throughput up to 5.25 Gbits/s and up to 512 distinct output streams with low cross-correlation.

关键词： Chaos Nonlinear systems Digital circuits Pseudo random number generator field programmable gate array

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An area-efficient low-power SCM topology for high performance network-on Chip (NoC) architecture using an optimized routing design

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2019年第14期31卷 e4760-e4760页

作者： Poovendran, R. Sumathi, S. Adhiyamaan Coll Engn Dept ECE Hosur India

The incorporation of network-on-Chip with communication delivers a strengthening solution to the rising complexity and problems in system-on-chip. Here, mesh topology is shortly connected, utilizing the symmetric properties of the network, and is introduced. In addition, 4x4-Router Architecture-Carry Select Adder (4x4-RA-CSLA) method is proposed to improve the function of the Router Architecture (RA) in the network. These features make the system achieve efficient architecture in terms of lower area and power for the interconnection of network scenarios. This new architecture is debugged using ModelSim with Verilog code. The experimental result shows improvement in area and power.

关键词： application specified integrated chip diametrical mesh field programmable gate array network-on-chip 4x4-Router Architecture-Carry Select Adder

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Design of a Multichannel Time Interval Measurement Interface Box

Design of a Multichannel Time Interval Measurement Interface...

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作者： Don, M. L Pugh, K. E Kline, B. J Hallameyer, J. M CCDC Army Research Laboratory Aberdeen Proving Ground United States

Precise time interval measurement is required for a number of applications including clock stability analysis, time-of-flight measurements, and particle physics. Commercial time interval measurement devices can achieve picosecond resolution but are expensive, especially for multichannel applications. In previous research, the US Army Combat Capabilities Development Command Army Research Laboratory demonstrated 10-ns resolution on 10 channels using a low-cost field-programmable gate array (FPGA) suitable for pulse-per-second monitoring. This technical note details the design of an interface box for this FPGA device, enabling practical time interval measurement with a variety of input signals. The purpose of this note is twofold: 1) to document the interface box to allow for easy use and future modifications and 2) to provide a reference to facilitate the construction of other interface units, including design advice and lessons learned.

关键词： field programmable gate array Time intervals Measurement Monitoring Time interval measurement field-programmable gate array Pulse per second Test and measurement Electronic interface

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