The proposed paper deals with Hardware-In-the-Loop (HIL) validation of a 3-phase PWM boost rectifier controller. This validation has been made using field programmable gate array (FPGA) target. The development of the ...
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ISBN:
(纸本)9781479902255
The proposed paper deals with Hardware-In-the-Loop (HIL) validation of a 3-phase PWM boost rectifier controller. This validation has been made using field programmable gate array (FPGA) target. The development of the Real-Time Emulator (RTE) of the power system is firstly discussed. All voltage sources from the grid, filters, power switches and the load real-time models are implemented in hardware using a Xilinx Spartan-6 FPGA device. As for the controller, a PI-based strategy has been chosen to control the DC-link voltage and a Hysteresis-based one for the control of 3-phase line currents. This controller has been implemented in software using the embedded Cortex-M3 processor of SmartFusion FPGA from MicroSemi. Real-time HIL simulation results, as well as offline simulation results are presented and compared.
We present an area efficient Time to Digital Converter (TDC) based on Vernier Principle yielding a high resolution of nearly 5ps. The TDC architecture reported in this paper uses Nutt Interpolation method i.e. compris...
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ISBN:
(纸本)9781467362429
We present an area efficient Time to Digital Converter (TDC) based on Vernier Principle yielding a high resolution of nearly 5ps. The TDC architecture reported in this paper uses Nutt Interpolation method i.e. comprises of coarse measurement using system clock and two controllable ring oscillators for fine measurement. Ring oscillators used in this work are identical and designed using fast carry logic. The reported improved resolution is attributed to the difference in their frequencies. The novel technique of obtaining difference in their period reduces manual efforts of designer. Two main features of this work are prototyping on a low-cost general purpose FPGA and new low cost verification methodology.
The wearable technology carries sufficient potential to incorporate smartness into working of the military workforces like the Military Control Unit, Medical Responders, Backup Unit and War Strategist. The proposed wo...
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ISBN:
(纸本)9781538674765
The wearable technology carries sufficient potential to incorporate smartness into working of the military workforces like the Military Control Unit, Medical Responders, Backup Unit and War Strategist. The proposed work focuses on real-time soldier activity detection, which is essential for the operation of the smart military suit. The customized Artificial Neural Network (ANN) IP core is developed for the soldier activity classification, which is an integral component of suit gateway design. The multilayer perceptron (7-5-4) classification algorithm is implemented on the low-cost (99$) FPGA evaluation platform by using Xilinx vivado and system generator development tools. The training (70%) and testing (30%) of this ANN design is performed on the UCI human activity dataset. The LabVIEW GUI and IP test design completed the hardware testing of this IP. The presented ANN IP is able to achieve 98.5% classification accuracy by utilizing minimal FPGA (Artix-7 xc7a35t) resources. The implemented ANN design requires only 285 nanoseconds for a classification and consumes 103 milliwatts of dynamic power. The system's accuracy at different development levels is also studied in this work.
To solve the crossing-linkable polyethylene (XLPE) insulation compound purity evaluation problem,a high speed scanning measurement system was designed according to *** the updated information technology and advanced...
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To solve the crossing-linkable polyethylene (XLPE) insulation compound purity evaluation problem,a high speed scanning measurement system was designed according to *** the updated information technology and advanced electronic devices,it is possible to develop a new inspecting technology for sorting,checking and evaluating material quality,by which defects microscopic images can be real-time recorded,processed and *** experimental results demonstrated that defects within 70μm~1000μm were inspected effectively by the CCD scanning defects inspection instrument,and Good agreement was shown between defects images real-time reconstructed and optical microscopic images not only in shape but also in gray.
Multichannel active noise control (MCANC) systems are commonly used in acoustic noise or vibration control, such as large-dimension ventilation ducts, open windows and mechanical structures. However, its computational...
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ISBN:
(纸本)9781509041183
Multichannel active noise control (MCANC) systems are commonly used in acoustic noise or vibration control, such as large-dimension ventilation ducts, open windows and mechanical structures. However, its computational load far exceeds the capabilities of digital signal processors (DSPs) and microcontrollers. Even the field programmable gate array (FPGA) cannot straightforwardly cope with the exponential increase in the computation load of MCANC systems. A novel architecture, called the multiple parallel branch with folding, is proposed for the J × J × M (J reference microphones, J secondary sources and Merror microphones) MCANC implementation with the floating-point arithmetic. This architecture addresses the tradeoff between throughput and hardware resource consumption by using parallel execution and folding. The proposed architecture is validated in an experimental setup that carries out a 4 × 4 × 4 multichannel filtered-x least mean square (FxLMS) algorithm achieving the sampling rate and throughput of 24 KHz and 18.4 Mbps, respectively.
The FPGA technology is researched and developed in the reactor protection system. The FPGA system is developed by the software tools, and applications in the hardware. The safety review points of FPGA from NRC are int...
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The FPGA technology is researched and developed in the reactor protection system. The FPGA system is developed by the software tools, and applications in the hardware. The safety review points of FPGA from NRC are introduced and some key points of FPGA's safety are discussed. The verification and validation, quality assurance and software tools seem more important for FPGA development. There are some disadvantages in the simulations of FPGA and the formal verification could be the usefully supplement for those disadvantages. Base on the SVA method in model checking of formal verification, the overpower ΔT trip chips were verified. And some bugs in ALU multiply modular were checked out and updated. Base on the SVA method, the formal verification makes the design and verification to take attentions on the function definition.
This paper introduces the first fully digital implementation of 1-D, 2-D and 3-D multiscroll chaos using the sawtooth nonlinearity in a 3rd order ODE with the Euler approximation. Systems indicate chaotic behaviour th...
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ISBN:
(纸本)9781467325264
This paper introduces the first fully digital implementation of 1-D, 2-D and 3-D multiscroll chaos using the sawtooth nonlinearity in a 3rd order ODE with the Euler approximation. Systems indicate chaotic behaviour through phase space boundedness and positive Lyapunov exponent. Low-significance bits form a PRNG and pass all tests in the NIST SP. 800-22 suite without post-processing. Real-time control of the number of scrolls allows distinct output streams with 2-D and 3-D multiscroll chaos enabling greater controllability. The proposed PRNGs are experimentally verified on a Xilinx Virtex 4 FPGA with logic utilization less than 1.25%, throughput up to 5.25 Gbits/s and up to 512 distinct output streams with low cross-correlation.
The incorporation of network-on-Chip with communication delivers a strengthening solution to the rising complexity and problems in system-on-chip. Here, mesh topology is shortly connected, utilizing the symmetric prop...
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The incorporation of network-on-Chip with communication delivers a strengthening solution to the rising complexity and problems in system-on-chip. Here, mesh topology is shortly connected, utilizing the symmetric properties of the network, and is introduced. In addition, 4x4-Router Architecture-Carry Select Adder (4x4-RA-CSLA) method is proposed to improve the function of the Router Architecture (RA) in the network. These features make the system achieve efficient architecture in terms of lower area and power for the interconnection of network scenarios. This new architecture is debugged using ModelSim with Verilog code. The experimental result shows improvement in area and power.
Precise time interval measurement is required for a number of applications including clock stability analysis, time-of-flight measurements, and particle physics. Commercial time interval measurement devices can achiev...
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Precise time interval measurement is required for a number of applications including clock stability analysis, time-of-flight measurements, and particle physics. Commercial time interval measurement devices can achieve picosecond resolution but are expensive, especially for multichannel applications. In previous research, the US Army Combat Capabilities Development Command Army Research Laboratory demonstrated 10-ns resolution on 10 channels using a low-cost field-programmablegatearray (FPGA) suitable for pulse-per-second monitoring. This technical note details the design of an interface box for this FPGA device, enabling practical time interval measurement with a variety of input signals. The purpose of this note is twofold: 1) to document the interface box to allow for easy use and future modifications and 2) to provide a reference to facilitate the construction of other interface units, including design advice and lessons learned.
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