This paper presents a new solution for processing the pulses from an optical encoder attached to a motor shaft, and deriving the rotational speed information. An adaptive method allows the evaluation of the motor rota...
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This paper presents a new solution for processing the pulses from an optical encoder attached to a motor shaft, and deriving the rotational speed information. An adaptive method allows the evaluation of the motor rotational speed with very good accuracy even at very low speeds, The adaptation also of the sampling period, according to the instant rotational speed, results in better response times at medium or high rotational speeds. The measurement accuracy at low speeds using the proposed method is improved, compared to currently known methods. Another significant advantage of using the proposed circuit is that it can be implemented in specific hardware, thus, reserving the full computational power of the controlling digital signal processor (DSP) for high-level control tasks and for future software expansions.
We present a new technique for testing field programmable gate arrays (FPGA's) based on look-up tables (LUT's). We consider a generalized structure for the basic FPGA logic element (cell);it includes devices s...
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We present a new technique for testing field programmable gate arrays (FPGA's) based on look-up tables (LUT's). We consider a generalized structure for the basic FPGA logic element (cell);it includes devices such as LUT's, sequential elements (flip-flops), multiplexers and control circuitry. We use a hybrid fault model for these devices. The model is based on a physical as well as a behavioral characterization. This permits detection of all single faults (either stuck-at or functional) and some multiple faults using repeated FPGA reprogramming. We show that different arrangements of disjoint one-dimensional (1-D) cell arrays with cascaded horizontal connections and common vertical input lines provide a good logic testing regimen. The testing time is independent of the number of cells in the array (C-testability), We define new conditions for C-testability of programmable/reconfigurable arrays. These conditions do not suffer from limited I/O pins. Cell configuration affects the controllability/observability of the iterative array. We apply the approach to various Xilinx FPGA families and compare it to prior work.
Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gatearray, and field programmable gate array (FPGA). Although nondeterministic algorithms such as Simulated Annealing ...
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Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gatearray, and field programmable gate array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) were successful in solving this problem, they are known to be slow. In this paper, a neural network algorithm is proposed that produces solutions as good as SA in substantially less time. This algorithm is based on Mean field Annealing (MFA) technique, which was successfully applied to various combinatorial optimization problems. A MFA formulation for the cell placement problem is derived which can easily be applied to all VLSI design styles. To demonstrate that the proposed algorithm is applicable in practice, a detailed formulation for the FPGA design style is derived, and the layouts of several benchmark circuits are generated. The performance of the proposed cell placement algorithm is evaluated in comparison with commercial automated circuit design software Xilinx Automatic Place and Route (APR) which uses SA technique. Performance evaluation is conducted using ACM/SIGDA Design Automation benchmark circuits. Experimental results indicate that the proposed MFA algorithm produces comparable results with APR. However, MFA is almost 20 times faster than APR on the average. (C) 1998 Elsevier Science Ltd. All rights reserved.
Network flow is an excellent approach to finding min-cuts because of the celebrated max-how min-cut theorem. For a long time, however, it was perceived as computationally expensive and deemed impractical for circuit p...
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Network flow is an excellent approach to finding min-cuts because of the celebrated max-how min-cut theorem. For a long time, however, it was perceived as computationally expensive and deemed impractical for circuit partitioning, Recently, the algorithm FBB [1], [2] successfully applied network flow to two-way balanced partitioning. It for the first time demonstrated that network flow was a viable approach to circuit partitioning. In this paper, we present FBB-MW, which is an extension of FEB, to solve the problem of multiway partitioning with area and pin constraints. Experimental results show that FBB-MW outperforms previous approaches for multiple field programmable gate array partitioning. In particular, although FBB-MW does not employ logic replication and logic resynthesis, it still outperforms [5] and [6], which allow replication and resynthesis for optimization.
The paper presents a hardware implementation of algorithms based on the Hough transform (HT) for real-time straight line detection. In particular, the basic HT on the edge points (EHT) and the Gradient-Weighted Hough ...
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The paper presents a hardware implementation of algorithms based on the Hough transform (HT) for real-time straight line detection. In particular, the basic HT on the edge points (EHT) and the Gradient-Weighted Hough transform (GWHT) for gray-level images are analyzed in detail and implemented on a pipelined architecture using field programmable gate arrays (FPGA). Algorithms execution times are compared with other hardware and software based systems in order to assess the efficiency of the presented approach. The paper shows how the achievable performance can meet the real-time requirements of an industrial inspection application. (C) 1998 Elsevier Science B.V. All rights reserved.
A real-time, VanderLugt-type optical correlator with a single SLM has been developed. A field programmable gate array was used to capture and process images obtained from a CCD camera at a rate of 60 video fields per ...
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ISBN:
(纸本)0819428353
A real-time, VanderLugt-type optical correlator with a single SLM has been developed. A field programmable gate array was used to capture and process images obtained from a CCD camera at a rate of 60 video fields per second. During both enrollment and verification, a finger slides over a glass prism and is input to the system via the frustration of total internal reflection. An auto-enrollment procedure captures the optimal image during each slide. An optimal composite filter is implemented. The correlation detection process comprises real-time tracking of the correlation peak while the finger is sliding, and a decision process based on projective decision boundaries. Real-life tests yielded a false rejection rate of 1% and a false acceptance rate of 0.2%.
To develop a cost-effective re-configurable DSP engine, it has been proposed to upgrade an existing custom designed TMS320C40 based multi-processing architecture with run-time configuration capabilities. The upgrade w...
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ISBN:
(纸本)0819429872
To develop a cost-effective re-configurable DSP engine, it has been proposed to upgrade an existing custom designed TMS320C40 based multi-processing architecture with run-time configuration capabilities. The upgrade will consist of four Xilinx XC6200 series field programmable gate arrays (FPGAs) which will enable concurrent algorithm structures to be efficiently mapped onto the system. Furthermore, the upgraded architecture will provide a platform for the development of adaptive routing structures, self-configuration techniques and facilitate the merging of instruction and hardware based parallelism.
This paper introduces a coarse-grained FPGA architecture that is specialized for high-performance Finite Impulse Response (FIR) filtering. The proposed architecture provides the flexibility of a DSP processor with per...
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ISBN:
(纸本)9780897919784
This paper introduces a coarse-grained FPGA architecture that is specialized for high-performance Finite Impulse Response (FIR) filtering. The proposed architecture provides the flexibility of a DSP processor with performance and area efficiency similar to that of a custom ASIC design, while allowing all of the basic FIR design parameters, including coefficient precision, to be configured. Previous research has already shown that FPGAs can provide a high-performance alternative to DSP processors. Experimental comparisons in this paper show that the performance and area efficiency of the proposed architecture is similar to that of custom approaches across a wide range of filter sizes and configurations.
field programmable gate arrays (FPGA's) suffer from lower density and lower performance than conventional gatearrays, Hierarchical interconnection structures for field programmable gate arrays are proposed, They ...
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field programmable gate arrays (FPGA's) suffer from lower density and lower performance than conventional gatearrays, Hierarchical interconnection structures for field programmable gate arrays are proposed, They help overcome these problems, Logic blocks in a held programmablegatearray are grouped into clusters, Clusters are then recursively grouped together, To obtain the optimal hierarchical structure with high performance and high density, various hierarchical structures with the same routability are discussed, The held programmablegatearrays with new architecture can be efficiently configured with existing computer aided design algorithms, The k-way min-cut algorithm is applicable to the placement step in the implementation. Global routing paths in a field programmable gate array can be obtained easily. The placement and global routing steps can be performed simultaneously, Experiments on benchmark circuits show that density and performance are significantly improved.
The authors present a systolic design for a simple GA mechanism which provides high throughput and unidirectional pipelining by exploiting the inherent parallelism in the genetic operators. The design computes in O(N ...
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The authors present a systolic design for a simple GA mechanism which provides high throughput and unidirectional pipelining by exploiting the inherent parallelism in the genetic operators. The design computes in O(N + G) time steps using O(N-2) cells where N is the population size and G is the chromosome length. The area of the device is independent of the chromosome length and so can be easily scaled by replicating the arrays or by employing fine-grain migration. The array is generic in the sense that it does not rely on the fitness function and can be used as an accelerator for any GA application using uniform crossover between pairs of chromosomes. The design can also be used in hybrid systems as an complement existing designs and fitness function acceleration and island-style population management.
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