The purpose of this paper is to analyze and design the controllers of power factor corrector for universal applications. And present its implementation using field programmable gate array. For the controller design, t...
详细信息
ISBN:
(纸本)9781467303408;9781467303422
The purpose of this paper is to analyze and design the controllers of power factor corrector for universal applications. And present its implementation using field programmable gate array. For the controller design, the bandwidth of voltage loop as the input voltage changes for PFC with and without input voltage feedforward will be analyzed. It will be shown that for the PFC without input voltage feedforward, the bandwidth of voltage loop varies as the input voltage changes. And the bandwidth of voltage loop for low line input is significantly reduced as it is designed based upon the high line input model. In contrast, the bandwidth of voltage loop of PFC for high line input is increased as it is designed based upon the low line input model. For the PFC with feedforward input voltage, the bandwidth of voltage loop retains constant for both low line and high line inputs and therefore no additional gains are required for universal input applications. This analysis provides a guideline for the design of PFC for universal input applications. Moreover, to fully take the advantages of digital control, an FPGA is used for the realization of digital-controlled PFC for universal input applications. Experimental results derived from an FPGA-based digital-controlled universal PFC are presented to fully support the presented PFC.
A new versatile and modular hardware platform for distributed real-time simulation is presented in this paper. The system is aimed at large-scale simulation on system level but with the ability to include simulation o...
详细信息
ISBN:
(纸本)9781467319706
A new versatile and modular hardware platform for distributed real-time simulation is presented in this paper. The system is aimed at large-scale simulation on system level but with the ability to include simulation of switched power electronics for hardware-in-the-loop components connected to single nodes of the simulated system. High complexity is possible through parallelization on the system level to account for large numbers of simulated components. Low time-steps are possible through parallelization on chip-level to offer parallel computation aided by field-programmablegatearray devices. Processor boards handle the simulation of subcomponents and are interconnected to build the large-scale systems. Hardware-in-the-loop connection is provided in a flexible yet powerful way by dedicated interface boards connected to a controlling processor board. A backplane with active routing capability is used to handle low-latency communication throughout the simulation platform. A small-scale system simulating an example buck converter with a time-step of 1 μs is presented to show the functionality of the simulation platform.
This paper describes the implementation of a digital compensation scheme, called CSAD, for correcting the effects of wideband gain and phase imbalances in dual-branch OFDM receivers. The proposed scheme is implemented...
详细信息
This paper describes the implementation of a digital compensation scheme, called CSAD, for correcting the effects of wideband gain and phase imbalances in dual-branch OFDM receivers. The proposed scheme is implemented on a Xilinx Virtex-4 field programmable gate array (FPGA). The flexible architecture of the implementation makes it readily adaptable for different broadband applications, such as DVB-T/H, WLAN, and WiMAX. The proposed correction scheme is resilient against multipath fading and frequency offset. When applied to DVB-T, it is shown that an 11-bit arithmetic precision is sufficient to achieve the required BER of 2×10{sup}(-4) at an SNR of 16.5 dB. Using this bit-precision, the implementation consumes 1686 Virtex-4 slices equivalent to about 42600 gates.
Discrete wavelet transform (DWT) has shown great performance in digital image compression and denoising applications. It is the transformation used for source encoding in JPEG2000 still image compression standard and ...
详细信息
ISBN:
(纸本)9781467311564
Discrete wavelet transform (DWT) has shown great performance in digital image compression and denoising applications. It is the transformation used for source encoding in JPEG2000 still image compression standard and FBI wavelet scalar quantization. DWT is capable of fast image compression at less area and low power consumption. This paper presents 4-tap orthogonal DWT based on the residue number system. Hardware complexity reduction and design improvement are achieved by employing RNS for arithmetic operations and LUT sharing between low pass and high pass filters. The RNS based DWT is simulated and implemented on the Xilinx FPGA to verify the functionality and efficiency of the design.
Sphere Decoder (SD) is widely being used in Multiple Input Multiple Output (MIMO) systems to reduce the complexity of the system while obtaining near Maximum Likelihood (ML) performance. The complexity of the system i...
详细信息
ISBN:
(纸本)9781479921041
Sphere Decoder (SD) is widely being used in Multiple Input Multiple Output (MIMO) systems to reduce the complexity of the system while obtaining near Maximum Likelihood (ML) performance. The complexity of the system increases with the increase in antenna configuration or the constellation size. Some pre-processing is a fundamental prerequisite in iterative detectors to reduce the system complexity by focusing the received signal energy to reduce the effect of inter-symbol interference. The QR Decomposition (QRD) of communication channel matrices in the pre-processor stage is an important issue to ensure good performance of the subsequent steps of decoding thus a QRD) is commonly used in many MIMO detection algorithms. A sorted QR decomposition (SQRD) is an advanced algorithm that improves the performance of MIMO detection. In this paper the efficiency of QRD and SQRD methods in terms of computational complexity, error rate performance and the FPGA resources utilized is presented. The main contribution of this work is a comparison of hardware implementations of the QRD and SQRD system. QRD for 4x4 MIMO system is implemented on various target FPGA platforms to compare their area utilization.
This paper introduces a new and an improved controlled start-up stochastic (CSS) architecture of Low-Density Parity-Check (LDPC) decoding, to implement fully parallel FPGA-based decoders. The developed architecture us...
详细信息
ISBN:
(纸本)9781467366748
This paper introduces a new and an improved controlled start-up stochastic (CSS) architecture of Low-Density Parity-Check (LDPC) decoding, to implement fully parallel FPGA-based decoders. The developed architecture uses a new variable nodes structure with larger internal memory lengths, to improve the convergence, without significant additional field programmable gate array (FPGA) resource. To validate the advantage of the proposed approach, a medium (1024, 512) and short (200, 100) codes are implemented. The results of Xilinx Virtex-6 VLX240T FPGA shoes that the variable node internal memories lengths can be increased from 2-bit, used in CSS and Delayed Stochastic (DS) decoders, to 64-bit without addition resource.
The orthogonal code is one of the error correction and detection codes and it can detect errors and correct corrupted data. An n-bit orthogonal code would haven/2 1's and n/2 0's and these properties can effec...
详细信息
ISBN:
(纸本)9781538619605
The orthogonal code is one of the error correction and detection codes and it can detect errors and correct corrupted data. An n-bit orthogonal code would haven/2 1's and n/2 0's and these properties can effectively participate in detecting and correcting the errors. Thus this article presents a new methodology to enable error detection capabilities using the orthogonal code. The orthogonal codes has been verified experimentally and proved their physical reliability by implementing on field programmable gate arrays (FPGA). The experimental results shows that the proposed orthogonal code can improve the detection capabilities of the transmitted informationup to 99.9% and also it corrects errors up to (n/2 - 1) bits in the received information with bandwidth efficiency.
Logic obfuscation is widely followed in intellectual property cores and chip designs as hardware protection mechanism against design security threats such as reverse engineering (RE), piracy, cloning, overbuilding, et...
详细信息
ISBN:
(纸本)9781467393393
Logic obfuscation is widely followed in intellectual property cores and chip designs as hardware protection mechanism against design security threats such as reverse engineering (RE), piracy, cloning, overbuilding, etc. In general, sequential obfuscation has two modes of operation such as obfuscated and functional modes. Finite state machines (FSM) are being used to implement the mode control. When a specific sequence of input vectors is applied during power up for user authentication, the circuit will enter into functional mode. Otherwise, FSM remains in obfuscated mode and do not perform the intended functionality. In general, hardware obfuscation technique is applicable to all programmable logic devices. However, we applied the structural modification based netlist obfuscation methodology to field programmable gate array devices. The software implementation of sequential obfuscation is performed for a set of ISCAS'89 benchmark circuits using Libero IDE v9.1 on Actel device. As simulation/structural analysis are the conventional methods to perform RE, we aimed to achieve a high percentage of simulation/structural mismatch during RE. We presented two scenarios of obfuscation: 1) For better structural mismatch during RE, insertion of obfuscation cells at different numbers of high fanout (HF) nets with minimum initialization sequence length (L). As per the designer's area constraint, the total number of nets to be obfuscated is chosen. 2) For better functional simulation mismatch during RE, FSM with different L values is included in the design with a minimum number of obfuscation cells. The initialization sequence length is decided concerning the system clock cycle (i.e. delay constraint). Based on the control signals derived from FSM, the values at HF obfuscated nets are decided. That is, the circuit executes the required functionality only in the functional mode. Hence, the simulation/structural RE complexity of PLDs is improved. This paper discusses the simulation
This work details the capabilities of a major new release of the Verilog-to-Routing (VTR) open-source FPGA CAD tool flow. Enhancements include generalizations of VTR’s architecture modeling language and optimizers to...
详细信息
This work details the capabilities of a major new release of the Verilog-to-Routing (VTR) open-source FPGA CAD tool flow. Enhancements include generalizations of VTR’s architecture modeling language and optimizers to enable a more diverse set of programmable routing fabrics, FPGAs with embedded hard Networks-on-Chip (NoCs) and three-dimensional FPGA systems that leverage stacked silicon integration. The new Parmys logic synthesis flow improves language coverage and result quality, and the physical implementation flow includes a more efficient placement engine, floorplanning constraints to guide placement, the ability to perform single-stage (flat) routing to improve quality, and parallel routing algorithms to reduce CPU time. This release also includes new architecture captures of recent commercial devices (Xilinx’s 7-series and Altera’s Stratix 10) and new benchmark suites (Titanium25 and Hermes) to aid FPGA architecture investigation. Verilog language coverage is greatly improved with the new Parmys logic synthesis flow, enabling more designs to be used with VTR. Finally, the placement and routing engines have beeen sped up by 4\(\times\) and 2.2\(\times\) vs. VTR 8, respectively, leading to an overall physical implementation flow CPU time reduction of 48% with better result quality on average compared to VTR 8.
暂无评论