Artificial Neural Network (ANN) algorithms are applicable in a variety of roles for image processing in Infrared Search and Track (IRST) systems. Achieving a high throughput is a key objective in developing ANNs for p...
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ISBN:
(纸本)0819424846
Artificial Neural Network (ANN) algorithms are applicable in a variety of roles for image processing in Infrared Search and Track (IRST) systems. Achieving a high throughput is a key objective in developing ANNs for processing large numbers of pixels at high frame rates. Previous work has investigated the use of a neural core supported by configurable logic to achieve a versatile technology applicable to a variety of systems. The implementation of Multi-Layer Perceptron (MLP) ANNs, using field programmable gate array (FPGA) technology to ensure upgradability and reconfigurability, is the focus of this research. Approximations to the MLP algorithms are needed to ensure that a high throughput can be achieved with a sufficiently low gate count.
With the current rapid growth in multimedia technology, there is an imminent need for efficient techniques to search and query large image databases. Because of their unique and peculiar needs, image databases cannot ...
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With the current rapid growth in multimedia technology, there is an imminent need for efficient techniques to search and query large image databases. Because of their unique and peculiar needs, image databases cannot be treated in a similar fashion to other types of digital libraries. The contextual dependencies present in images, and the complex nature of two-dimensional image data make the representation issues more difficult for image databases. An invariant representation of an image is still an open research issue. For these reasons, it is difficult to find a universal content-based retrieval technique. Current approaches based on shape, texture, and color for indexing image databases have met with limited success. Further, these techniques have not been adequately tested in the presence of noise and distortions. A given application domain offers stronger constraints for improving the retrieval performance. Fingerprint databases are characterized by their large size as well as noisy and distorted query images. Distortions are very common in fingerprint images due to elasticity of the skin. In this paper, a method of indexing large fingerprint image databases is presented. The approach integrates a number of domain-specific high-level features such as pattern class and ridge density at higher levels of the search. At the lowest level, it incorporates elastic structural feature-based matching for indexing the database. With a multilevel indexing approach, we have been able to reduce the search space. The search engine has also been implemented on Splash 2-a field programmable gate array (FPGA)-based array processor to obtain near-ASIC level speed of matching. Our approach has been tested on a locally collected test data and on NIST-9, a large fingerprint database available in the public domain.
This paper describes the architecture of the MIX system that was designed to investigate the trade-off between the use of reconfigurable and fixed logic. The calculation of the dot-product of two vectors of 32 bit flo...
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ISBN:
(纸本)0818675489
This paper describes the architecture of the MIX system that was designed to investigate the trade-off between the use of reconfigurable and fixed logic. The calculation of the dot-product of two vectors of 32 bit floating point numbers, that forms the basis of array processing in may engineering applications, is used as the basic algorithm for the investigation. The results indicate that fixed logic is more suited for floating point units and memories while reconfigurable logic is useful for implementing control logic providing significant flexibility. It was also found that the additional delay in reconfigurable logic can effectively overlap with the operating time of the fixed logic subsystems. The advantage of reconfigurability of the control is therefore combined with the high bandwidth properties of the fixed logic.
Applications requiring variable-precision arithmetic often rely on software implementations because custom hardware is either unavailable or too costly to build. By using the flexibility of the Xilinx XC4010 field pro...
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Applications requiring variable-precision arithmetic often rely on software implementations because custom hardware is either unavailable or too costly to build. By using the flexibility of the Xilinx XC4010 field programmable gate arrays, we present a hardware implementation of square root that is easily tailored to any desired precision. Our design consists of three types of modules: a control logic module, a data path module to extend the precision in 4-bit increments, and an interface module to span multiple chips. Our data path design avoids the common problem of large fan-out delay in the critical path. Cycle time is independent of precision, and operation latency can be independent of interchip communication delays.
In the past three years a new type of programmable logic device has emerged. The programmablegatearray is a new approach to an old problem of trying to implement logic designs in an efficient manner. This thesis exp...
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In the past three years a new type of programmable logic device has emerged. The programmablegatearray is a new approach to an old problem of trying to implement logic designs in an efficient manner. This thesis explores the implementation of design using the field programmable gate array (FPGA). In particular, this thesis utilizes the XILINX development system tools to implement design into the XILINX Logic Cell array (LCA). This thesis begins by defining the characteristics of the LCA and then defines the characteristics of the Small Computer Systems Interface (SCSI) which is used as a design implementation example. The XILINX implementation method is then explored and a complete design implementation study is conducted on the design example. Both Mentor Graphics and Futurenet schematic capture tools are used for design entry. Following design implementation, backannotated design simulation is performed to study the effect of the LCA technology on design performance. The results of this thesis showed that designs implemented using this technology performed comparably to other implementation technologies. Additionally, this implementation method allows design to be completed in a significantly shorter time frame than previously possible.
Teoretická část této práce se zabývá koncepty a rozhraními využívanými pro programování mikrokontrolérů (MCU) a rekonfiguraci programovatelných hradlov&...
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Teoretická část této práce se zabývá koncepty a rozhraními využívanými pro programování mikrokontrolérů (MCU) a rekonfiguraci programovatelných hradlových polí (FPGA) s užším zaměřením na ty z nich, které jsou dostupné pro MCU Kinetis K60 a FPGA Spartan-6 v zapojení daném architekturou výukového kitu Minerva. Tyto znalosti jsou využity v praktické části popisující nasazení podpůrného firmware, patřícího do skupiny tzv. bootloaderů. Nakonec je popsána obslužná aplikace QDevKit3 pracující s tímto firmware, představující účinný a rychlý prostředek pro jednoduché naprogramování FLASH paměti daného MCU pomocí rozhraní USB.
Tato práce se věnuje návrhu, realizaci a testování zařízení, které provádí spektrální analýzu gama záření na základě vyhodnocování...
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Tato práce se věnuje návrhu, realizaci a testování zařízení, které provádí spektrální analýzu gama záření na základě vyhodnocování pulzů ze scintilačního detektoru. Ty jsou po zesílení zdigitalizovány a jejich další zpracování probíhá číslicově v hradlovém poli, což umožňuje snadnou případnou budoucí modifikaci funkce vyvinutého zařízení. Po úvodu do problematiky spektroskopie gama záření se zaměřením na jeho detekci se práce věnuje vývoji hardwaru multikanálového analyzátoru, jehož jednotlivé části jsou postupně rozebrány. Dále je popsán vývoj číslicového systému pro zpracování signálu v programovatelném hradlovém poli. Následuje rozbor firmwaru řídícího mikrokontroléru a textového protokolu pro ovládání zařízení. Na závěr jsou diskutovány výsledky práce zejména testovacího měření gama záření.
Cílem této práce je implementace digitálních decimačních filtrů do programovatelného hradlového pole. Součástí práce je také popis technologie MEMS včetně s...
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Cílem této práce je implementace digitálních decimačních filtrů do programovatelného hradlového pole. Součástí práce je také popis technologie MEMS včetně srovnání mikrofonů s technologií MEMS různých výrobců. Další část textu je také věnována sigma-delta modulaci. Stěžejní částí práce je ovšem návrh a implementace digitálních filtrů CIC a FIR pro zpracování signálu z digitálního mikrofonu, včetně simulací a ověření vlastností navržených filtrů v programu Matlab.
This work details the capabilities of a major new release of the Verilog-to-Routing (VTR) open-source FPGA CAD tool flow. Enhancements include generalizations of VTR’s architecture modeling language and optimizers to...
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This work details the capabilities of a major new release of the Verilog-to-Routing (VTR) open-source FPGA CAD tool flow. Enhancements include generalizations of VTR’s architecture modeling language and optimizers to enable a more diverse set of programmable routing fabrics, FPGAs with embedded hard Networks-on-Chip (NoCs) and three-dimensional FPGA systems that leverage stacked silicon integration. The new Parmys logic synthesis flow improves language coverage and result quality, and the physical implementation flow includes a more efficient placement engine, floorplanning constraints to guide placement, the ability to perform single-stage (flat) routing to improve quality, and parallel routing algorithms to reduce CPU time. This release also includes new architecture captures of recent commercial devices (Xilinx’s 7-series and Altera’s Stratix 10) and new benchmark suites (Titanium25 and Hermes) to aid FPGA architecture investigation. Verilog language coverage is greatly improved with the new Parmys logic synthesis flow, enabling more designs to be used with VTR. Finally, the placement and routing engines have beeen sped up by 4\(\times\) and 2.2\(\times\) vs. VTR 8, respectively, leading to an overall physical implementation flow CPU time reduction of 48% with better result quality on average compared to VTR 8.
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