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5th IEEE International Conference on Power Electronics and Drive Systems (PEDS 2003)

作者： Huang, SJ Sun, CH Lee, TS Natl Cheng Kung Univ Dept Elect Engn Tainan 70101 Taiwan

ISBN: (纸本)0780378857

A novel design of line-interactive uninterruptible power supplies is proposed in this paper. In the designated circuit, by utilizing single-stage power converter, the system can be operated either in the active power filter mode or in the voltage-stabilizing mode based on the operating state of mains power. When the system is operated at the active power filter mode, both the harmonic reduction and reactive power compensation can be achieved via a set of current feedback signals. When the system is operated at the voltage-stabilizing mode, by deeming the capacitor current as the control variable, the first-order current control method can be formulated such that the system stability is maintained while the speed response is significantly improved. With the aid of the FP GA in the digital design, it is found that the hardware circuit can be realized within a shorter time and the design cost can be also lowered down. This proposed system has been validated by theoretical analysis and experimental realization. Test results support the feasibility of the proposed approach for the application considered.

关键词： field programmable gate array line-interactive uninterruptible power supply

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A digital methodology integrating experimental and theoretical neuroscience 1

A digital methodology integrating experimental and theoretic...

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1st International IEEE/EMBS Conference on Neural Engineering

作者： Snider, RK Lukes, AJ Zhu, Y Miller, JP Montana State Univ Dept Elect & Comp Engn Bozeman MT 59717 USA

ISBN: (纸本)0780375793

A digital methodology integrating experimental and theoretical neuroscience is being developed by the creation of a reconfigurable on-line modeling platform (ROMP). The platform will perform real-time analysis of multi-channel data streams for data-driven neural simulations and modeling. The computational architecture is a distributed real-time system of modular design consisting of computational nodes that contain a floating-point digital signal processor (DSP) and a field programmable gate array (FPGA). Configuring the system as a multi-dimensional mesh will allow it to scale in order to process an arbitrary number of real-time data streams. The platform will be used to aid the discovery process where neural encoding schemes through which sensory information is represented and transmitted within a nervous system will be uncovered. The system will enable real-time decoding of neural information streams and it will allow neuronal models to be inserted in simple nervous systems. Allowing experimental perturbation of neural signals while in transit between peripheral and central processing stages will provide an unprecedented degree of interactive control in the analysis of neural function, and could lead to major insights into the biological basis of neural computation.

关键词： neural modeling simulations reconfigurable computing field programmable gate array FPGA real-time parallel computing digital signal processing DSP experimental theoretical computational neuroscience

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Digital frequency conversion technique in HDTV 3

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3rd Asia-Pacific Conference on Environmental Electromagnetics

作者： Ai, B Wang, Y Ge, JH Zhao, YN Xidian Univ Natl Key Lab Integrated Serv Networks Xian 710071 Peoples R China

ISBN: (纸本)7563508023

This paper makes a research on the fundamental principle of digital modulation and frequency conversion in broad band digital broadcasting-terrestrial TV ( BDB-T) system. Different from conventional down-conversion technique, this paper proposes a new digital down-conversion model utilizing Hilbert transform and a method eliminating the A/D DC offset in this model is also proposed. The correspondent FPGA hardware though testing process in HDTV prototype proves the efficiency and good performance of the model and the new method.

关键词： High Definition TV coded orthogonal frequency division multiplexing digital frequency conversion field programmable gate array

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The design and FPGA realization of the long PN code acquisition circuit based on digital matched-filter 5

The design and FPGA realization of the long PN code acquisit...

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5th International Conference on ASIC

作者： Tan, XH Yang, SZ Chongqing Univ Coll Commun Engn Chongqing 400044 Peoples R China

ISBN: (纸本)078037889X

In a Low-earth-orbit (LEO) satellite system the received signal will be characterized by low signal to noise, it requires a minimum spreading processing gain of 30dB. i.e., the PseudoNoise (PN) code length is 1023. However, the Application specific Integrated Circuit (ASIC) based on Digital Matched-filter (DMF) for PN code acquisition on the market can't support such a long PN code length. It is necessary to use field programmable gate array (FPGA) to design the long PN code acquisition circuit based on DMF for the so high spreading processing gain. In this paper, the PN code acquisition circuit based on DMF is analyzed. A new approach to PN code acquisition based on DMF, which can obtain high spread processing gain (30dB) while the cost of the hardivare is largely depressed, is presented. VDHL design, verification and FPGA realization of the DMF is accomplished. and main design results are also given.

关键词： integrated circuit design field programmable gate arrays pseudonoise codes digital filters matched filters FPGA PN code acquisition circuit digital matched-filter low-earth orbit satellite system pseudonoise code application specific integrated circuit ASIC field programmable gate array processing gain VHDL DMF 30 dB

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High resolution X-ray medical sequential image acquisition and processing system based on PCI interface

High resolution X-ray medical sequential image acquisition a...

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Conference on Applications of Digital Image Processing XXVI

作者： Lu, DM Chen, Q Gu, GH Nanjing Univ Sci & Technol Coll Elect Engn & Optoelect Technol Nanjing 210094 Peoples R China

ISBN: (纸本)0819450766

In the field of medical application, it is of great importance to adopt digital image processing technique. Based on the characteristics of medical image, we introduced the digital image processing method to the X-ray imaging system, and developed a high resolution x-ray medical sequential image acquisition and processing system that employs image enhancer and CCD. This system consists of three basic modules, namely sequential image acquisition, data transfer and system control, and image processing. Under the control of FPGA (field programmable gate array), images acquired by the front-end circuit are transmitted to a PC through high speed PCI bus, and then optimized by the image processing program. The software kits, which include PCI Device Driver and Image Processing Package, are developed with Visual C++ Language based on Windows OS. In this paper, we present a general introduction to the principle and the operating procedure of X-ray Sequential Image Acquisition and Processing System, with special emphasis on the key issues of the hardware design. In addition, the context, principle, status quo and the digitizing trend of X-ray Imaging are explained succinctly. Finally, the preliminary experimental results are shown to demonstrate that the system is capable of achieving high quality X-ray sequential images.

关键词： digital video signal processing PCI bus interface technique field programmable gate array medical X-ray imaging system

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field programmable gate array-based PCI interface for a coprocessor system

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MICROPROCESSORS AND MICROSYSTEMS 1999年第7期22卷 373-388页

作者： Kuusilinna, K Hämäläinen, T Saarinen, J Tampere Univ Technol Signal Proc Lab FIN-33101 Tampere Finland

This paper presents the design and implementation of a field programmable gate array (FPGA)-based PCI bus interface for a general purpose parallel neurocomputer, which is hosted by a personal computer. The basic background of the PCI bus and a detailed discussion of applicable FPGA design considerations are given. With FPGA, critical implementation factors are the realization of fast-enough state machines and efficient resource allocation. Emphasis is placed on presenting how to allocate resources efficiently from the VHDL hardware description language. Related to the overall implementation, PCI bus agent initialization and configuration from the operating system are considered. (C) 1999 Elsevier Science Ltd. All rights reserved.

关键词： PCI field programmable gate array VHDL synthesis

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An uncooled infrared sensor of dielectric bolometer mode using a new detection technique of operation bias voltage

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SENSORS AND ACTUATORS A-PHYSICAL 2002年 97-8卷 329-336页

作者： Noda, M Inoue, K Ogura, M Xu, HP Murakami, S Kishihara, K Okuyama, M Osaka Univ Grad Sch Engn Dept Phys Sci Area Mat & Device Phys Toyonaka Osaka 5608531 Japan Technol Res Inst Osaka Prefecture Izumi 5941157 Japan Sanyo Elect Co Ltd New Mat Res Ctr Funct Mat Dept Hirakata Osaka 5738534 Japan Shimadzu Co Ltd Technol Res Lab Kyoto 6190237 Japan

A new operation technique of dielectric bolometer (DB) mode infrared (IR) image sensor has been developed to ensure both highly sensitive IR detection and uniform IR sensitivity in every detector pixel. After calculating and adjusting the optimum amplitude and phase of supply voltage to the pixel circuit, the voltage waveform with individually adjusted amplitude and phase is supplied to every detector pixel for compensation of the output offset. A key technique is to use a field programmable gate array (FPGA) to feed the adjusted supply voltage to detector pixels when applying the compensation method to a pixel array. A program was also developed to make the adjusted supply voltage and induce the output of the detector pixels with data communication between the FPGA and a controlling personal computer. It was found that the compensation technique enables the I x 4 array to have nearly zero-offset level in all the pixels and therefore high and uniform IR detectivity. Finally, with this technique, we have fabricated several IR sensor arrays of 4 x 4, 8 x 8, and 16 x 16 pixels, where high IR sensitivities such as R-v and D* of 1.2 kV/W and 2.9 x 10(8) cm, Hz(1/2)/W, respectively, and a resultant two-dimensional image of an IR source were successfully obtained. (C) 2002 Published by Elsevier Science B.V.

关键词： infrared sensor dielectric bolometer detector pixel compensation field programmable gate array uncooled focal plane array

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Comment on "Generic universal switch blocks"

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IEEE TRANSACTIONS ON COMPUTERS 2002年第1期51卷 93-95页

作者： Fan, HB Wu, YL Chang, YW Univ Victoria Dept Comp Sci Victoria BC V8W 3P6 Canada Chinese Univ Hong Kong Dept Comp Sci & Engn Shatin Hong Kong Peoples R China Natl Chiao Tung Univ Dept Comp & Informat Sci Hsinchu 300 Taiwan

In the paper [5], the authors defined the well-structured symmetric switch block M-N,M-W and showed that M-N,M-W is universal for any pair of positive integers N and W, However, we find that this result is partially correct. Here, we show that, when N greater than or equal to 7, M-N,M-W is not universal for odd Ws (greater than or equal to 3) and it is universal for any even W.

关键词： field programmable gate array universal switch block design FPGA routing

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Autonomous Genetic Machine

Autonomous Genetic Machine

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IEEE Canadian Conference on Electrical and Computer Engineering

作者： Karnik, G Reformat, M Pedrycz, W Univ Alberta Edmonton AB T6G 2M7 Canada

ISBN: (纸本)0780375149

Research in evolvable hardware includes application of evolutionary, methods in a process of system design and on-line system adaptation. Building a hardware system capable of performing adaptation processes without external computing resources is a necessary step towards achieving a high level autonomy. Such a system, called Autonomous Genetic Machine (AGM), is presented in this paper. It represents a hardware realization of a Genetic Algorithm. Modular architecture of the AGM ensures its ease for modifications and suitability for different applications. A detailed description of design stages and implementation issues is included with emphasis focused on performance-related topics. The elaborate on the role of crucial parameters of genetic optimization such as population size, chromosome length as well as discuss various possibilities in the formation of the fitness function. In particular, we show how to design AGM for Altera's FPGAs.

关键词： Genetic Algorithms hardware implementation field programmable gate array autonomous systems evolvable hardware

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An uncooled infrared sensor of dielectric bolometer mode using a new detection technique of operation bias voltage

An uncooled infrared sensor of dielectric bolometer mode usi...

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Transducers 2001 Conference/Eurosensor XVth Conference

ISBN: (纸本)3540421505

关键词： infrared sensor dielectric bolometer detector pixel compensation field programmable gate array uncooled focal plane array

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