检索结果-内蒙古大学图书馆

3rd International Conference on 3G Mobile Communication Technologies

作者： Macpherson, K Stirling, I Rice, G García-Alís, D Stewart, R Univ Strathclyde Glasgow G1 1XQ Lanark Scotland

ISBN: (纸本)0852967497

DSP system-level design decisions can have significant effects on field programmable gate array (FPGA) hardware cost and efficiency. In this paper we demonstrate how modifying filter coefficients and taking advantage of non-canonical implementation techniques can yield reduced FPGA hardware cost. Using the Root-Raised Cosine (RRC) pulse shaping filters required in the 3G uplink reception chain as an example, different implementation techniques are compared in terms of DSP system performance and FPGA cost. RRC filter performance is evaluated through simulation of the Adjacent Channel Selectivity (ACS) test. Simulation results are presented and the differing hardware structures are evaluated.

关键词： field programmable gate arrays noncanonical implementation techniques filter coefficients FPGA hardware cost field programmable gate array DSP system-level design decisions FIR filters digital signal processing chips 3G mobile communication

来源：评论

学校读者我要写书评

暂无评论

Third Military and Aerospace programmable-Logic Devices International Conference (MAPLD'2000)

引用

JOURNAL OF SPACECRAFT AND ROCKETS 2002年第4期39卷 473-473页

作者： Vladimirova, T Katz, R Univ Surrey Surrey Space Ctr Guildford GU2 5XH Surrey England NASA Goddard Space Flight Ctr Greenbelt MD 20771 USA

来源：评论

学校读者我要写书评

暂无评论

Evolving a spatio-spectral network on reconfigurable computers for multi-spectral feature identification

Evolving a spatio-spectral network on reconfigurable compute...

引用

Conference on Imaging Spectrometry VII

作者： Porter, R Gokhale, M Harvey, N Perkins, S Young, C Los Alamos Natl Lab Los Alamos NM 87545 USA

ISBN: (纸本)0819441945

Feature identification attempts to find algorithms that can consistently separate a feature of interest from the background in the presence of noise and uncertain conditions. This paper describes the development of a high-throughput, reconfigurable computer based, feature identification system known as POOKA. POOKA is based on a novel spatio-spectral network, which can be optimized with an evolutionary algorithm on a problem-by-problem basis. The reconfigurable computer provides speed up in two places: 1) in the training environment to accelerate the computationally intensive search for new feature identification algorithms, and 2) in the application of trained networks to accelerate content based search in large multi-spectral image databases. The network is applied to several broad area features relevant to scene classification. The results are compared to those found with traditional remote sensing techniques as well as an advanced software system known as GENIE. The hardware efficiency and performance gains compared to software are also reported.

关键词： field programmable gate array reconfigurable computer evolutionary algorithm evolvable hardware feature extraction classification feature identification pattern recognition multi-spectral

来源：评论

学校读者我要写书评

暂无评论

A routability driven technology mapping algorithm for LUT based FPGA designs

引用

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2001年第11期E84A卷 2690-2696页

作者： Kao, CC Lai, YT Natl Cheng Kung Univ Dept Elect Engn Tainan 701 Taiwan

This paper presents a CAD technology mapping algorithm for LUT-based FPGAs. Since interconnections in an FPGA must be accomplished with limited routing resources, routability is the most important objective in a technology mapping algorithm. To optimize routability, the goal of the algorithm is the production of a design with a minimum interconnection. The Min-cut algorithm [1]-[3] is first used to partition a graph representing a Boolean network into clusters so that the total number of interconnections between clusters is minimum. To decrease further the number of interconnect ions needed, clusters are then merged into larger clusters by a pairing technique. This algorithm has been tested on the MCNC benchmark circuits. Compared with other LUT-based FPGA mapping algorithms, the algorithm produces better routability characteristics.

关键词： technology mapping routability min-cut field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Designing a Java microprocessor core using FPGA technology

引用

COMPUTING & CONTROL ENGINEERING JOURNAL 2000年第3期11卷 135-141页

作者： Kim, A Chang, M Lucent Techol Murray Hill NJ 07974 USA IIT Chicago IL 60616 USA

Ever since its introduction from Sun Microsystems four years ago, Java has been widely accepted in the computing and Internet industry. However, the runtime performance is still not good enough for Java to become a general-purpose programming language. This article shows how to implement a Java microprocessor core in silicon to speed up the execution of Java. For a reconfigurable and flexible design, the field programmable gate array is chosen as a target technology for the Java microprocessor. By applying a top-down hardware design methodology to the FPGA design process, it becomes easier and more flexible to implement Java in a FPGA. The DFT technique is added for better testability.

关键词： Computer architecture Microprocessor chips FPGA design process Microprocessors and microcomputers Sun Microsystems flexible design field programmable gate array general-purpose programming language Java microprocessor core design silicon implementation Digital circuit design, modelling and testing Object-oriented programming target technology Distributed systems software field programmable gate arrays Logic circuits Logic and switching circuits Java Logic design methods microprocessor chips High level languages reconfigurable architectures design for testability FPGA technology top-down hardware design methodology runtime performance DFT technique

来源：评论

学校读者我要写书评

暂无评论

Trellis extracted synchronisation and SNR estimation for turbo codes

引用

IEE PROCEEDINGS-COMMUNICATIONS 2000年第4期147卷 221-225页

作者： Coulton, P Honary, B Univ Lancaster SECAMS Dept Commun Syst Lancaster LA1 4YR England

Synchronisation is a requirement of all digital communication systems, while signal-to-noise ratio estimation is a particular requirement when using the maximum a posteriori probability algorithm for the iterative stage of a turbo code. The authors address these requirements and provide novel digital algorithms using the trellis structure of the component codes in a turbo code system. The results show that the algorithms provide the necessary functionality without degradation of performance and, as they are purely digital solutions, they are suitable for implementation on a digital signal processor or field programmable gate array.

关键词： trellis extracted synchronisation maximum a posteriori probability algorithm SNR estimation turbo codes signal-to-noise ratio digital signal processor component codes Codes trellis structure iterative decoding error correction codes synchronisation digital communication systems iterative decoding stage field programmable gate array trellis codes digital communication

来源：评论

学校读者我要写书评

暂无评论

Distributed-memory parallel routing for field-programmable gate arrays

引用

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2000年第8期19卷 850-862页

作者： Chan, PK Schlag, MDF Ebeling, C McMurchie, L Univ Calif Santa Cruz Dept Comp Engn Santa Cruz CA 95064 USA Univ Washington Dept Comp Sci Engn Seattle WA 98195 USA

The problems of placement and routing are without doubt the most time-consuming part of the process of automatically. synthesizing and configuring circuits for field-programmable gate arrays (FPGAs). FPGAs offer the ability to quickly reconfigure circuits to support rapid prototyping, emulation, or configurable computing, but the time to perform placement and routing, which can take many hours, has become a serious bottleneck. This problem is addressed here by showing that the negotiation-based routing paradigm, which has been applied successfully in several FPGA routers, can be parallelized to achieve increased performance without any significant decrease in the quality of the results. In this paper, me report several new findings related to the negotiation-based routing paradigm. We examine in-depth the convergence of the negotiation-based routing algorithm. We illustrate that the negotiation-based algorithm can be parallelized. Finally, we demonstrate that a negotiation-based parallel FPGA router performs well in terms of delay and speedup with practical FPGA circuits.

关键词： distributed computing field programmable gate array parallel algorithms parallel processing routing

来源：评论

学校读者我要写书评

暂无评论

Timing-driven routing for symmetrical array-based FPGAs

引用

ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2000年第3期5卷 433-450页

作者： Chang, YW Zhu, K Wong, DF Natl Chiao Tung Univ Dept Comp & Informat Sci Hsinchu 300 Taiwan Triscend Corp Mountain View CA 94043 USA Univ Texas Dept Comp Sci Austin TX 78712 USA

In this paper we present a timing-driven router for symmetrical array-based FPGAs. The routing resources in the FPGAs consist of segments of various lengths. Researchers have shown that the number of segments, instead of wirelength, used by a net is the most critical factor in controlling routing delay in an FPGA. Thus, the traditional measure of routing delay on the basis of geometric distance of a signal is not accurate. To consider wirelength and delay simultaneously, we study a model of timing-driven routing trees, arising from the special properties of FPGA routing architectures. Based on the solutions to the routing-tree problem, we present a routing algorithm that is able to utilize various routing segments with global considerations to meet timing constraints. Experimental results show that our approach is very effective in reducing timing violations.

关键词： computer-aided design of VLSI field programmable gate array layout synthesis

来源：评论

学校读者我要写书评

暂无评论

Design principle of SDH digital cross-connect (SDXC) matrix 2

Design principle of SDH digital cross-connect (SDXC) matrix

引用

2nd International Conference on Microwave and Millimeter Wave Technology

作者： Shi, GW Wang, Q Chen, M Northwestern Polytech Univ Xian 710072 Peoples R China

This paper presents the design principle of a SDH Digital Cross-connect (SDXC) matrix implemented with field programmable gate array (FPGA). The SDXC matrix enables construction of flexible SDH network, reduces the ef... 详细信息

ISBN: (纸本)0780357434

关键词： synchronous digital hierarchy field programmable gate arrays electronic switching systems design principle SDH digital cross-connect matrix field programmable gate array FPGA implementation flexible SDH network TDM STM-1 multiplexing structure

来源：评论

学校读者我要写书评

暂无评论

Frame processing unit for thermovision camera based on solid programmable gate array

Frame processing unit for thermovision camera based on solid...

引用

International Workshop on Optoelectronic and Hybrid Optical/Digital Systems for Image and Signal Processing

作者： Kondratov, P Bozhenko, I Hrytskiv, Z Muravov, S Res & Design Inst ELVIT UA-290005 Lviv Ukraine

ISBN: (纸本)0819437956

The video signal preprocessing unit (processor) for thermovision camera, developed by the authors on the basis of a pyroelectric vidicon, is intended for: calculation of a difference between the "positive" and "negative" frames, obtained in obturation mode: n-divisible accumulation of the resulting frame;non-volatile storage of the received images;images transmission to the computer. These functions are realized by means of following units: video signal digitizer;arithmetic-logical unit;accumulation, display and archive memory units;microcontroller. Processor is developed with field programmable gate arrays (FPGA) use. Its structure is considered.

关键词： pyroelectric vidicon frame processor thermovision camera field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：