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field programmable gate array Based Fuzzy Neural Signal Processing System for Differential Diagnosis of QRS Complex Tachycardia and Tachyarrhythmia in Noisy ECG Signals

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JOURNAL OF MEDICAL SYSTEMS 2012年第2期36卷 765-775页

作者： Chowdhury, Shubhajit Roy Jadavpur Univ Dept Elect & Telecommun Engn IC Design & Fabricat Ctr Kolkata 700032 India

The paper reports of a field programmable gate array (FPGA) based embedded system for detection of QRS complex in a noisy electrocardiogram (ECG) signal and thereafter differential diagnosis of tachycardia and tachyarrhythmia. The QRS complex has been detected after application of entropy measure of fuzziness to build a detection function of ECG signal, which has been previously filtered to remove power line interference and base line wander. Using the detected QRS complexes, differential diagnosis of tachycardia and tachyarrhythmia has been performed. The entire algorithmhas been realized in hardware on an FPGA. Using the standard CSE ECG database, the algorithm performed highly effectively. The performance of the algorithm in respect of QRS detection with sensitivity (Se) of 99.74% and accuracy of 99.5% is achieved when tested using single channel ECG with entropy criteria. The performance of the QRS detection system has been compared and found to be better than most of the QRS detection systems available in literature. Using the system, 200 patients have been diagnosed with an accuracy of 98.5%.

关键词： field programmable gate array Fuzzy entropy Electrocardiogram QRS complex

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The development of high bandwidth arbitrary waveform generator based on ADA14S800

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Radiation Detection Technology and Methods 2024年第4期8卷 1682-1692页

作者： Jia-ming Li Hong-fei Zhang Jian Wang Jie Gao Kun Ge State Key Laboratory of Particle Detection and Electronics/Deep Space Exploration Laboratory Department of Modern PhysicsUniversity of Science and Technology of ChinaHefei230026China School of Microelectronics University of Science and Technology of ChinaHefei230026China Institute of Advanced Technology University of Science and Technology of ChinaHefei230088China

Purpose To enhance signal generation capabilities,improve the performance of experimental and testing equipment,and promote innovation in related technological fields,this study aims to develop a high-bandwidth Arbitrary Waveform Generator(AWG)using the high-speed Digital-to-Analog Converter(DAC)ADA14S8000 made in *** The AWG uses the Direct Digital Waveform Synthesis(DDWS)principle with FPGA assistance to generate the waveform and achieved a storage depth of 2 Gpts with four Double Data Rate 4 Synchronous Dynamic Random-Access Memory(DDR4 SDRAM).The AWG comprises the waveform generation module,waveform conditioning module,and an operational software called *** initiate waveform generation,the AWGOperator is used to configure the waveform parameters,after which the waveform data are transferred to the waveform generation module via USB ***,the waveform generation module processes the data and generates the corresponding analogue ***-time adjustments of amplitude,bias,and delay parameters of the output waveform are also *** and conclusion The AWG provides a maximum sampling rate of 4 GSPS,a resolution of 14 bits,and a bandwidth specification of 1.6 GHz,and typical non-harmonic distortion of−55 dBc and a phase noise of less than−110 dBc/Hz at 10 kHz offset.

关键词： Arbitrary waveform generator field programmable gate array Digital-to-analog converter

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Hardware-Efficient Polar Decoder for 5G Internet of Things Communication 9th

Hardware-Efficient Polar Decoder for 5G Internet of Things C...

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9th International Conference on Intelligent IoT as a Service

作者： Guo, Jing Li, Congduan Sun Yat Sen Univ Sch Elect & Commun Engn Shenzhen Peoples R China

ISBN: (纸本)9783031705069;9783031705076

Polar codes have aroused extensive attention due to their capacity-achieving property and low encoding and decoding complexity. With the increasing demand for real-time and high-quality applications, achieving low-latency communication in resource-constrained scenarios such as on Internet of Things (IoT) devices has become essential. This paper proposes a modified semi-parallel decoder for 5G IoT communication, with low decoding latency and high efficiency of hardware resources. 4-bit decoding algorithm and look-ahead approach are used in this work to reduce latency caused by conventional semi-parallel architecture. For a code length of N = 2(10), the proposed decoder improves latency by 48.64% and 75.19% than the conventional semi-parallel decoder and 2-bit decoder, separately. The significant improvement in hardware utilization rate of processing elements by 68.42% and 119.35% leads to high efficiency of hardware resources.

关键词： Internet of things Polar codes Wireless communication Hardware architecture field programmable gate array

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Small-step Real-time Simulation for VSC Based on FPGA 9

Small-step Real-time Simulation for VSC Based on FPGA

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9th International Conference on Power and Renewable Energy

作者： Hou, Yanqi Li, Kuan Fan, Deling Sun, Kongming Huang, Qiang Li, Yudun Sun, Yuntao Zhang, Guohui Shandong Smart Grid Technol Innovat Ctr State Grid Shandong Elect Power Res Inst Jinan Peoples R China

ISBN: (纸本)9798350377477;9798350377460

The voltage source converter (VSC) has been widely used in the new power system. Its electromagnetic transient simulation has the characteristics of low simulation speed and high resource consumption. In this paper, the small-step real-time simulator for VSC based on field programmable gate array (FPGA) is established. Firstly, the fixed-admittance model for VSC is established to improve the calculation speed of the primary system. At the same time, the parallel computing process of the primary system is designed to achieve small-step real-time computing of the primary system for VSC based on the parallel computing architecture of FPGA. Secondly, according to the logic of the control system for VSC, the serial-parallel computing process of the control system is designed, and the controller for VSC is implemented based on FPGA. Finally, the performance of the established FPGA simulator is verified based on the control experiments on PSCAD/EMTDC.

关键词： small-step real-time simulation voltage source converter field programmable gate array fixed-admittance model

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Set-based fast gradient projection algorithm for model predictive control of grid-tied power converters

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AUTOMATIKA 2023年第2期64卷 304-314页

作者： Babojelic, Renato Belina, Bruno Vilic Iles, Sandor Matusko, Jadranko Univ Zagreb Fac Elect Engn & Comp Zagreb Croatia

Model Predictive Control (MPC) has attracted much attention and is widely used in power electronics. However, implementing the MPC algorithm is still a difficult task due to the fast dynamics of power converters and strict time constraints. In this paper, a computationally efficient MPC algorithm for grid-tied power converters based on the fast gradient projection method and invariant set theory is proposed. The algorithm is implemented and tested through hardware-in-the-loop simulations using Texas Instruments digital signal processors and Xilinx field programmable gate arrays platforms.

关键词： Power converters model predictive control robust control fast gradient projection method field programmable gate array

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Tapped Delay Line Time-to-Digital Converters Calibration Based on Geiger-Mode Avalanche Photodiode

Tapped Delay Line Time-to-Digital Converters Calibration Bas...

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2024 Applied Optics and Photonics China

作者： Jina, Zhihan Li, Jianjun Wang, Wentao Wang, Huili Zhai, Wenchao Zheng, Xiaobing Chinese Acad Sci Hefei Inst Phys Sci Anhui Prov Key Lab Opt Quantitat Remote Sensing Hefei 230031 Peoples R China Univ Sci & Technol China Hefei 230026 Peoples R China

ISBN: (数字)9781510687868

ISBN: (纸本)9781510687851;9781510687868

field programmable gate array (FPGA) based Tapped Delay Line (TDL)- Time-to-Digital Converters (TDC) are widely used in photoelectric measurement due to flexible design and low cost. These types of TDCs require calibration to quantify the inconsistent bin width of the delay line for better accuracy. This paper proposes a code density method based on Geiger-Mode Avalanche Photodiode (GM-APD) avalanche signals for calibration. The paper analyzes the Poisson distribution of GM-APD's avalanche signals. Then, using an experiment to verify that the proposed method is convenient and effective for TDL-TDC's calibration, reduces the Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) in measurement.

关键词： time-to-digital converters avalanche photodiode field programmable gate array quantum random number generation calibration method tapped delay line code density

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Leveraging High Level Synthesis for the Design of Hardware Accelerators for Model Predictive Control 6

Leveraging High Level Synthesis for the Design of Hardware A...

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6th Argentine Conference on Electronics (CAE)

作者： Cortes, Alfonso Aguero, Juan C. Silva, Cesar Carvajal, Gonzalo Univ Tecn Federico Santa Maria Dept Elect Valparaiso Chile

ISBN: (纸本)9798350305081

This work explores the benefits of using the High-Level Synthesis paradigm for the rapid design of FPGA-based accelerators for Model Predictive Control following a top-down design strategy. Starting from a software implementation of the operations in the control loop, we focus on leveraging typical hardware directives for parallelizing the execution of computationally demanding linear algebra operations involved in optimization algorithms, to achieve low-latency real-time operation while retaining numerical accuracy of the software counterparts with reduced design effort. The performed analysis and evaluations provide insights into the performance-cost tradeoffs when optimizing the Alternating Direction Method of Multipliers algorithm. We also derive general guidelines for tuning application-specific algorithms and deploying cost-effective FPGA accelerators to fulfill requirements for control timing intervals with relatively low coding effort.

关键词： field programmable gate array High Level Synthesis Model Predictive Control

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Functional ISS-Driven Verification of Superscalar RISC-V Processors 31

Functional ISS-Driven Verification of Superscalar RISC-V Pro...

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31st Conference on Electronics Circuits and Systems

作者： Galimberti, Andrea Vitali, Marco Vittoria, Sebastiano Zoni, Davide Politecn Milan Dipartimento Elettron Informaz & Bioingn DEIB Milan Italy

ISBN: (纸本)9798350377217;9798350377200

A time-efficient and comprehensive verification is a fundamental part of the design process for modern computing platforms, and it becomes ever more important and critical to optimize as the latter get ever more complex. SupeRFIVe is a methodology for the functional verification of superscalar processors that leverages an instruction set simulator to validate their correctness according to a simulation-based approach, interfacing a testbench for the design under test with the instruction set simulator by means of socket communication. We demonstrate the effectiveness of the SupeRFIVe methodology by applying it to verify the functional correctness of a RISC-V dual-issue superscalar CPU, leveraging the state-of-the-art RISC-V instruction set simulator Spike and executing a set of benchmark applications from the open literature.

关键词： central processing unit superscalar architecture instruction set simulator hardware verification functional verification RISC-V field programmable gate array

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Research on the Deployment Strategy of Big Data Visualization Platform by the Internet of Things Technology

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EAI ENDORSED TRANSACTIONS ON SCALABLE INFORMATION SYSTEMS 2023年第4期10卷 1-11页

作者： Zhang, Guangtao Yangzhou Polytechn Coll Informat Engn Coll Yangzhou 225000 Jiangsu Peoples R China

In order to improve the performance of the big data visualization platform and improve the task scheduling capability of the platform, a big data visualization platform is constructed based on field programmable gate array (FPGA) chip application power equipment. This study proposes to combine genetic algorithm and ant colony scheduling (ACOS) algorithm to design a big data visualization platform deployment strategy based on improved ACOS algorithm. Firstly, big data technology is analyzed. Then, the basic theory of ant colony algorithm is studied. According to the basic theory of ACOS and genetic algorithm, an improved ACOS algorithm model is constructed. The improved ACOS algorithm scheduler is compared with the other three schedulers. Under the same environment, the completion time of scheduling the same job and different task amounts is analyzed. The Central Processing Unit (CPU) utilization is analyzed when different schedulers completely different workloads. The results show that the constructed big data visualization platform based on the improved ACOS algorithm model has higher task scheduling efficiency than other schedulers, and can greatly shorten the data processing time. The experimental results show that under the homogeneous cluster, the completion time of the improved ACOS algorithm generally lags the capacity scheduler and the fair scheduler. Under the heterogeneous cluster, the improved ACOS algorithm scheduler can reasonably allocate tasks to nodes with different performances, reducing the task completion time. When the number of completed tasks increases from 50 to 200, the time increases by 45s, and the completion time is smaller than other schedulers. The CPU utilization of different task volumes is the highest, and the utilization rate increases from 81% to 95%. The improved ACOS algorithm scheduler has the shortest data processing time and the highest efficiency. This work provides a certain reference value for optimizing the deployment strat

关键词： CPU field programmable gate array genetic algorithm IOT ant colony scheduling big data

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Towards Quantum Circuit Emulation on Low -Tier FPGAs 5

Towards Quantum Circuit Emulation on Low -Tier FPGAs

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2024 International Conference on Quantum Computing and Engineering

作者： Conti, Christian Volpe, Deborah Cirillo, Giovanni Amedeo GrazianoT, Mariagrazia Zamboni, Maurizio Turvani, Giovanna Politecnico Torino Italy Dept Elctron & Telecommun Turin Italy Politecnico Torino Italy Dept Appl Sci & Technol Turin Italy

ISBN: (纸本)9798331541378

Researchers and industries are increasingly drawn to quantum computing for its computational potential. However, validating new quantum algorithms is challenging due to current quantum device limitations. Software simulators are time and memory -intensive, making hardware emulators an attractive alternative. This article introduces a digital architecture, designed to emulate quantum computing on low -tier field -programmable gate arrays (FPGAs), supporting Clifford+T and rotational gate sets. It simplifies and accelerates quantum algorithm verification using a RISC -like structure and efficiently handling sparse quantum gates. A dedicated compiler translates OpenQASM 2.0 into RISC -like instructions. The architecture is validated against the Qiskit state vector simulator, successfully emulating sixteen qubits on a Xilinx Kria KV260 SoM.

关键词： Quantum Computing Emulation field programmable gate array Quantum Algorithm Verification Quantum Computing Simulation

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