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Design of SSVEP Enhancement-Based Brain Computer Interface

IEEE SENSORS JOURNAL 2021年第13期21卷 14330-14338页

作者： Lin, Bor-Shing Wang, Hsiao-An Huang, Yao-Kuang Wang, Yu-Lin Lin, Bor-Shyh Natl Taipei Univ Dept Comp Sci & Informat Engn New Taipei 23741 Taiwan Natl Chiao Tung Univ Inst Imaging & Biomed Photon Tainan 71150 Taiwan Chiayi Chang Gung Mem Hosp Div Cardiovasc Surg Puzi City 61363 Chiayi County Taiwan Chi Mei Med Ctr Dept Rehabil Tainan 71004 Taiwan

Brain computer interface (BCI) system is a communication bridge between the brain and the external device, and it has been rapidly developed in the recent years. Here, steady state visually evoked potential (SSVEP) is one of the most frequently used control methods for BCI due to its advantages of low training requirement and high stability. However, some people present unobvious SSVEP feature at the location of the primary visual cortex, and this will reduce the performance of SSVEP-based BCIs. In this study, a novel field programmable gate array (FPGA)-based brain computer interface with SSVEP enhancement is proposed to improve the above issue. In the proposed system, a SSVEP-enhancement active dry electrode is designed to acquire good quality of electroencephalography (EEG) without conductive gels, and further enhance the local EEG signal. The experimental results show the proposed system can effectively improve the signal-to-noise ratio of SSVEP and the information transfer rate. Moreover, compared with the current SSVEP-based BCIs in the previous studies, the proposed BCI system contains the advantages of local EEG enhancement, wearablility, wireless transmission, front-end BCI translation, and it contains the potential of applying in many BCI applications in daily life.

关键词： Electroencephalography Electrodes Pins Metals Skin Brain-computer interfaces Visualization Brain computer interface steady state visually evoked potentials field programmable gate array SSVEP enhancement

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Multiple perspectives on the hardware implementations of biological neuron models and programmable design aspects

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2016年第3期24卷 1729-1746页

作者： Korkmaz, Nimet Ozturk, Ismail Kilic, Recai Erciyes Univ Fac Engn Dept Elect & Elect Engn Kayseri Turkey

A few individual design examples of programmable device-based biological neuron model implementations are available in the literature, but there is no comprehensive study that examines analog and digital programmable design examples of frequently studied biological neuron model implementations. The aim of this paper is to present a comparative study about programmable and reconfigurable implementations of the FitzHugh-Nagumo, Izhikevich, and Hindmarsh-Rose neuron models. Since field programmable analog array (FPAA) and field programmable gate array (FPGA) devices offer several advantages such as flexible design possibilities, reduction of the complexity of design, real-time modification, and software control for programmable and reconfigurable implementations of neuron models and neural structures, they are preferred in these implementations as analog and digital programmable devices. Experimental results agree with the numerical simulations and verify the design effectiveness of FPAA- and FPGA-based implementations.

关键词： Neuron models field programmable analog array field programmable gate array circuit implementation

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FPGA-based entropy neural processor for online detection of multiple combined faults on induction motors

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MECHANICAL SYSTEMS AND SIGNAL PROCESSING 2012年 30卷 123-130页

作者： Cabal-Yepez, E. Valtierra-Rodriguez, M. Romero-Troncoso, R. J. Garcia-Perez, A. Osornio-Rios, R. A. Miranda-Vidales, H. Alvarez-Salas, R. Univ Guanajuato Carr Salamanca Valle Div Ingn HSPdigital CA Telemat Procesamiento Digital Senal Guanajuato 36700 Mexico Univ Autonoma Queretaro Fac Ingn HSPdigital CA Mecatron San Juan Del Rio 76807 Queretaro Mexico Zona Univ Univ Autonoma San Luis Potosi Fac Ingn CA Elect Potencia & Control San Luis Potosi 78290 SLP Mexico

For industry, a faulty induction motor signifies production reduction and cost increase. Real-world induction motors can have one or more faults present at the same time that can mislead to a wrong decision about its operational condition. The detection of multiple combined faults is a demanding task, difficult to accomplish even with computing intensive techniques. This work introduces information entropy and artificial neural networks for detecting multiple combined faults by analyzing the 3-axis startup vibration signals of the rotating machine. A field programmable gate array implementation is developed for automatic online detection of single and combined faults in real time. (C) 2012 Elsevier Ltd. All rights reserved.

关键词： Induction motors Multiple combined faults 3-axis vibration signals Information entropy Artificial neural networks field programmable gate array

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Real-time digital simulation of power electronics systems with Neutral Point Piloted multilevel inverter using FPGA

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ELECTRIC POWER SYSTEMS RESEARCH 2011年第2期81卷 687-698页

作者： Rakotozafy, Mamianja Poure, Philippe Saadate, Shahrokh Bordas, Cedric Leclere, Loic Fac Sci & Tech LIEN F-54506 Vandoeuvre Les Nancy France Fac Sci & Tech GREEN F-54506 Vandoeuvre Les Nancy France CONVERTEAM SAS F-90008 Belfort France

Most of actual real time simulation platforms have practically about ten microseconds as minimum calculation time step, mainly due to computation limits such as processing speed, architecture adequacy and modeling complexities. Therefore, simulation of fast switching converters' instantaneous models requires smaller computing time step. The approach presented in this paper proposes an answer to such limited modeling accuracies and computational bandwidth of the currently available digital *** an example, the authors present a low cost, flexible and high performance FPGA-based real-time digital simulator for a complete complex power system with Neutral Point Piloted (NPP) three-level inverter. The proposed real-time simulator can model accurately and efficiently the complete power system, reducing costs, physical space and avoiding any damage to the actual equipment in the case of any dysfunction of the digital controller prototype. The converter model is computed at a small fixed time step as low as 100 ns. Such a computation time step allows high precision account of the gating signals and thus avoids averaging methods and event compensations. Moreover, a novel high performance model of the NPP three-level inverter has also been proposed for FPGA implementation. The proposed FPGA-based simulator models the environment of the NPP converter: the dc link, the RLE load and the digital controller and gating signals. FPGA-based real time simulation results are presented and compared with offline results obtained using PLECS software. They validate the efficiency and accuracy of the modeling for the proposed high performance FPGA-based real-time simulation approach. This paper also introduces new potential FPGA-based applications such as low cost real time simulator for power systems by developing a library of flexible and portable models for power converters, electrical machines and drives. (C) 2010 Elsevier B.V. All rights reserved.

关键词： field programmable gate array Power electronics Real-time simulation Neutral Point Piloted three-level converter Power system simulation

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Non-linear behavioural modelling of device-level transients for complex power electronic converter circuit hardware realisation on FPGA

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IET POWER ELECTRONICS 2018年第9期11卷 1566-1574页

作者： Lin, Ning Shi, Bo Dinavahi, Venkata Univ Alberta Dept Elect & Comp Engn Edmonton AB Canada

Detailed device-level models of the insulated-gate-bipolar-transistor (IGBT) and diode are essential for power converter design evaluation for providing insight into circuit and device behaviours, as well as to shorten the design cycle and reduce costs. In this study, the non-linear behavioural models of IGBT and power diode are utilised for emulating the modular multilevel converter (MMC) on the field programmable gate array. For digital hardware-in-the-loop (HIL) emulation, these time-domain continuous models are discretised and linearised prior to being designed into the corresponding hardware modules using the hardware description language VHDL that features a fully paralleled and pipelined implementation. A circuit partitioning approach is adopted according to the MMC structure to enhance computation efficiency and then, detailed information from the system-level performance to the specific features of individual switches is available. HIL emulation and the subsequent comparison with results from the commercial off-line simulation tools prove that the complex IGBT and diode models can be involved in the efficient simulation of large-scale power converters.

关键词： field programmable gate arrays power convertors power semiconductor switches insulated gate bipolar transistors power semiconductor diodes time-domain analysis hardware description languages nonlinear behavioural modelling of device level transient model complex power electronic converter circuit hardware FPGA insulated-gate-bipolar-transistor IGBT power diode modular multilevel converter field programmable gate array digital hardware-in-the-loop emulation HIL emulation time domain continuous model hardware description language VHDL pipelined implementation circuit partitioning approach MMC structure switch

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Very-large-scale integration design of a low-power and cost-effective context-based adaptive variable length coding decoder for H.264/AVC portable applications

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IET IMAGE PROCESSING 2012年第2期6卷 104-114页

作者： Huang, H-J. Fang, C-H. Fan, C-P. Natl Chiao Tung Univ Dept Elect Engn Hsinchu 300 Taiwan Natl Chung Hsing Univ Dept Elect Engn Taichung 402 Taiwan

Context-based adaptive variable length coding (CAVLC) is a new and efficient entropy coding tool in H.264/AVC (advanced video coding). This study proposes a low-power and cost-effective CAVLC decoding architecture for the H.264/AVC baseline profile. Specifically, this study proposes an optimum two-layer power model for the variable length look-up table (VLUT) in the CAVLC decoder, and divides the decoding phase of the LUT into two-layer decoding to reduce power consumption. To achieve a cost-effective design, the proposed design merges common codewords to reduce the hardware cost among different LUTs in the second layer decoding. The proposed decoder is based on Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 mu m CMOS technology, and was completely verified on a field-programmable gate array (FPGA) emulation platform. The proposed design meets the demands of the real-time CAVLC decoding and reduces power consumption by 44-48% more than previous low-power CAVLD schemes. Finally, the proposed low-power and cost-effective CAVLD design is suitable for H.264/AVC portable applications.

关键词： size 0.18 mum Codes table lookup variable length codes field programmable gate arrays Image and video coding entropy codes CMOS technology context-based adaptive variable length coding decoder entropy coding tool common codewords adaptive codes Logic circuits video coding Logic and switching circuits cost-effective CAVLC decoding variable length look-up table advanced video coding H.264/AVC portable applications two-layer decoding decoding CMOS integrated circuits VLSI Video signal processing Taiwan Semiconductor Manufacturing Company field programmable gate array low-power CAVLC decoding power consumption very large scale integration

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FPGAN: An FPGA Accelerator for Graph Attention Networks With Software and Hardware Co-Optimization

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IEEE ACCESS 2020年 8卷 171608-171620页

作者： Yan, Weian Tong, Weiqin Zhi, Xiaoli Shanghai Univ Sch Comp Engn & Sci Shanghai 200444 Peoples R China Shanghai Univ Shanghai Inst Adv Commun & Data Sci Shanghai 200444 Peoples R China

The Graph Attention Networks (GATs) exhibit outstanding performance in multiple authoritative node classification benchmark tests (including transductive and inductive). The purpose of this research is to implement an FPGA-based accelerator called FPGAN for graph attention networks that achieves significant improvement on performance and energy efficiency without losing accuracy compared with PyTorch baseline. It eliminates the dependence on digital signal processors (DSPs) and large amounts of on-chip memory and can even work well on low-end FPGA devices. We design FPGAN with software and hardware co-optimization across the full stack from algorithm through architecture. Specifically, we compress model to reduce the model size, quantify features to perform fixed-point calculation, replace multiplication addition cell (MAC) with shift addition units (SAUs) to eliminate the dependence on DSPs, and design an efficient algorithm to approximate SoftMax function. We also adjust the activation functions and fuse operations to further reduce the computation requirement. Moreover, all data is vectorized and aligned for scalable vector computation and efficient memory access. All the above optimizations are integrated into a universal hardware pipeline for various structures of GATs. We evaluate our design on an Inspur F10A board with an Intel Arria 10 GX1150 and 16 GB DDR3 memory. Experimental results show that FPGAN can achieve 7.34 times speedup over Nvidia Tesla V100 and 593 times over Xeon CPU Gold 5115 while maintaining accuracy, and 48 times and 2400 times on energy efficiency respectively.

关键词： field programmable gate arrays Acceleration Computational modeling Computer architecture Optimization Hardware Energy efficiency Graph attention networks model optimization inference accelerating field programmable gate array heterogeneous computing parallel computing energy efficiency shift operation

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A routability driven technology mapping algorithm for LUT based FPGA designs

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2001年第11期E84A卷 2690-2696页

作者： Kao, CC Lai, YT Natl Cheng Kung Univ Dept Elect Engn Tainan 701 Taiwan

This paper presents a CAD technology mapping algorithm for LUT-based FPGAs. Since interconnections in an FPGA must be accomplished with limited routing resources, routability is the most important objective in a technology mapping algorithm. To optimize routability, the goal of the algorithm is the production of a design with a minimum interconnection. The Min-cut algorithm [1]-[3] is first used to partition a graph representing a Boolean network into clusters so that the total number of interconnections between clusters is minimum. To decrease further the number of interconnect ions needed, clusters are then merged into larger clusters by a pairing technique. This algorithm has been tested on the MCNC benchmark circuits. Compared with other LUT-based FPGA mapping algorithms, the algorithm produces better routability characteristics.

关键词： technology mapping routability min-cut field programmable gate array

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A Deep Learning Approach for the Design of Narrow Transition-Band FIR Filter

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2022年第10期41卷 5578-5613页

作者： Roy, Subhabrata Chandra, Abhijit Jadavpur Univ Dept Instrumentat & Elect Engn Kolkata 700106 India

Deep neural network (DNN), being an important member of machine learning family, has been employed to serve a wide range of applications in the area of signal and image processing like pattern recognition, speech recognition, language processing, image segmentation, etc. To this aim, this paper concentrates on the design of a narrow transition-band finite impulse response (FIR) filter with the aid of back-propagation-based deep learning approach. The proposed deep learning-based approach offers a unified design framework for a variety of FIR filters. Convergence behaviour of the proposed algorithm has been proved analytically in situations when weights between adjacent layers are updated continuously. Simulation results have shown the frequency response characteristics of several FIR filters with narrow transition-band, designed with the help of proposed approach. Advantage of our design strategy has also been established in terms of magnitude response over a number of state-of-the-art techniques of recent interest. Simulation results have shown noticeable improvement in terms of transition bandwidth when compared with few existing works. Designed filter is subsequently implemented on Altera's Cyclone IV field programmable gate array (FPGA) chip, and hardware efficiency of the suggested design has strongly been established by correlating its hardware cost with many of the state-of-the-art FIR filters.

关键词： Deep neural network Finite impulse response filter field programmable gate array Low complexity Narrow-band filter

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Hardware Implementation of Reconfigurable 1D Convolution

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2016年第1期82卷 1-16页

作者： Rao, Lei Zhang, Bin Zhao, Jizhong Xi An Jiao Tong Univ Xian 710049 Shaanxi Peoples R China

Convolution has been extensively used in image processing and computer vision, including image enhancement, smoothing, and structure extraction. However, convolution operation typically requires a significant amount of computing resources. A novel one-dimensional (1D) convolution processor with reconfigurable architecture is implemented in this study. This processor is a combination of a line buffer, controller units, as well as a reconfigurable and separable convolution module. The use of a reconfigurable architecture and separable convolution approach improves the flexibility and performance of the convolution processor. The reconfigurable and separable convolution array, which is the main component of the processor, can simultaneously execute convolution operation with different kernels, with a maximum kernel size of up to 24 x 24. Experimental results show that the maximum frames rate of the processor is approximately 194 frames per second (fps), which exceeds the real-time requirement. Synthesis results show that the processor occupies 13.39 mm (2) at a 204 MHz system clock and consumes a power of 419 mW at maximum kernel size at a 120 MHz system clock in SMIC 0.18 mu m CMOS technology. Verification experiments on field programmable gate arrays (FPGAs) demonstrate that the processor is suitable for real-time image processing applications even for high-resolution images.

关键词： Convolution field programmable gate array Reconfigurable architecture

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