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NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT 2013年 701卷 7-16页

作者： Hromalik, Marianne S. Green, Katherine S. Philipp, Hugh T. Tate, Mark W. Gruner, Sol M. SUNY Coll Oswego Dept Comp Sci Oswego NY 13126 USA Cornell Univ Lab Atom & Solid State Phys Ithaca NY 14853 USA Cornell Univ Cornell High Energy Synchrotron Source Ithaca NY 14853 USA

A proposed design for a reconfigurable x-ray Pixel array Detector (PAD) is described. It operates by integrating a high-end commercial field programmable gate array (FPGA) into a 3-layer device along with a high-resistivity diode detection layer and a custom, application-specific integrated circuit (ASIC) layer. The ASIC layer contains an energy-discriminating photon-counting front end with photon hits streamed directly to the FPGA via a massively parallel, high-speed data connection. FPGA resources can be allocated to perform user defined tasks on the pixel data streams, including the implementation of a direct time autocorrelation function (ACF) with time resolution down to 100 ns. Using the FPGA at the front end to calculate the ACF reduces the required data transfer rate by several orders of magnitude when compared to a fast framing detector. The FPGA-ASIC high-speed interface, as well as the in-FPGA implementation of a real-time ACF for x-ray photon correlation spectroscopy experiments has been designed and simulated. A 16 x 16 pixel prototype of the ASIC has been fabricated and is being tested. (C) 2012 Published by Elsevier B.V.

关键词： X-ray Pixel array Detectors field programmable gate array Real-time data processing Autocorrelation function

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FPGA implementation of NN based LMS-LMF control algorithm in DSTATCOM for power quality improvement

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CONTROL ENGINEERING PRACTICE 2020年 98卷 104378-000页

作者： Malathi, S. Jayachandran, J. SASTRA Deemed Univ Dept Elect & Elect Engn Thanjavur 613401 Tamil Nadu India

Neural Network (NN) based Least Mean Square (LMS)-Least Mean Fourth (LMF) control technique is developed and implemented in field programmable gate array (FPGA) for Shunt Active Power Filter (SAPF) to enhance Power Quality (PQ) in three-phase four wire distribution system. The PQ enhancement comprises the improvement of power factor, mitigation of harmonics and compensation of reactive power. The proposed control strategy is simulated in MATLAB/Simulink to determine the reference source currents and weights of active and reactive components. The simulation results of LMS-LMF control are compared with the other three control strategies. The NN control is developed as individual modules in FPGA. Thus it can be configured to any other research area which has identical requirements. The FPGA implementation overcomes the drawback of conventional controllers with a fast and accurate response. The FPGA based proposed control strategy for SAPF is developed as a laboratory prototype and the results obtained are analyzed. The results attained adhere to power quality standards.

关键词： Neural network Shunt active power filter Total harmonic distortion field programmable gate array Power quality

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Low Complexity Digital Quadrature Oscillators for Variable Frequency Applications

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 2024年第9期71卷 10475-10485页

作者： Sengupta, Arkadeb Shahu, Vihan Kundu, Utsab John, Vinod Univ Kiel Chair Power Elect D-24143 Kiel Germany Indian Inst Sci Dept Elect Engn Bengaluru 560012 India

Switching frequency is utilized as a degree of freedom in digital control strategies for power converters. In addition to carrier-based schemes, quadrature oscillators offer an alternative method for the generation of variable frequency switching pulses. In this article, amplitude instability in a computationally simple digital quadrature oscillator is analyzed. Algorithms for stabilizing the oscillator are developed based on this. Further implementation issues arising are addressed and a systematic comparison to carrier-based schemes is executed. It is shown that the proposed approach can be implemented with only four additions and four comparison steps without resorting to multiplication. The studies are validated in system simulation and experiments on a commercial field programmable gate array board.

关键词： Amplitude stabilization field programmable gate array integrator discretization quadrature oscillator second order generalized integrator

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Hardware-assisted initialisation for constant modulus algorithm adaptive antenna

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IET MICROWAVES ANTENNAS & PROPAGATION 2008年第4期2卷 303-311页

作者： Boonpoonga, A. Sirisuk, P. Chongcheawchamnan, M. Patisang, S. Krairiksh, M. King Mongkuts Inst Technol Ladkrabang Fac Engn Bangkok 10520 Thailand King Mongkuts Inst Technol Ladkrabang Res Ctr Commun & Informat Technol Bangkok 10520 Thailand Mahanakorn Univ Technol Fac Engn Bangkok 10530 Thailand

A cost-effective approach for initialisation of an adaptive antenna based on the constant modulus algorithm (CMA) is proposed. The technique utilises 1 bit phase shifters and a power detector, which are normally integrated with a multibeam antenna, to determine the maximum power beam direction. Consequently, the beam is exploited as an initial beam for CMA. Development of hardware-assisted initialisation is discussed. In addition field programmable gate array implementation of a CMA processor and associated control circuitry is presented. Several simulations are performed to evaluate the performance of the proposed initialisation technique. In addition, the developed prototype is tested with a phase array antenna designed for operation at the IMT2000 frequency of 1.95 GHz. Experimental results confirm superiority of the proposed technique.

关键词： Other analogue circuits field programmable gate arrays multibeam antenna field programmable gate array constant modulus algorithm hardware-assisted initialisation adaptive antenna arrays phase shifters associated control circuitry Logic circuits CMA processor CMA based adaptive antenna Antenna arrays power detector

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Design and implementation of equilateral triangle array digital direction finding system

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IEICE ELECTRONICS EXPRESS 2012年第13期9卷 1102-1108页

作者： Zhou, Lin Wang, Fan Gao, Huotao Sun, Yuxiang Zhang, Huajun Wuhan Univ Elect Informat Dept Wuhan 430072 Peoples R China

In this work, a scheme of an equilateral triangle array digital direction finding system is proposed, which implements the online real-time direction finding task for an airborne system. The three-elements equilateral triangle array can be used for calibrating the channel errors and eliminating the DOA (direction of arrival) fuzzy problem of the two-elements linear array, which is greatly reduced the system complexity and suitable for portable requirement. At the same time, the project adopts field programmable gate array (FPGA) to process the sample data in parallel mode, including data quadrature demodulation and multiple signal classification (MUSIC) algorithm. The hardware implementation of MUSIC algorithm makes the system more flexible and faster than software implementation. The experimental results show that the deviation is less than 0.5 degrees with over 64 snapshots and the time is less 6ms with 256 snapshots, and then the program can complete the MUSIC algorithm accurately with high speed.

关键词： direction of arrival equilateral triangle array channel calibration field programmable gate array multiple signal classification algorithm

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A Video Streaming Encryption Method and Experimental System Based on Reconfigurable Quaternary Logic Operators

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IEEE ACCESS 2024年 12卷 25034-25051页

作者： Zhou, Xinyu Wang, Hongjian Li, Kuiyan Tang, Lifeng Mo, Ningchun Jin, Yi Donghua Univ Sch Comp Sci & Technol Shanghai 201620 Peoples R China Shanghai Astronaut Elect Co Ltd Shanghai 201821 Peoples R China Shanghai Meiduo Commun Equipment Co Ltd Shanghai 200333 Peoples R China Shanghai Univ Sch Comp Engn & Sci Shanghai 200444 Peoples R China

Multiple-valued logics (MVL) have abundant operation functions which can be used for encryption. A reconfigurable MVL operator can perform all MVL functions with a universal circuit structure at fast operation speed, based on which a one-time-pad cryptosystem is expected to be built. However, we find that when the existing MVL encryption method is applied to video data encryption, the color edges in the plaintext image will remain in the ciphertext image, resulting in partial leakage of information. To solve this problem, we propose byte reorganization and random mask strategies, forming an improved MVL encryption method for video streaming. For verifying the effectiveness of the method, we implement an FPGA-based experimental system to encrypt and decrypt real-time video streaming data. In this system, 16-quit reconfigurable quaternary logic operators are implemented to encrypt, decrypt and derive keys. The process of either encryption or decryption only takes 34 clock cycles. The encryption and decryption modules are capable of processing streaming data at a speed of 6.21 Gbit/s, showing that the system has real-time processing capability. For proving that our method is secure, we compare our improved MVL encryption method with existing image encryption methods in terms of common security evaluation metrics. Experimental results show that our method solves the problem of remained color edge and the ciphertext exhibits good statistical properties.

关键词： Encryption Cryptography Streaming media Real-time systems Symbols Image edge detection field programmable gate arrays Videos Image processing Reconfigurable architectures Video and image encryption multiple-valued logic reconfigurable quaternary logic operator field programmable gate array

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FPGA Based Integrated Control of Brushless DC Motor for Renewable Energy Storage System

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CYBERNETICS AND SYSTEMS 2024年第4期55卷 918-939页

作者： Karthikeyan, S. Lakshmi, K. Sri Krishna Coll Engn & Technol Coimbatore Tamilnadu India KSR Coll Engn Dept EEE Tiruchengode Tamilnadu India

To reduce air pollution and global warming, renewable energy technologies may generate power. Wind, solar PV, and fuel cell energy are the primary sources. Solar PV system-powered brushless direct current motor (BLDC) drives are used in the automobile industry due to their importance. In this study, Sheppard-Taylor (S-T) converter and Pulse Width Modulated (PWM) Inverter-fed BLDC provide steady voltage across the BLDC motor drive independent of solar PV system power output. When renewable energy is scarce, the proposed battery-supercapacitor hybrid energy storage system (BS-HESS) provides electricity. S-T converters may be used for load matching and power processing to create energy-efficient systems and stabilize PV panel output voltage. The variable step size open circuit voltage-Maximum Power Point Tracking (VSSOCV-MPPT) technique in S-T converter switching pulses extracts maximum power from the solar PV system. This study considers the PVSWPS control function as a Port-Controlled Hamiltonian (PCH) system to continue rural growth and reduce the greatest demand and load. MATLAB/Simulink software simulates the system's performance, and FPGA controllers validate the controller's real-time performance.

关键词： Brushless DC motor energy storage system field programmable gate array renewable energy storage system solar water pumping system (PVSWPS) S-T converter variable step size open circuit voltage-Maximum Power Point Tracking (VSSOCV-MPPT)

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Dynamic Robust Single-Event Upset Simulator

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JOURNAL OF AEROSPACE INFORMATION SYSTEMS 2018年第5期15卷 282-296页

作者： Carlisle, Edward George, Alan Univ Pittsburgh NSF Ctr Space High Performance & Resilient Comp Pittsburgh PA 15261 USA Univ Florida 560 Schenley Pl Pittsburgh PA 15213 USA Univ Pittsburgh NSF Ctr Space High Performance & Resilient Comp ECE 1238D Benedum Hall Pittsburgh PA 15261 USA

This paper presents the dynamic robust single-event upset simulator, which is a novel framework for fault injection on hardware (via onchip debugging) and simulation testbeds (via the Simics (R) full-system simulator from Wind River Systems). Typically, radiation-hardened processers are used for space computing;however, commercial off-the-shelf processors can provide higher performance and lower costs. Although commercial devices are susceptible to radiation-induced faults, fault-injection testing can be used to qualify these devices for use in space. The de facto standard for fault injection is radiation-beam testing, which is often prohibitively expensive and time consuming. The current methodology provides a means to iteratively decrease design vulnerabilities through rapid fault injection before beam testing. Additionally, the methodology can supplement beam-test results by targeting injections at individual components of interest that are difficult to isolate in beam tests. The current fault-injection mechanisms leverage on-chip debuggers and simulation checkpoints, allowing the framework to target a wide range of system components for injection. The injection capabilities and analysis features of the framework are demonstrated by presenting fault-injection results for an image-processing application on two different processor architectures (PowerPC and ARM (R)) in both hardware and simulation.

关键词： Fault Injection Image Processing Space Computing Commercial off the Shelf Debugger field programmable gate array Portable Operating System Feature Detection High Performance Reconfigurable Computing Random Access Memory

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A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems

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MICROELECTRONICS JOURNAL 2006年第6期37卷 554-564页

作者： Galanis, MD Milidonis, A Kakarountas, AP Goutis, CE Univ Patras Dept Elect & Comp Engn VLSI Design Lab Patras 26500 Greece

In this paper, we propose a method for speeding-up Digital Signal Processing applications by partitioning them between the reconfigurable hardware blocks of different granularity and mapping critical parts of applications on coarse-grain reconfigurable hardware. The reconfigurable hardware blocks are embedded in a heterogeneous reconfigurable system architecture. The fine-grain part is implemented by an embedded FPGA unit, while for the coarse-grain reconfigurable hardware our developed high-performance coarse-grain data-path is used. The design flow mainly consists of three steps;the analysis procedure, the mapping onto coarse-grain blocks, and the mapping onto the fine-grain hardware. In this work, the methodology is validated using five real-life applications;an OFDM transmitter, a medical imaging technique, a wavelet-based image compressor, a video compression scheme and a JPEG encoder. The experimental results show that the speedup, relative to an all-FPGA solution, ranges from 1.55 to 4.17 for the considered applications. (C) 2005 Elsevier Ltd. All rights reserved.

关键词： heterogeneous reconfigurable system partitioning coarse-grain reconfigurable hardware field programmable gate array performance design flow

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Signal processing at 250 MHz using high-performance FPGA's

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1998年第2期6卷 238-246页

作者： Von Herzen, B Rapid Prototypes Inc Carson City NV 89701 USA

This paper describes an application in high-performance signal processing using reconfigurable computing engines: a 250-MHz cross correlator for radio astronomy. Experimental results indicate that complementary metal-oxide-semiconductor (CMOS) field programmable gate arrays (FPGA's) can per form useful computation at 250 MHz. The notion of an "event horizon" for FPGA's leads to clear design constraints for highspeed application developers, and can be applied to a variety of real-time signal processing algorithms. Recent estimates indicate that higher performance FPGA's available early in 1998 can attain speeds of over 300 MHz using 20% fewer logic elements than current designs. The results of this design work provide important clues on how to improve FPGA architectures for signal processing at hundreds of MHz. Direct routing channels between logic elements can significantly increase performance. Routing architectures with four-way symmetry allow for rotations and reflections of subcircuits needed for optimal packing density. Experimental results indicate that clock buffering often limits the top speed of the FPGA. Wave pipelining of clock distribution network may improve FPGA performance.

关键词： correlators event horizon field programmable gate array manual partitioning and placement programmable logic real-time signal processing

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