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IEEE International Conference on Control Applications Part of 2010 IEEE Multi-Conference on Systems and Control

作者： Sun, Yifan Fang, Yongchun Zhang, Yudong Dong, Xiaokun Nankai Univ Inst Robot & Automat Informat Syst IRAIS Tianjin 300071 Peoples R China

ISBN: (纸本)9781424453634

This report describes the realization of an embedded hardware system designed to perform fast control for an atomic force microscope (AFM). Traditional implementation of control algorithms for AFMs, either PC-based or DSP-based, does not meet the high-speed scanning requirement. Considering the capability of parallel computing, FPGA is employed to achieve real-time control for an AFM equipment. Specifically, in the designed embedded system, the hardware includes several key components of signal acquisition, signal conversion, data communication as well as the FPGA-based control law implementation. Besides higher control frequency, the designed FPGA-based embedded system provides a general platform for different advanced control strategies, on which a variety of control algorithms can be implemented and tested conveniently by replacing the codes in the software rather than changing hardware structure, due to the merit that FPGA can integrate internal CPU and it has a large number of logic cells and soft-cores. The widely utilized proportional-integral-derivative (PID) algorithm is chosen as an example to demonstrate the implementation of a controller by using powerful hardware description tools.

关键词： AFM real-time control FPGA-based control law atomic force microscope atomic force microscopy embedded hardware system design embedded systems field programmable gate array field programmable gate arrays parallel computing proportional-integral- derivative algorithm three-term control

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field programmable gate array HIGH CAPACITY TECHNOLOGY FOR RADAR AND COUNTER-RADAR DRFM SIGNAL PROCESSING

FIELD PROGRAMMABLE GATE ARRAY HIGH CAPACITY TECHNOLOGY FOR R...

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作者： Hawken L. Grubbs NAVAL POSTGRADUATE SCHOOL

学位级别：硕士

Radar systems often use low power, continuous waveform radio frequency (RF) modulations and require high-speed adaptive signal processors to provide the necessary processing gain to detect small radar cross-section targets in clutter on range-Doppler maps. Counter-radar technologies include digital RF memories (DRFMs) that attempt to provide multiple, structured false targets with clutter, for example, using a pipelined, finite impulse response arrangement of complex range bin processors. This thesis investigates high-capacity field-programmable gate array (FPGA) technology to enable on-the-fly flexibility and reconfigurability for both radar signal processing and DRFM electronic attack using a Xilinx Virtex Ultrascale+. A three-stage range, Doppler, post-detection integration radar modulation compression circuit is designed and quantified. A range compression circuit with a peak power consumption of 6.100W and a post-implementation utilization of 11% was designed. The Doppler filter bank was designed at 400 MHz with a peak power consumption of 2.688W and a post-implementation utilization of 9%. A coherent integration processor at 400 MHz had a peak power consumption of 2.517W and a post-implementation utilization of 9%. In addition, a DRFM complex range bin processor was designed and quantified at 500 MHz and had a peak power 2.543W with a post-implementation utilization of 11%.

关键词： LPI radar low probability of intercept radar FPGA field programmable gate array Virtex Ultrascale+ Vivado Simulink DSP digital signal processing DRFM Xilinx

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Design optimisation of multiplier-free parallel pipelined FFT on field programmable gate array

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IET CIRCUITS DEVICES & SYSTEMS 2020年第7期14卷 995-1000页

作者： Godi, Prasanna Kumar Krishna, Battula Tirumala Kotipalli, Pushpa Jawaharlal Nehru Technol Univ Elect & Commun Engn Kakinada India Shri Vishnu Engn Coll Women Autonomous Elect & Commun Engn Bhimavaram India

Fast Fourier transform (FFT) is utilised to minimise the complexity of discrete Fourier transform by converting signals from frequency domain to time domain and conversely. Digital signal processing systems like image processing, general filtering, sonar, spread-spectrum communications and convolutions use this FFT operations. Radix-2 decimation in frequency (R2DIF) method is designed to execute an efficient FFT architecture in this study. Each and every state of the FFT stores the input and output the data using the R2DIF method. Also, the complex twiddle factors in FFT are replaced by the proposed uniform Montgomery algorithm. This technique simply performs the shift-add method instead of the multiplication process which also enhances the convergence of the calculation. So, the FFT implementation is done with the help of the proposed method which reduces the usage of chips in the process. Based on this approach, it performs the operation of FFT from 16 points to 1024 points and the performance of this proposed method is compared with existing approaches. Moreover, it does not require expensive dedicated functional blocks and uses only distributed logic resources. The simulation is carried out by the Xilinx platform using Verilog coding. The proposed design outperforms conventional methods in terms of less usage power and high speed.

关键词： discrete Fourier transforms hardware description languages pipeline processing digital signal processing chips fast Fourier transforms field programmable gate arrays mathematics computing design optimisation multiplier-free parallel field programmable gate array frequency domain time domain digital signal image processing general filtering spread-spectrum communications FFT operations radix-2 decimation frequency method efficient FFT architecture FFT stores R2DIF method complex twiddle factors uniform Montgomery algorithm shift-add method multiplication process FFT implementation

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Blur identification with assumption validation for sensor-based video reconstruction and its implementation on field programmable gate array

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IET COMPUTERS AND DIGITAL TECHNIQUES 2011年第4期5卷 271-286页

作者： Angelopoulou, M. E. Bouganis, C-S. Cheung, P. Y. K. Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn London SW7 2BT England

Restoration methods, such as super-resolution (SR), largely depend on the accuracy of the point spread function (PSF). PSF estimation is an ill-posed problem, and a linear and uniform motion is often assumed. In real-life systems, this may deviate significantly from the actual motion, impairing subsequent restoration. To address the above, this work proposes a dynamically configurable imaging system that combines algorithmic video enhancement, field programmable gate array (FPGA)-based video processing and adaptive image sensor technology. Specifically, a joint blur identification and validation (BIV) scheme is proposed, which validates the initial linear and uniform motion assumption. For the cases that significantly deviate from that assumption, the real-time reconfiguration property of an adaptive image sensor is utilised, and the sensor is locally reconfigured to larger pixels that produce higher frame-rate samples with reduced blur. Results demonstrate that once the sensor reconfiguration gives rise to a valid motion assumption, highly accurate PSFs are estimated, resulting in improved SR reconstruction quality. To enable real-time reconstruction, an FPGA-based BIV architecture is proposed. The system's throughput is significantly higher than 25 fps, for frame sizes up to 1024 x 1024, and its performance is robust to noise for signal-to-noise ratio (SNR) as low as 20 dB.

关键词： adaptive image sensor technology algorithmic video enhancement Video signal processing Logic and switching circuits point spread function imaging techniques autocorrelation-based blur identification framework Logic circuits image reconstruction sensor-based video reconstruction method field programmable gate arrays passive cameras Optical, image and video signal processing high-throughput hardware architecture Computer vision and image processing techniques image enhancement field programmable gate array image motion analysis joint blur identification and validation scheme Image sensors improved SR reconstruction quality image sensors system throughput signal-to-noise ratio

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Development and experimental validation of a real-time capable field programmable gate array-based gas exchange model for negative valve overlap

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INTERNATIONAL JOURNAL OF ENGINE RESEARCH 2020年第3期21卷 421-436页

作者： Gordon, David Wouters, Christian Wick, Maximilian Xia, Feihong Lehrheuer, Bastian Andert, Jakob Koch, Charles R. Pischinger, Stefan Univ Alberta Dept Mech Engn Edmonton AB T6G 2R3 Canada Eindhoven Univ Technol Dept Mech Engn Eindhoven Netherlands Rhein Westfal TH Aachen Mechatron Syst Combust Engines Aachen Germany Rhein Westfal TH Aachen Inst Combust Engines Aachen Germany

Homogeneous charge compression ignition has the potential to significantly reduce NOx emissions, while maintaining a high fuel efficiency. Homogeneous charge compression ignition is characterized by compression-induced autoignition of a lean homogeneous air-fuel mixture. Combustion timing is highly dependent on the in-cylinder state including pressure, temperature and trapped mass. To control homogeneous charge compression ignition combustion, it is necessary to have an accurate representation of the gas exchange process. Currently, microprocessor-based engine control units require that the gas exchange process is linearized around a desired operating point to simplify the model for real-time implementation. This reduces the models' ability to handle disturbances and limits the flexibility of the model. However, using a field programmable gate array, a detailed simulation of the physical gas exchange process can be implemented in real time. This paper outlines the process of converting physical governing equations to an offline zero-dimensional gas exchange model. The process used to convert this model to a field programmable gate array capable model is described. This model is experimentally validated using a single cylinder research engine with electromagnetic valves to record real-time field programmable gate array gas exchange results and comparing to the offline zero-dimensional physical model. The field programmable gate array model is able to accurately calculate the cylinder temperature and cylinder mass at 0.1 degrees CA intervals during the gas exchange process for a range of negative valve overlaps, boost conditions and engine speeds making the model useful for future real-time control applications.

关键词： field programmable gate array homogeneous charge compression ignition gasoline-controlled autoignition gas exchange model zero-dimensional engine simulation

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Design of Novel field programmable gate array-Based Hearing Aid

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IEEE ACCESS 2019年 7卷 63809-63817页

作者： Lin, Bor-Shing Yang, Po-Yu Liu, Ching-Feng Huang, Yi-Chia Liu, Chengyu Lin, Bor-Shyh Natl Taipei Univ Dept Comp Sci & Informat Engn New Taipei 23741 Taiwan Natl Chiao Tung Univ Inst Imaging & Biomed Photon Tainan 71150 Taiwan Chang Jung Christian Univ Chi Mei Med Ctr Dept Med Res Tainan 71004 Taiwan Southeast Univ Sch Instrument Sci & Engn Nanjing 210096 Jiangsu Peoples R China

Hearing loss is one of the most common chronic diseases. For people with hearing loss, communicating with other people, particularly in an environment with considerable background noise, is difficult. Recently, several hearing aids have been developed to improve speech comprehension in a noisy environment. The use of an adaptive beamformer is one of the alternative methods for improving speech intelligibility. However, the adaptive beamformer requires the location of the desired speaker to estimate the time differences of arrival (TDOAs) of speech sources to numerous spatially separated sensors in acoustics. In general, the technique of steered response power source localization was used to estimate the TDOA;however, this technique was easily affected by environmental reverberation. To overcome the aforementioned concern, a novel hearing aid is proposed in this paper. By using an image processing technology, the location of the desired speaker could be manually selected to provide precise information on the TDOA. Moreover, adaptive signal enhancements were implemented in a field-programmable gate array to enhance the speech of interest in real time. The experimental results indicate that the proposed system could improve speech intelligibility in various noisy environments. Therefore, the proposed system may be employed to improve the daily lives of people with hearing the loss in the future.

关键词： Hearing aid adaptive beamformer field programmable gate array time difference of arrival image processing technology

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Design and implementation of hydrogen economy using artificial neural network on field programmable gate array

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INTERNATIONAL JOURNAL OF HYDROGEN ENERGY 2020年第41期45卷 20709-20720页

作者： Koyuncu, Ismail Yilmaz, Ceyhun Alcin, Murat Tuna, Murat Afyon Kocatepe Univ Dept Elect Elect Engn TR-03200 Afyon Turkey Afyon Kocatepe Univ Dept Mech Engn TR-03200 Afyon Turkey Afyon Kocatepe Univ Dept Mechatron Engn TR-03200 Afyon Turkey Kirklareli Univ Dept Elect TR-39000 Kirklareli Turkey

In this study, economic analysis of the hydrogen generation and liquefaction system has been modeled using Multi-Layer Feed-Forward Artificial Neural Network (MLFFANN) and implemented on field programmable gate array (FPGA). Firstly, the 100X6 data set has been created to be used in the ANN-based modeling of the system using the Engineering Equation Solver (EES) program. This data set has been divided into two data sets as 80X6 for training and 20X6 for testing. The structure of the ANN-based economic analysis of hydrogen generation and liquefaction has been composed of 3 neurons in the input layer, ten neurons in the hidden layer, and three neurons in the output layer. Elliott-2-based TanSig transfer function and Purelin transfer function have been used in the neurons of the hidden layer and the output layer, respectively. Then, the ANN-model has been trained and tested using the Matlab program. The MSE values, 1.40x10E-7 and 2.07x10E-5, have been obtained as the results of the training phase and test phase of the ANN-based system, respectively. After getting fruitful results from training and testing phases, the economic analyses of hydrogen generation and liquation systems have been modeled in VHDL using bias and weight values located in the constructed ANN-based system using Matlab. The modeling has been performed in the Xilinx ISE Design Tools program using a 32-bit IEEE754-1985 floating-point number standard. Then, the modeled ANN-based economic analysis of the hydrogen generation and liquation system has been implemented on the Xilinx Virtex-7 FPGA chip by performing the Place&Route process. The maximum operating frequency of the ANN-based hydrogen generation and liquefaction economy system implemented on FPGA has been obtained as 281.702 MHz using Xilinx ISE Design Tools. (C) 2020 Hydrogen Energy Publications LLC. Published by Elsevier Ltd. All rights reserved.

关键词： Hydrogen production Hydrogen liquefaction Economic analysis Artificial neural networks field programmable gate array VHDL

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Decoupling of consecutive gasoline controlled auto-ignition combustion cycles by field programmable gate array based real-time cylinder pressure analysis

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INTERNATIONAL JOURNAL OF ENGINE RESEARCH 2018年第2期19卷 153-167页

作者： Wick, Maximilian Lehrheuer, Bastian Albin, Thivaharan Andert, Jakob Pischinger, Stefan Rhein Westfal TH Aachen Mechatron Syst Combust Engines Forckenbeckstr 4 D-52056 Aachen Germany Rhein Westfal TH Aachen Inst Combust Engines Aachen Germany Rhein Westfal TH Aachen Inst Automat Control Aachen Germany

Gasoline controlled auto-ignition combustion offers high potential for CO2 emission reduction, but faces challenges regarding combustion stability and high sensitivity to changing boundary conditions. Combustion chamber recirculation allows a wide operation range, but results in a strong coupling of consecutive cycles due to residuals that are transferred to the subsequent combustion cycle. The cycle coupling leads to phases of unstable operation with reduced efficiency and increased emission levels. State-of-the-art control algorithms use data-driven models of gasoline controlled autoignition combustion to achieve cycle-to-cycle control of the process or use offline calibration and optimization. A closed-loop control is proposed and implemented on a rapid control prototyping engine control unit. The control algorithm continuously calculates the current residual fuel in the combustion chamber. The heat release is observed and compared with the theoretical heat release of the injected fuel mass. The rate of unburned fuel mass transferred to the subsequent cycle is calculated offline by a detailed gas exchange model. Based on this information, the control algorithm adapts the injected fuel quantity for each cycle individually using an inverse injector model. In this article, a concept for decoupling consecutive cycles is presented to reduce the deviations of the indicated mean effective pressure and thus the heat release. Unstable sequences are analyzed in the time domain, and unburned residuals are identified as a strong correlating factor for consecutive cycles. Using real-time cylinder pressure analysis based on a field programmable gate array enables the online calculation of unburned residual fuel. Based on this calculation, the injection of each cycle can be adapted individually to decouple consecutive cycles and avoid unstable operation. The results of the control algorithm and the stabilization of the gasoline controlled auto-ignition combustion are validated

关键词： Gasoline controlled auto-ignition homogeneous charge compression ignition field programmable gate array cylinder pressure indication in-cycle control

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Low-power and area efficient binary coded decimal adder design using a look up table-based field programmable gate array

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IET CIRCUITS DEVICES & SYSTEMS 2016年第3期10卷 163-172页

作者： Sworna, Zarrin Tasnim UlHaque, Mubin Tara, Nazma Babu, Hafiz Md. Hasan Biswas, Ashis Kumar Univ Dhaka Dept Comp Sci & Engn Dhaka 1000 Bangladesh Univ Texas Arlington Dept Comp Sci & Engn Arlington TX 76019 USA

The binary coded decimal (BCD) system is suitable for digital communication, which can be designed by field programmable gate array (FPGA) technology, where look up table (LUT) is one of the major components of FPGA. In this study, the authors proposed a low power and area efficient LUT-based BCD adder which is constructed basically in three steps: First, a new technique is introduced for the BCD addition to obtain the correct BCD digit. Second, a new controller circuit of LUT is presented which is designed to select and send Read/Write voltage to memory cell for performing Read or Write operation. Finally, a compact BCD adder is designed using the proposed LUT. Their proposed 2-input LUT outperforms the existing best one providing 65.8% improvement in terms of area, 44.1% for Read operation and 43.5% for Write operation in power consumption. The proposed BCD adder using FPGA gains a radical achievement compared with the existing best-known LUT-based BCD adder providing prominent better performance of 65.6% in area and 48.3% less power consumption.

关键词： read operation BCD digit low-power electronics low-power area efficient binary coded decimal adder memory cell adders write operation table lookup BCD addition field programmable gate array binary codes 2-input LUT controller circuit power consumption field programmable gate arrays FPGA read-write voltage compact BCD adder look up table

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Diffuse Correlation Spectroscopy Analysis Implemented on a field programmable gate array

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IEEE ACCESS 2019年 7卷 122503-122512页

作者： Lin, Wei Busch, David R. Goh, Chia Chief Barsi, James Floyd, Thomas F. SUNY Stony Brook Dept Biomed Engn Stony Brook NY 11794 USA Univ Texas Southwestern Med Ctr Dallas Dept Anesthesiol & Pain Management Dallas TX 75390 USA SUNY Stony Brook Dept Orthoped Stony Brook NY 11794 USA

Diffusive correlation spectroscopy (DCS) is an emerging optical technique that measures blood perfusion in deep tissue. In a DCS measurement, temporal changes in the interference pattern of light, which has passed through tissue, are quantified by an autocorrelation function. This autocorrelation function is further parameterized through a non-linear curve fit to a solution to the diffusion equation for coherence transport. The computational load for this non-linear curve fitting is a barrier for deployment of DCS for clinical use, where real-time results, as well as instrument size and simplicity, are important considerations. We have mitigated this computational bottleneck through development of a hardware analyzer for DCS. This analyzer implements the DCS curving fitting algorithm on digital logic circuit using field programmable gate array (FPGA) technology. The FPGA analyzer is more efficient than a typical software analysis solution. The analyzer module can be easily duplicated for processing multiple channels of DCS data in real-time. We have demonstrated the utility of this analyzer in pre-clinical large animal studies of spinal cord ischemia. In combination with previously described FPGA implementations of auto-correlators, this hardware analyzer can provide a complete device-on-a-chip solution for DCS signal processing. Such a component will enable new DCS applications demanding mobility and real-time processing.

关键词： High performance computing field programmable gate array diffuse correlation spectroscopy

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