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A Fast and Accurate FPGA System for Short Read Mapping Based on Parallel Comparison on Hash Table

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 2017年第5期E100D卷 1016-1025页

作者： Sogabe, Yoko Maruyama, Tsutomu Univ Tsukuba Grad Sch Syst & Informat Engn Tsukuba Ibaraki 3058573 Japan

The purpose of DNA sequencing is to determine the order of nucleotides within a DNA molecule of target. The target DNA molecules are fragmented into short reads, which are short fixed-length subsequences composed of 'A', 'C', 'G' 'T', by next generation sequencing (NGS) machine. To reconstruct the target DNA from the short reads using a reference genome, which is a representative example of a species that was constructed in advance, it is necessary to determine their locations in the target DNA from where they have been extracted by aligning them onto the reference genome. This process is called short read mapping, and it is important to improve the performance of the short read mapping to realize fast DNA sequencing. We propose three types of FPGA acceleration methods based on hash table;(1) sorting and parallel comparison, (2) matching that allows one mutation to reduce the number of the candidates, (3) optimized hash function using variable masks. The first one reduces the number of accesses to off-chip memory to avoid the bottleneck by access latency. The second one enables to reduce the number of the candidates without degrading mapping sensitivity by allowing one mutation in the comparison. The last one reduces hash collisions using a table that was calculated from the reference genome in advance. We implemented the three methods on Xilinx Virtex-7 and evaluated them to show their effectiveness of them. In our experiments, our system achieves 20 fold of processing speed compared with BWA, which is one of the most popular mapping tools. Furthermore, we shows that the our system outperforms one of the fastest FPGA short read mapping systems.

关键词： field programmable gate array genome sequence alignment accelerated implementation bioinformatics

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An FPGA-Based electronic cochlea

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EURASIP JOURNAL ON APPLIED SIGNAL PROCESSING 2003年第7期2003卷 629-638页

作者： Leong, MP Jin, CT Leong, PHW Chinese Univ Hong Kong Dept Comp Sci & Engn Shatin Hong Kong Peoples R China Univ Sydney Dept Elect & Informat Engn Sydney NSW 2006 Australia

A module generator which can produce an FPGA-based implementation of an electronic cochlea filter with arbitrary precision is presented. Although hardware implementations of electronic cochlea models have traditionally used analog VLSI as the implementation medium due to their small area, high speed, and low power consumption, FPGA-based implementations offer shorter design times, improved dynamic range, higher accuracy, and a simpler computer interface. The tool presented takes filter coefficients as input and produces a synthesizable VHDL description of an application-optimized design as output. Furthermore, the tool can use simulation test vectors in order to determine the appropriate scaling of the fixed-point precision parameters for each filter. The resulting model can be used as an accelerator for research in audition or as the front-end for embedded auditory signal processing systems. The application of this module generator to a real-time cochleagram display is also presented.

关键词： field programmable gate array electronic cochlea VHDL modules

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Low power VLSI implementation of real fast Fourier transform with DRAM-VM-CLA

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MICROPROCESSORS AND MICROSYSTEMS 2019年第Sep.期69卷 92-100页

作者： Turaka, Rajasekhar Ram, Satya Sai M. Velagapudi Ramakrishna Siddhartha Engn Coll Dept Elect & Commun Engn Vijayawada Andhra Pradesh India RVR & JC Coll Engn Dept Elect & Commun Engn Guntur 522019 Andhra Pradesh India

In recent years, Fast Fourier Transform (FFT) plays a vital role in signal processing application for converting time domain to frequency domain. This paper presents Real FFT architecture which is implemented in radix-2 Decimation- in-Frequency (DIF). Instead of using more number of Random Access Memory (RAM), single Dual port RAM (DRAM) is used to store the intermediate data results. In Processing Element (PE), normal multiplier and adder has been used in previous works. In this paper, Vedic Multiplier (VM) and Carry Lookahead Adder (CLA) is used for improving the Real FFT operation and it is implemented in Verilog code. Application Specified Integrated Circuits (ASIC) and field programmable gate array (FPGA) performances are evaluated for all the architectures. In DRAM-VM-CLA architecture, LUT, flip flop, slices, and frequency are improved in FPGA performance as well as area, power, and delay are improved in ASIC performance. In ASIC 180 nm technology, 81.14% of area, 45.98% of delay, and 89.77% of Area Delay Product (ADP) is minimized in DRAM-VM-CLA as well as 72.64% of area, 5.44% of delay, and 74.10% of ADP is reduced in ASIC 45 nm technology. (C) 2019 Elsevier B.V. All rights reserved.

关键词： Application specified integrated circuits Carry lookahead adder Dual port RAM field programmable gate array Real FFT Vedic multiplier

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A parallel Viterbi decoder for block cyclic and convolution codes

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SIGNAL PROCESSING 2006年第2期86卷 273-278页

作者： Reeve, JS Amarasinghe, K Univ Southampton Dept Elect & Comp Sci Southampton SO17 1BJ Hants England

We present a parallel version of Viterbi's decoding procedure, for which we are able to demonstrate that the resultant task graph has restricted complexity in that the number of communications to or from any processor cannot exceed four for BCH codes. The resulting algorithm works in lock step making it suitable for implementation on a systolic processor array, which we have implemented on a field programmable gate array and have demonstrated the perfect scaling of the algorithm for two exemplar BCH codes. The parallelisation strategy is applicable to all cyclic codes and convolution codes. We also present a novel method for generating the state transition diagrams for these codes. (C) 2005 Elsevier B.V. All rights reserved.

关键词： Viterbi decoding BCH codes field programmable gate array parallel algorithms

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An Energy Efficient ECG Ventricular Ectopic Beat Classifier Using Binarized CNN for Edge AI Devices

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IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS 2022年第2期16卷 222-232页

作者： Wong, David Liang Tai Li, Yongfu Deepu, John Ho, Weng Khuen Heng, Chun-Huat Natl Univ Singapore Dept Elect & Comp Engn Singapore 117583 Singapore Shanghai Jiao Tong Univ Dept Micronano Elect Shanghai 200240 Peoples R China Shanghai Jiao Tong Univ MoE Key Lab Artificial Intelligence Shanghai 200240 Peoples R China Univ Coll Dublin Sch Elect & Elect Engn Dublin D04 V1W8 Ireland

Wearable Artificial Intelligence-of-Things (AIoT) requires edge devices to be resource and energy-efficient. In this paper, we design and implement an efficient binary convolutional neural network (bCNN) algorithm utilizing function-merging and block-reuse techniques to classify between Ventricular and non-Ventricular Ectopic Beat images. We deploy our model into a low-resource low-power field programmable gate array (FPGA) fabric. Our model achieves a classification accuracy of 97.3%, sensitivity of 91.3%, specificity of 98.1%, precision of 86.7%, and F1-score of 88.9%, along with dynamic power dissipation of only 10.5-mu W.

关键词： Electrocardiography Convolution Pregnancy Heart rate variability field programmable gate arrays Convolutional neural networks Image edge detection Artificial Intelligence-of-Things co-design convolutional neural network ECG field programmable gate array fusion inference low-power design wearable state machine

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Efficient FPGA based architecture for high-order FIR filtering using simultaneous DSP and LUT reduced utilization

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IET CIRCUITS DEVICES & SYSTEMS 2021年第5期15卷 475-484页

作者： Maamoun, Mountassar Hassani, Adnane Dahmani, Samir Saadi, Hocine Ait Zerari, Ghania Chabini, Noureddine Beguenane, Rachid Univ Blida Dept Elect LATSI Lab Blida Algeria ENS Kouba LSIC Lab Dept Phys Algiers Algeria Royal Mil Coll Canada Dept Elect & Comp Engn Kingston ON Canada

This paper proposes an efficient high-order finite impulse response (FIR) filter structure for field programmable gate array (FPGA)-based applications with simultaneous digital signal processing (DSP) and look-up-table (LUT) reduced utilization. The real-time updating of the filter coefficients is also put into perspective. In order to perform these objectives, both the speed and the structure of FPGA are efficiently exploited. The gap between the required input sampling frequency and the FPGA allowed maximum frequency is managed to achieve additional computing sequences. Furthermore, the special structures of the FPGA Look-up-table Shift-Register (LUT-SR) and their internal connections are fully employed for pipelining and selecting the input samples. The FPGA Block RAMs (BRAMs) are employed for handling the reconfigurable filter coefficients, and the FPGA DSP slices are associated for computing the output data of the BRAMs and the multiplexers. To synchronize the BRAM unit addressing with the LUT multiplexer selection, a single unit is used for simultaneous control. The obtained results show that the proposed reconfigurable 16-tap FIR filter offers reductions of 79.3% and 74.4% of slice utilization over the hybrid variable size partitioning (VP-Hybrid) based structure and the Radix-2(R) based structure, respectively when implemented on a Xilinx Spartan-6 XC6SLX45 FPGA. Moreover, an improvement of efficiency is achieved compared to all reputed FPGA-based architectures.

关键词： LUT-SR LUT multiplexer selection reputed FPGA-based architectures high-order FIR FIR filters special structures random-access storage simultaneous DSP efficient FPGA based architecture reconfigurable 16-tap FIR filter efficient high-order finite impulse response filter structure FPGA block RAM required input sampling frequency table lookup simultaneous digital signal processing high-order FIR filtering field programmable gate array LUT reduced utilization FPGA DSP slices field programmable gate arrays digital signal processing chips look-up-table reduced utilization reconfigurable filter coefficients Xilinx Spartan-6 XC6SLX45 FPGA BRAM unit addressing FPGA look-up-table shift-register

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Design of parallel conversion multichannel analog to digital converter for scan time reduction of programmable logic controller using FPGA

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COMPUTER STANDARDS & INTERFACES 2015年 39卷 12-21页

作者： Dhanabalan, G. Selvi, S. Tamil Kamaraj Coll Engn & Technol Dept Elect & Instrumentat Engn Spgc Nagar Virudhunagar India Natl Engn Coll Dept Elect & Commun Engn Kovilpatti India

The execution speed of a programmable logic controller (PLC) depends upon the number of analog and digital input it scans, complication in ladder diagram and the time to store the ladder diagram outputs in memory. Next to the ladder diagram, scanning of analog signals consume enough time as they have to be converted into digital. The two facts that limit the conversion speed is that the processor used for analog signal scanning can process only one channel at a time and the multichannel analog to digital converter (ADC) has digital output for only one channel. The hardware nature of field programmable gate array (FPGA) allows simultaneous conversion of all the analog signals into digital and storage of digital data in block RAM. The proposed design discusses the design of multichannel ADC using FPGA. The simulation result shows that the conversion time of 'n' channel ADC is 13.17 mu s. This increases the PLC execution speed. (C) 2014 Elsevier B.V. All rights reserved.

关键词： programmable logic controller Analog to digital converter Analog input module field programmable gate array Scan time

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Development of a re-configurable ambisonic decoder for irregular loudspeaker configuration

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IET CIRCUITS DEVICES & SYSTEMS 2009年第4期3卷 197-203页

作者： Tsang, P. W. M. Cheung, K. W. K. City Univ Hong Kong Dept Elect Engn Hong Kong Hong Kong Peoples R China

This study reports a heuristic genetic algorithm to determine the decoding parameters in a first-order ambisonic system for reconstructing a three-dimensional sound field with an arbitrary quad speaker configuration. On this basis, a hardware prototype has been developed using a field programmable gate array (FPGA) to decode ambisonic signals that are encoded in the standard B-format. To allow direct coupling with digital audio sources, the input and output channels of the decoder are implemented with the 12S interface. Evaluations reveal that the decoding parameters derived by this method are superior to existing approaches in terms of flexibility in loudspeaker configuration and optimisation of some of the essential factors in surround sound reconstruction.

关键词： first-order ambisonic system loudspeakers heuristic programming heuristic genetic algorithm standard B-format acoustic signal processing irregular loudspeaker configuration decoding arbitrary quad speaker configuration field programmable gate array digital audio sources reconfigurable architectures re-configurable ambisonic decoder encoding decoding parameters field programmable gate arrays signal reconstruction three-dimensional sound field genetic algorithms direct coupling hardware prototype acoustic field audio coding surround sound reconstruction

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Evaluation of Tradeoffs in the Design of FPGA Fabrics Using Electrostrictive 2-D FETs

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2021年第4期29卷 691-701页

作者： Baskaran, Saambhavi Sampson, Jack Penn State Univ Sch Elect Engn & Comp Sci Dept Comp Sci & Engn University Pk PA 16802 USA

The electrostrictive 2-D field-effect transistor (EFET) is a steep-slope device that promises to offer aggressive length and voltage scalability. Two key features of this device are its high-drive strength with high ON-OFF current ratio and the isolated back-gate terminal, which provides us the fourth knob to control the transistor drive strength. The disadvantage of the technology is the increased device capacitance incurred due to the additional piezoelectric layer in the transistor structure. Second, although the back-gate biasing of EFETs provides us the fourth knob of control, statically biasing the back gate increases the static power consumption. Despite the idiosyncrasies of the technology, this work shows the use of EFETs in field-programmable gate arrays (FPGAs) to be advantageous because the added energy cost of device capacitance gets amortized by the improvement in performance and energy efficiency of using high-drive EFET transistors in the FPGA interconnect architecture. We also show that co-optimization of back-bias voltage along with transduction efficiency is essential in the FPGA subcircuit level for achieving an energy-efficient architecture. This work highlights the specific design approach tradeoffs that differ from prior CMOS approaches and provides guidance for the engineering parameters necessary for EFETs to evolve as a competitive technology.

关键词： field programmable gate arrays Capacitance Logic gates Strain Photonic band gap Delays Routing Electrostrictive field-effect technology field programmable gate array integrated circuit technology beyond CMOS two-dimensional materials

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RF Drone Detection System Based on a Distributed Sensor Grid With Remote Hardware-Accelerated Signal Processing

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IEEE ACCESS 2023年 11卷 138759-138772页

作者： Flak, Przemyslaw Czyba, Roman Silesian Tech Univ Fac Automat Control Elect & Comp Sci Dept Automat Control & Robot PL-44100 Gliwice Poland Silesian Tech Univ Fac Automat Control Elect & Comp Sci Dept Automat Control & Robot PL-44100 Gliwice Poland

Unmanned Aerial Vehicles (UAVs), sometimes known as drones, evolved from military to civilian applications, opening up novel perspectives in a variety of everyday services. The rapidly growing consumer interest in amateur drones equipped with high-end cameras compromises the everyday safety and privacy of people. In the literature, a variety of sensing techniques based on different physical phenomena have been proposed for drone detection. Among acoustic, optical, or radar detection systems, passive radiofrequency sensing is the only one that can identify a drone even before it takes off and additionally indicate the operator's location. A spectrogram-based method is developed and optimised in terms of computing location, resulting in the possibility of sensor grid deployment over a standard Ethernet network. The detection phase involves hardware-accelerated energy sensing to extract the data frames from the background noise. Drone presence is then identified using machine learning based solely on preamble pattern recognition, which reduces the computational effort. The presented procedure is evaluated in an isolated setting employing an open-source dataset and tuned across multiple neural network architectures. Next, the complete sensor processing chain is examined in a real-life scenario. The analytical energy detector stage reaches a margin of roughly -8.7 dB in the signal-to-noise (SNR) ratio. With 1.1 M parameters, the proposed neural network achieves 99.93% simulation accuracy in up to -9.5 dB SNR range. Even after quantization for embedded platform implementation, the device can be used as a stand-alone early intrusion detector or as part of a distributed sensor grid.

关键词： Convolutional neural network drones field programmable gate array software defined radio spectrogram surveillance unmanned aerial vehicles

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