Tool-path generation is one of the most complex problems in computer-aided manufacturing. Although some efficient strategies have been developed to solve it, most of them are only useful for 3- and 5-axis standard mac...
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Tool-path generation is one of the most complex problems in computer-aided manufacturing. Although some efficient strategies have been developed to solve it, most of them are only useful for 3- and 5-axis standard machining. The algorithm called virtual digitising computes the tool path by means of a "virtually digitised" model of the surface and a geometry specification of the tool and its motion, so it can be used even in non-standard machining (retrofitting). This algorithm is simple, robust, and avoids the problem of tool-surface collision. However, its computing cost is high. Presented in the paper there is a virtual digitising optimisation that takes advantage of reconfigurable computing (using fieldprogrammablegates arrays) in order to improve the algorithm speed. A comparative study will show the gain and precision achieved.
There has been increased interest in the exploration of the Moon in recent years. Pinpoint precision landing is highly desirable for future lunar missions. This paper is concerned with the design of the on-board data ...
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There has been increased interest in the exploration of the Moon in recent years. Pinpoint precision landing is highly desirable for future lunar missions. This paper is concerned with the design of the on-board data handling (OBDH) subsystem for the pinpoint lunar lander of the Magnolia-1 project, funded by NASA. Four proposed on-board data handling architectures are outlined and compared in terms of power consumption, performance and reliability. Implementation results are presented, which are obtained from prototyping of the flight computer for the optimal OBDH architecture option on a Xilinx Virtex-5 field programmable gate array. (C) 2010 Elsevier Ltd. All rights reserved.
The mammalian spatial navigation system is characterized by an initial divergence of internal representations, with disparate classes of neurons responding to distinct features including location, speed, borders and h...
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The mammalian spatial navigation system is characterized by an initial divergence of internal representations, with disparate classes of neurons responding to distinct features including location, speed, borders and head direction;an ensuing convergence finally enables navigation and path integration. Here, we report the algorithmic and hardware implementation of biomimetic neural structures encompassing a feed-forward trimodular, multi-layer architecture representing grid-cell, place-cell and decoding modules for navigation. The grid-cell module comprised of neurons that fired in a grid-like pattern, and was built of distinct layers that constituted the dorsoventral span of the medial entorhinal cortex. Each layer was built as an independent continuous attractor network with distinct grid-field spatial scales. The place-cell module comprised of neurons that fired at one or few spatial locations, organized into different clusters based on convergent modular inputs from different grid-cell layers, replicating the gradient in place-field size along the hippocampal dorsoventral axis. The decoding module, a two-layer neural network that constitutes the convergence of the divergent representations in preceding modules, received inputs from the place-cell module and provided specific coordinates of the navigating object. After vital design optimizations involving all modules, we implemented the tri-modular structure on Zynq Ultrascale+ field-programmablegatearray silicon chip, and demonstrated its capacity in precisely estimating the navigational trajectory with minimal overall resource consumption involving a mere 2.92% Look Up Table utilization. Our implementation of a biomimetic, digital spatial navigation system is stable, reliable, reconfigurable, real-time with execution time of about 32 s for 100k input samples (in contrast to 40 minutes on Intel Core i7-7700 CPU with 8 cores clocking at 3.60 GHz) and thus can be deployed for autonomous-robotic navigation without
Markov Chain Monte Carlo (MCMC) based methods have been the main tool used for Bayesian Inference by practitioners and researchers due to their flexibility and theoretical properties that guarantee unbiased sampling-b...
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Markov Chain Monte Carlo (MCMC) based methods have been the main tool used for Bayesian Inference by practitioners and researchers due to their flexibility and theoretical properties that guarantee unbiased sampling-based estimates. Nevertheless, with the availability of large data sets and the constant need to develop more complex models that better capture the targeted problem, significant computational challenges have been presented. Current approaches, based on multi-core CPUs, GPUs, and FPGAs, aim to accelerate the execution time of the MCMC methods using subsampling techniques or custom precision arithmetic, resulting to biased estimates. In this work, a novel FPGA-based construction is proposed that utilises the custom precision support of FPGA devices in order to accelerate the computations, guaranteeing at the same time asymptotically unbiased estimates. Key to this approach is the extension of the parameter space by an extra parameter that indicates the required precision in the computation of the likelihood of a data point. The work proposes an FPGA architecture for the above algorithm, as well as discuss its tuning for maximising the performance of the system. The performance of the FPGA-mapped sampler is evaluated using two Bayesian logistic regression case studies of varying complexity, which show significant speedups compared to existing FPGA- and CPU-based works that utilise double floating point arithmetic, without any bias on the sampling-based estimates.
In this paper, we propose a target board architecture suitable for embedded signal processing applications based on hardware software codesign. The target board, which serves as a system attached to a host PC via a PC...
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In this paper, we propose a target board architecture suitable for embedded signal processing applications based on hardware software codesign. The target board, which serves as a system attached to a host PC via a PCI bus interface, contains a TMS320C30 DSP processor and up to four Xilinx XC5204 FPGAs. The software and hardware sections of the codesign can be easily implemented using C and VHDL programming in the C30 processor and FPGAs, respectively. Based on the proposed target board architecture, the interface circuitry and the communication protocols between the hardware (FPGAs) and software (C30) sections are first derived. The interface circuitry is described in VHDL code and will be added to the FPGA design for high level synthesis. Five types of HW/SW communications are supported. A HW/SW codesign flow is also exploited, and a partitioning verification procedure is developed. To illustrate the merits of the proposed system, a HW/SW codesign, implementation example based on the G.728 LD-CELP decoder for speech compression is described.
In this paper, we present a software framework that implements a formalized methodology for partitioning Digital Signal Processing applications between reconfigurable hardware blocks of different granularity. A hybrid...
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In this paper, we present a software framework that implements a formalized methodology for partitioning Digital Signal Processing applications between reconfigurable hardware blocks of different granularity. A hybrid generic reconfigurable architecture is considered, so that the methodology is applicable to a large variety of hybrid reconfigurable systems. The developed framework is composed of analysis, partitioning, and mapping tools. Although, the framework is parametrical in respect to the mapping procedures for the fine and coarse-grain reconfigurable units, we provide specific mapping algorithms for these types of hardware. In this work, the methodology is validated using five real-world digital signal processing applications;an orthogonal frequency division multiplexing transmitter, a cavity detector, a video compression technique, a JPEG encoder, and a wavelet-based image compressor. The experiments report that an average clock cycles decrease of 60.7%, relative to an all fine-grain mapping solution, is achieved using the developed framework for the considered applications. (c) 2006 Elsevier B.V. All rights reserved.
Computer vision applications rely upon high resolution images with extended depth of field (DoF). Most approaches contain arrays of lenses and computing intensive algorithms that must be calibrated every time, to reac...
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Computer vision applications rely upon high resolution images with extended depth of field (DoF). Most approaches contain arrays of lenses and computing intensive algorithms that must be calibrated every time, to reach in-focus images;however, by changing directly the system focal length, resolution and information are lost. Traditional methods consist in taking a great number of images varying the optical system pupil aperture, whereas, the post processing system demands a great amount of computational resources with long processing time and high implementation cost. In this work a novel methodology for DoF extension that applies a complex-amplitude mask during a single image pre-processing taken at full pupil aperture, and a Wiener filter for the image recovery without focalization errors, during post-processing, is introduced. An FPGA-based implementation shows the feasibility of the proposed methodology for real-time DoF extension. Obtained results demonstrate qualitatively and quantitatively the effectiveness of the proposed FPGA-based method, which offers a reconfigurable solution for online DoF extension on a single image, in real time. (C) 2017 Elsevier Inc. All rights reserved.
The main application of the filter bank in radar signal processing is the wideband digital channelized receiver. In order to save hardware resources of the field programmable gate array (FPGA), the efficient channeliz...
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The main application of the filter bank in radar signal processing is the wideband digital channelized receiver. In order to save hardware resources of the field programmable gate array (FPGA), the efficient channelized receiver structure using polyphase filter has been designed. However, when the number of channels is greatly increased or the transition bandwidth of the filter bank (FB) becomes very narrow, it still consumes large amounts of hardware resources. Therefore, a novel efficient channelized receiver structure based on frequency response masking (FRM) and modulation filter bank is proposed in this paper. The proposed novel structure has less computational complexity in implementing FB with narrow transition bandwidth (NTB). Compared with other efficient FRM-based structures, the proposed novel structure is more suitable for wideband digital channelization receiver. The proposed novel structure is verified correctly by Matlab simulation. The FPGA implementation of the polyphase channelized receiver structure and the proposed novel efficient FRM-based channelized receiver structure are completed by Xilinx System Generator. The result shows that the proposed novel efficient FRM-based channelized receiver structure can save 48.09% of the DSP48E1 hardware resources compared with the polyphase channelized receiver structure and has low group delay characteristic.
The paper deals with the accomplishment of a FPGA-based dynamic model of a three-phase Vienna rectifier controlled in order to feature unity power factor operations. Such a model has been developed for the Hardware In...
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The paper deals with the accomplishment of a FPGA-based dynamic model of a three-phase Vienna rectifier controlled in order to feature unity power factor operations. Such a model has been developed for the Hardware In the Loop (HIL) implementation of a test rig in which the power converter is replaced with an embedded system using a FPGA board. The proposed approach has been fostered mainly to test different converter control algorithms in a fast and safe way. Such solution is based on a software platform environment with a high-level abstraction that ensures a good trade-off between accuracy and hardware resources, also allowing a fast prototyping procedure. The results obtained by the HIL implementation have been compared with those of a fully hardware experimental rig, confirming a very good agreement in terms of accuracy and dynamic behavior.
The paper describes the design and training of a fuzzy neural network used for early diagnosis of a patient through an FPGA based implementation of a smart instrument. The system employs a fuzzy interface cascaded wit...
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The paper describes the design and training of a fuzzy neural network used for early diagnosis of a patient through an FPGA based implementation of a smart instrument. The system employs a fuzzy interface cascaded with a feed-forward neural network. In order to obtain an optimum decision regarding the future pathophysiological state of a patient, the optimal weights of the synapses between the neurons have been determined by using inverse delayed function model of neurons. The neurons that are considered in the proposed network are devoid of self connections instead of commonly used self connected neurons. The current work also find out the optimal number of neurons in the hidden layer for accurate diagnosis as against the available number of CLB in the FPGA. The system has been trained and tested with renal data of patients taken at 10 days interval of time. Applying the methodology, the chance of attainment of critical renal condition of a patient has been predicted with an accuracy of 95.2%, 30 days ahead of actually attaining the critical condition. The system has also been tested for pathophysiological state prediction of patients at multiple time steps ahead and the prediction at the next instant of time stands out to be the most accurate. (C) 2009 Elsevier Ltd. All rights reserved.
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