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Development of a re-configurable ambisonic decoder for irregular loudspeaker configuration

IET CIRCUITS DEVICES & SYSTEMS 2009年第4期3卷 197-203页

作者： Tsang, P. W. M. Cheung, K. W. K. City Univ Hong Kong Dept Elect Engn Hong Kong Hong Kong Peoples R China

This study reports a heuristic genetic algorithm to determine the decoding parameters in a first-order ambisonic system for reconstructing a three-dimensional sound field with an arbitrary quad speaker configuration. On this basis, a hardware prototype has been developed using a field programmable gate array (FPGA) to decode ambisonic signals that are encoded in the standard B-format. To allow direct coupling with digital audio sources, the input and output channels of the decoder are implemented with the 12S interface. Evaluations reveal that the decoding parameters derived by this method are superior to existing approaches in terms of flexibility in loudspeaker configuration and optimisation of some of the essential factors in surround sound reconstruction.

关键词： first-order ambisonic system loudspeakers heuristic programming heuristic genetic algorithm standard B-format acoustic signal processing irregular loudspeaker configuration decoding arbitrary quad speaker configuration field programmable gate array digital audio sources reconfigurable architectures re-configurable ambisonic decoder encoding decoding parameters field programmable gate arrays signal reconstruction three-dimensional sound field genetic algorithms direct coupling hardware prototype acoustic field audio coding surround sound reconstruction

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Design of parallel conversion multichannel analog to digital converter for scan time reduction of programmable logic controller using FPGA

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COMPUTER STANDARDS & INTERFACES 2015年 39卷 12-21页

作者： Dhanabalan, G. Selvi, S. Tamil Kamaraj Coll Engn & Technol Dept Elect & Instrumentat Engn Spgc Nagar Virudhunagar India Natl Engn Coll Dept Elect & Commun Engn Kovilpatti India

The execution speed of a programmable logic controller (PLC) depends upon the number of analog and digital input it scans, complication in ladder diagram and the time to store the ladder diagram outputs in memory. Next to the ladder diagram, scanning of analog signals consume enough time as they have to be converted into digital. The two facts that limit the conversion speed is that the processor used for analog signal scanning can process only one channel at a time and the multichannel analog to digital converter (ADC) has digital output for only one channel. The hardware nature of field programmable gate array (FPGA) allows simultaneous conversion of all the analog signals into digital and storage of digital data in block RAM. The proposed design discusses the design of multichannel ADC using FPGA. The simulation result shows that the conversion time of 'n' channel ADC is 13.17 mu s. This increases the PLC execution speed. (C) 2014 Elsevier B.V. All rights reserved.

关键词： programmable logic controller Analog to digital converter Analog input module field programmable gate array Scan time

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Evaluation of Tradeoffs in the Design of FPGA Fabrics Using Electrostrictive 2-D FETs

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2021年第4期29卷 691-701页

作者： Baskaran, Saambhavi Sampson, Jack Penn State Univ Sch Elect Engn & Comp Sci Dept Comp Sci & Engn University Pk PA 16802 USA

The electrostrictive 2-D field-effect transistor (EFET) is a steep-slope device that promises to offer aggressive length and voltage scalability. Two key features of this device are its high-drive strength with high ON-OFF current ratio and the isolated back-gate terminal, which provides us the fourth knob to control the transistor drive strength. The disadvantage of the technology is the increased device capacitance incurred due to the additional piezoelectric layer in the transistor structure. Second, although the back-gate biasing of EFETs provides us the fourth knob of control, statically biasing the back gate increases the static power consumption. Despite the idiosyncrasies of the technology, this work shows the use of EFETs in field-programmable gate arrays (FPGAs) to be advantageous because the added energy cost of device capacitance gets amortized by the improvement in performance and energy efficiency of using high-drive EFET transistors in the FPGA interconnect architecture. We also show that co-optimization of back-bias voltage along with transduction efficiency is essential in the FPGA subcircuit level for achieving an energy-efficient architecture. This work highlights the specific design approach tradeoffs that differ from prior CMOS approaches and provides guidance for the engineering parameters necessary for EFETs to evolve as a competitive technology.

关键词： field programmable gate arrays Capacitance Logic gates Strain Photonic band gap Delays Routing Electrostrictive field-effect technology field programmable gate array integrated circuit technology beyond CMOS two-dimensional materials

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RF Drone Detection System Based on a Distributed Sensor Grid With Remote Hardware-Accelerated Signal Processing

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IEEE ACCESS 2023年 11卷 138759-138772页

作者： Flak, Przemyslaw Czyba, Roman Silesian Tech Univ Fac Automat Control Elect & Comp Sci Dept Automat Control & Robot PL-44100 Gliwice Poland Silesian Tech Univ Fac Automat Control Elect & Comp Sci Dept Automat Control & Robot PL-44100 Gliwice Poland

Unmanned Aerial Vehicles (UAVs), sometimes known as drones, evolved from military to civilian applications, opening up novel perspectives in a variety of everyday services. The rapidly growing consumer interest in amateur drones equipped with high-end cameras compromises the everyday safety and privacy of people. In the literature, a variety of sensing techniques based on different physical phenomena have been proposed for drone detection. Among acoustic, optical, or radar detection systems, passive radiofrequency sensing is the only one that can identify a drone even before it takes off and additionally indicate the operator's location. A spectrogram-based method is developed and optimised in terms of computing location, resulting in the possibility of sensor grid deployment over a standard Ethernet network. The detection phase involves hardware-accelerated energy sensing to extract the data frames from the background noise. Drone presence is then identified using machine learning based solely on preamble pattern recognition, which reduces the computational effort. The presented procedure is evaluated in an isolated setting employing an open-source dataset and tuned across multiple neural network architectures. Next, the complete sensor processing chain is examined in a real-life scenario. The analytical energy detector stage reaches a margin of roughly -8.7 dB in the signal-to-noise (SNR) ratio. With 1.1 M parameters, the proposed neural network achieves 99.93% simulation accuracy in up to -9.5 dB SNR range. Even after quantization for embedded platform implementation, the device can be used as a stand-alone early intrusion detector or as part of a distributed sensor grid.

关键词： Convolutional neural network drones field programmable gate array software defined radio spectrogram surveillance unmanned aerial vehicles

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Reconfigurable computing for tool-path computation

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INTERNATIONAL JOURNAL OF ADVANCED MANUFACTURING TECHNOLOGY 2003年第12期21卷 945-951页

作者： Jimeno, A Cuenca, S Univ Alicante Comp Sci Technol & Computat Dept Alicante 03690 Spain

Tool-path generation is one of the most complex problems in computer-aided manufacturing. Although some efficient strategies have been developed to solve it, most of them are only useful for 3- and 5-axis standard machining. The algorithm called virtual digitising computes the tool path by means of a "virtually digitised" model of the surface and a geometry specification of the tool and its motion, so it can be used even in non-standard machining (retrofitting). This algorithm is simple, robust, and avoids the problem of tool-surface collision. However, its computing cost is high. Presented in the paper there is a virtual digitising optimisation that takes advantage of reconfigurable computing (using field programmable gates arrays) in order to improve the algorithm speed. A comparative study will show the gain and precision achieved.

关键词： field programmable gate array virtual digitising

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A novel autonomous low-cost on-board data handling architecture for a pin-point planetary lander

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ACTA ASTRONAUTICA 2011年第7-8期68卷 811-829页

作者： Vladimirova, Tanya Fayyaz, Muhammad Sweeting, Martin N. Vitanov, Valentin I. Univ Surrey Dept Elect Engn Surrey Space Ctr Guildford GU2 7XH Surrey England Univ Durham Sch Engn & Comp Sci Durham DH1 3LE England

There has been increased interest in the exploration of the Moon in recent years. Pinpoint precision landing is highly desirable for future lunar missions. This paper is concerned with the design of the on-board data handling (OBDH) subsystem for the pinpoint lunar lander of the Magnolia-1 project, funded by NASA. Four proposed on-board data handling architectures are outlined and compared in terms of power consumption, performance and reliability. Implementation results are presented, which are obtained from prototyping of the flight computer for the optimal OBDH architecture option on a Xilinx Virtex-5 field programmable gate array. (C) 2010 Elsevier Ltd. All rights reserved.

关键词： On-board data handling Pin-point planetary lander field programmable gate array

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Biomimetic FPGA-based spatial navigation model with grid cells and place cells

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NEURAL NETWORKS 2021年 139卷 45-63页

作者： Krishna, Adithya Mittal, Divyansh Virupaksha, Siri Garudanagiri Nair, Abhishek Ramdas Narayanan, Rishikesh Thakur, Chetan Singh Indian Inst Sci Dept Elect Syst Engn NeuRonICS Lab Bangalore 560012 Karnataka India Indian Inst Sci Mol Biophys Unit Cellular Neurophysiol Lab Bangalore 560012 Karnataka India

The mammalian spatial navigation system is characterized by an initial divergence of internal representations, with disparate classes of neurons responding to distinct features including location, speed, borders and head direction;an ensuing convergence finally enables navigation and path integration. Here, we report the algorithmic and hardware implementation of biomimetic neural structures encompassing a feed-forward trimodular, multi-layer architecture representing grid-cell, place-cell and decoding modules for navigation. The grid-cell module comprised of neurons that fired in a grid-like pattern, and was built of distinct layers that constituted the dorsoventral span of the medial entorhinal cortex. Each layer was built as an independent continuous attractor network with distinct grid-field spatial scales. The place-cell module comprised of neurons that fired at one or few spatial locations, organized into different clusters based on convergent modular inputs from different grid-cell layers, replicating the gradient in place-field size along the hippocampal dorsoventral axis. The decoding module, a two-layer neural network that constitutes the convergence of the divergent representations in preceding modules, received inputs from the place-cell module and provided specific coordinates of the navigating object. After vital design optimizations involving all modules, we implemented the tri-modular structure on Zynq Ultrascale+ field-programmable gate array silicon chip, and demonstrated its capacity in precisely estimating the navigational trajectory with minimal overall resource consumption involving a mere 2.92% Look Up Table utilization. Our implementation of a biomimetic, digital spatial navigation system is stable, reliable, reconfigurable, real-time with execution time of about 32 s for 100k input samples (in contrast to 40 minutes on Intel Core i7-7700 CPU with 8 cores clocking at 3.60 GHz) and thus can be deployed for autonomous-robotic navigation without

关键词： Path integration Autonomous robot navigation Time-multiplexing Continuous attractor network field programmable gate array Neuromorphic computing

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An Unbiased MCMC FPGA-Based Accelerator in the Land of Custom Precision Arithmetic

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IEEE TRANSACTIONS ON COMPUTERS 2017年第5期66卷 745-758页

作者： Liu, Shuanglong Mingas, Grigorios Bouganis, Christos-Savvas Imperial Coll Dept Elect & Elect Engn London SW7 2AZ England

Markov Chain Monte Carlo (MCMC) based methods have been the main tool used for Bayesian Inference by practitioners and researchers due to their flexibility and theoretical properties that guarantee unbiased sampling-based estimates. Nevertheless, with the availability of large data sets and the constant need to develop more complex models that better capture the targeted problem, significant computational challenges have been presented. Current approaches, based on multi-core CPUs, GPUs, and FPGAs, aim to accelerate the execution time of the MCMC methods using subsampling techniques or custom precision arithmetic, resulting to biased estimates. In this work, a novel FPGA-based construction is proposed that utilises the custom precision support of FPGA devices in order to accelerate the computations, guaranteeing at the same time asymptotically unbiased estimates. Key to this approach is the extension of the parameter space by an extra parameter that indicates the required precision in the computation of the likelihood of a data point. The work proposes an FPGA architecture for the above algorithm, as well as discuss its tuning for maximising the performance of the system. The performance of the FPGA-mapped sampler is evaluated using two Bayesian logistic regression case studies of varying complexity, which show significant speedups compared to existing FPGA- and CPU-based works that utilise double floating point arithmetic, without any bias on the sampling-based estimates.

关键词： field programmable gate array Markov chain Monte Carlo custom arithmetic precision logistic regression MNIST database

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Rapid prototyping of hardware/software codesign for embedded signal processing

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JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 1998年第3期14卷 605-632页

作者： Hwang, YT Wang, YH Hwang, JS Natl Yunlin Univ Sci & Technol Dept Elect Engn Yunlin 640 Taiwan

In this paper, we propose a target board architecture suitable for embedded signal processing applications based on hardware software codesign. The target board, which serves as a system attached to a host PC via a PCI bus interface, contains a TMS320C30 DSP processor and up to four Xilinx XC5204 FPGAs. The software and hardware sections of the codesign can be easily implemented using C and VHDL programming in the C30 processor and FPGAs, respectively. Based on the proposed target board architecture, the interface circuitry and the communication protocols between the hardware (FPGAs) and software (C30) sections are first derived. The interface circuitry is described in VHDL code and will be added to the FPGA design for high level synthesis. Five types of HW/SW communications are supported. A HW/SW codesign flow is also exploited, and a partitioning verification procedure is developed. To illustrate the merits of the proposed system, a HW/SW codesign, implementation example based on the G.728 LD-CELP decoder for speech compression is described.

关键词： hardware/software codesign communication interface embedded system hardware/software partitioning hardware description language target board rapid prototyping field programmable gate array

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Automated framework for partitioning DSP applications in hybrid reconfigurable platforms

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MICROPROCESSORS AND MICROSYSTEMS 2007年第1期31卷 1-14页

作者： Galanis, M. D. Milidonis, A. Theodoridis, G. Soudris, D. Goutis, C. E. Univ Patras VLSI Design Lab Elect & Comp Engn Dept Rion Greece Aristotle Univ Thessaloniki Dept Phys Sect Elect GR-54006 Thessaloniki Greece Democritus Univ VLSI Design Ctr Elect & Comp Engn Dept Xanthi Greece

In this paper, we present a software framework that implements a formalized methodology for partitioning Digital Signal Processing applications between reconfigurable hardware blocks of different granularity. A hybrid generic reconfigurable architecture is considered, so that the methodology is applicable to a large variety of hybrid reconfigurable systems. The developed framework is composed of analysis, partitioning, and mapping tools. Although, the framework is parametrical in respect to the mapping procedures for the fine and coarse-grain reconfigurable units, we provide specific mapping algorithms for these types of hardware. In this work, the methodology is validated using five real-world digital signal processing applications;an orthogonal frequency division multiplexing transmitter, a cavity detector, a video compression technique, a JPEG encoder, and a wavelet-based image compressor. The experiments report that an average clock cycles decrease of 60.7%, relative to an all fine-grain mapping solution, is achieved using the developed framework for the considered applications. (c) 2006 Elsevier B.V. All rights reserved.

关键词： hybrid reconfigurable platform partitioning methodology mapping analysis coarse-grain reconfigurable hardware field programmable gate array performance

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