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Modeling, simulation, and implementation issues of CPGs for neuromorphic engineering applications

COMPUTER APPLICATIONS IN ENGINEERING EDUCATION 2018年第4期26卷 782-803页

作者： Korkmaz, Nimet Ozturk, Ismail Kilic, Recai Erciyes Univ Dept Elect & Elect Engn TR-38039 Kayseri Turkey Amasya Univ Dept Elect & Elect Engn Amasya Turkey

Neuromorphic engineering is a discipline used to develop hardware, which can mimic the characteristics and abilities of biological systems by investigating their physiological structures and data transfer mechanisms. The recent studies about the neuromorphic systems mostly consist of robotic applications whose designs are inspired by Central Pattern Generators (CPGs). CPGs are special neural networks which can produce coordinated rhythmic activity patterns and these rhythmic movements are modeled mathematically, tested with simulation programs and verified by hardware implementations. A reconfigurable hardware platform (field programmable gate array FPGA) is compatible with numerical simulation tools, allows software control over hardware, has a user-friendly interface and allows real time modifications. Thus, recently, it is preferred in CPG based robotic applications. In this study, the details of the modeling, simulation and implementation stages of several CPG structures are introduced by using a digital reconfigurable hardware platform. In order to show the conceptual learning achievements of these stages and to assess the contribution to the modeling, simulation and implementation skills of the students, a training course has been planned for the undergraduate students at Erciyes University. This process has been held in an educative manner supported by a survey and an experimental examination, so that this training course has been evaluated by the trainees in terms of the advantage, practicality, and challenge.

关键词： Central Pattern Generators engineering education field programmable gate array neuromorphic engineering

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Generic systolic array for genetic algorithms

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IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 1997年第2期144卷 107-119页

作者： Megson, GM Bland, IM Laboratory of Chromatography DEPg.Fac.Quimica Universidad Nacional Autonoma de Mexico Circuito interior Cd Universitaria/CP 04510 Mexico D.F.Mexico

The authors present a systolic design for a simple GA mechanism which provides high throughput and unidirectional pipelining by exploiting the inherent parallelism in the genetic operators. The design computes in O(N + G) time steps using O(N-2) cells where N is the population size and G is the chromosome length. The area of the device is independent of the chromosome length and so can be easily scaled by replicating the arrays or by employing fine-grain migration. The array is generic in the sense that it does not rely on the fitness function and can be used as an accelerator for any GA application using uniform crossover between pairs of chromosomes. The design can also be used in hybrid systems as an complement existing designs and fitness function acceleration and island-style population management.

关键词： field programmable gate array optimisation algorithm systolic array

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Improved Algorithms and Implementations for Integer to τNAF Conversion for Koblitz Curves

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2018年第1期65卷 154-162页

作者： Li, Lijuan Li, Shuguo Tsinghua Univ Inst Microelect Beijing 100084 Peoples R China

The conversion from an integer scalar to a short and sparse tau-adic nonadjacent form (tau NAF) is crucial for efficient elliptic curve scalar multiplication over Koblitz curves. Currently the conversion is costly both in time and area, limiting the application of Koblitz curves. In this paper, we propose improved algorithms and implementations for both the single-digit and double-digit scalar conversions. Area reduction is achieved by removing the tau-and-add calculation of the remainder upon division by tau(m) for lazy reduction or the tau(2)-and-add one for the double lazy reduction. The tau NAF and the double tau NAF algorithms are modified accordingly to support a mixed-form-reduced scalar from the new reduction algorithms. Furthermore, fair pipelining is explored to speed up conversion with only a slight increase in area. Implementation results on Altera Stratix II FPGA show that the proposed single-digit converters are both smaller and faster than existing works, and the 4-stage pipelined one achieves at least 42.3% area reduction and 78.9% better area-time product (ATP) performance. On Xilinx Virtex IV, our non-pipelined double-digit converters are at least 44.5% smaller but slightly slower, while the 4-stage pipelined one can run faster with averagely 46.6% better ATP than previous equivalent works.

关键词： Elliptic curve cryptography Koblitz curves integer to tau NAF conversion lazy reduction field programmable gate array scalar multiplication

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Digital implementation of DS-SFH hybrid spread-spectrum modulation technique in three-phase voltage-source converter

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ELECTRICAL ENGINEERING 2022年第3期104卷 1413-1423页

作者： Alavanthan, Rajalakshmi Kavitha, A. Rajalakshmi Engn Coll Dept EEE Chennai 602105 Tamil Nadu India Coll Engn Guindy Dept EEE Chennai 600025 Tamil Nadu India

Random Pulse Width modulation (RPWM) technique is being used presently for producing gate pulses for power electronic circuits such as rectifiers, inverters, and choppers. But in recent times, Direct-Sequence Slow-Frequency Hopping (DS-SFH) Hybrid Spread-Spectrum modulation technique has been employed in military communication systems since it combines the advantages of two different modulation techniques, namely Direct Spread Spectrum Modulation and Frequency Hopping Spread Spectrum Modulation. This hybrid technique is now proposed for the first time, for the suppression of EMI and improvement of power quality in three-phase grid-connected bidirectional Voltage Source Converters. This digital modulation technique is implemented through a compact low-cost SPARTAN field programmable gate array by developing a suitable VHDL coding for producing the required switching pulses for the converter. A comparative analysis is also presented between the proposed DS-SFH hybrid modulation and the RPWM. It is shown that the implementation of DS-SFH results in reduced EMI, decreased Total Harmonic Distortion, and power factor is also improved significantly.

关键词： Three-phase bidirectional Voltage Source Converter Electromagnetic Interference Electromagnetic Compatibility Total Harmonic Distortion Power Quality Random Pulse Width Modulation Direct-Sequence Slow-Frequency Hopping Hybrid Spread-Spectrum Modulation field programmable gate array

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Abnormality Detection in Kidney Ultrasound Images by Various Classifiers with FPGA

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IETE JOURNAL OF RESEARCH 2023年第12期69卷 9278-9287页

作者： Vijayakumari, B. Rashmita, S. Mepco Schlenk Engn Coll Dept Elect & Commun Engn Sivakasi India

Ultrasound scanning has been used as the preliminary diagnosis tool all over the world. The ultrasound data are being analyzed by tele-radiologists. It lacks online availability. The drawbacks of tele-radiology have been overcome by using computer-aided diagnosis. As an aid to this, the Random Forest Classifier has been used here for detecting kidney abnormalities. The initial pre-processing stage filters the speckle noise existing in the input kidney image. Then feature extraction has been performed. Image categorization as normal, cyst and stone has been done with Random Forest Classifier. Then the performance is evaluated by comparing it with K-nearest neighbor classifier and support vector machine. From experimentation, it is observed that the accuracy and F-measure values of Random Forest Classifier range high when compared with other classifiers due to the continuous split of the trees until accurate categorization is done. Simulation and Implementation have been done using Modelsim 6.4a and Xilinx Spartan-6 FPGA board.

关键词： Block RAM Computer-aided design field programmable gate array K-nearest neighbor Random forest classifier Speckle

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A Fast Hardware Architecture for Integer to τNAF Conversion for Koblitz Curves

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IEEE TRANSACTIONS ON COMPUTERS 2012年第5期61卷 732-737页

作者： Adikari, Jithra Dimitrov, Vassil S. Jarvinen, Kimmo U. Univ Waterloo Dept Elect & Comp Engn Waterloo ON N2L 3G1 Canada Univ Calgary Dept Elect & Comp Engn Calgary AB T2N 1N4 Canada Aalto Univ Dept Informat & Comp Sci Sch Sci & Technol FI-00076 Aalto Finland

Scalar multiplication in elliptic curve cryptography is the most computational intensive operation. Efficiency of this operation can be significantly improved in hardware implementations by using Frobenius endomorphisms which require integer to tau-adic nonadjacent form conversion. Because conversion is one of the limiting factors in some of Koblitz curve-based cryptosystems, it has become an interesting problem. In this paper, we propose two algorithms and a novel hardware architecture to double the speed of integer to tau-adic nonadjacent form conversion.

关键词： Elliptic curve cryptography Koblitz curves integer to tau NAF conversion field programmable gate array application specific integrated circuit

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Design and evaluation of a low-cost multistatic netted radar system

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IET RADAR SONAR AND NAVIGATION 2007年第5期1卷 362-368页

作者： Derham, T. E. Doughty, S. Woodbridge, K. Baker, C. J. UCL Dept Elect & Elect Engn London WC1E 7JE England NHK Japan Broadcasting Corp Sci & Tech Res Labs Setagaya Ku Tokyo 1578510 Japan

This paper reports on the design and initial evaluation of a low-cost multistatic radar system that exploits digital components. The system is based on a commercial-off-the-shelf and open architecture approach, using a direct digital synthesiser, a field programmable gate array and a digital signal processor as core components. Instrument function testing, calibration and the results of the initial field tests are reported. Some of the first multistatic experimental results are reported and demonstrate a number of aspects of the performance of such a configuration. The advantages and limitations of a low-cost digital radar design are discussed and further system development possibilities outlined. This system will enable the collection of a wide range of novel multistatic data and has the potential to demonstrate a number of new radar applications.

关键词： field programmable gate arrays digital components field programmable gate array direct digital synthesiser low-cost multistatic netted radar system radar digital signal processor Radar and radionavigation low-cost digital radar design

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FPGA based Fuzzy Logic Controller for plasma position control in ADITYA Tokamak

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FUSION ENGINEERING AND DESIGN 2012年第11期87卷 1866-1871页

作者： Suratia, Pooja Patel, Jigneshkumar Rajpal, Rachana Kotia, Sorum Govindarajan, J. Maharaja Sayajirao Univ Baroda Fac Engn & Technol Dept Elect Engn Vadodara 390001 Gujarat India Inst Plasma Res Gandhinagar 382428 Gujarat India

Tokamaks are the most promising devices for obtaining nuclear fusion energy from high-temperature, ionized gas termed as Plasma. The successful operation of tokamak depends on its ability to confine plasma at the geometric center of vacuum vessel with sufficient stability. The quality of plasma discharge in ADITYA Tokamak is strongly related to the radial position of the plasma column in the vacuum vessel. If the plasma column approaches too near to the wall of vacuum vessel, it leads to minor or complete disruption of plasma. Hence the control of plasma position throughout the entire plasma discharge duration is a fundamental requirement. This paper describes Fuzzy Logic Controller (FLC) which is designed for radial plasma position control. This controller is tested and evaluated on the ADITYA RZIP control model. The performance of this FLC was compared with that of Proportional-Integral-Derivative (PID) Controller and the response was found to be faster and smoother. FLC was implemented on a field programmable gate array (FPGA) chip with the use of a Very High-Speed Integrated-Circuits Hardware Description-Language (VHDL). (C) 2012 Elsevier B.V. All rights reserved.

关键词： Fuzzy Logic Controller field programmable gate array Tokamak Plasma control

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A comparative analysis of 1-level multiplier-free discrete wavelet transform implementations on FPGAs

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2018年第5期26卷 2194-2205页

作者： Alzaq, Husam Ustundag, Burak Berk Istanbul Tech Univ Fac Comp Engn Dept Comp Engn Istanbul Turkey

In this article, we investigated the design and implementation aspects of multilevel discrete wavelet transform (DWT) by employing a finite impulse response filter on field programmable gate array platform. We presented two key multiplication-free architectures, namely, the distributed arithmetic algorithm (DAA) and residue number system (RNS). Our goal is to estimate the performance requirements and hardware resources for each approach, allowing for selection of the proper algorithm and implementation of multilevel DAA- and RNS-based DWT. The design has been implemented and synthesized in Xilinx Virtex 6 ML605, taking advantage of Virtex 6's embedded block RAMs. The results reveal that the DAA-based approach is appropriate for a small number of filter taps, while the RNS-based approach would be more appropriate for more than 10 filter taps, yet both DAA- and RNS-based approaches offer high signal quality with peak signal-to-noise ratio as 73.5 and 56.5 dB, respectively.

关键词： Discrete wavelet transform distributed arithmetic algorithm field programmable gate array residue number system

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Hierarchical Watermarking Method for FPGA IP Protection

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IETE TECHNICAL REVIEW 2013年第5期30卷 367-374页

作者： Nie, Tingyuan Zhou, Lijian Li, Yansheng Qingdao Technol Univ Commun & Elect Engn Inst Qingdao 266033 Peoples R China

With the increasing intellectual property (IP) abuse in System-on-a-Chip design, watermarking technique is playing an important role for IP protection. In this paper, we combine watermarking methods at different levels to construct a hierarchical watermarking scheme for field programmable gate array (FPGA) IP protection. We first embed the watermark into the netlist by using a look-up table-SRL transformation. Then we embed the watermark into the bitstream of the same design by using JBits. We test our method on three public FPGA benchmarks. The experimental results show that the overhead of watermarking is significantly reduced due to our judicious strategies. The watermark embedded at high level is well propagated to lower level. Our technique provides a robust and secure watermarking solution.

关键词： field programmable gate array IP protection Watermarking method

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