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Distributed Deep Learning With GPU-FPGA Heterogeneous Computing

IEEE MICRO 2021年第1期41卷 15-22页

作者： Tanaka, Kenji Arikawa, Yuki Ito, Tsuyoshi Morita, Kazutaka Nemoto, Naru Terada, Kazuhiko Teramoto, Junji Sakamoto, Takeshi NTT Corp NTT Device Technol Labs Atsugi Kanagawa 2430198 Japan NTT Corp NTT Software Innovat Ctr Tokyo 1808585 Japan

In distributed deep learning (DL), collective communication algorithms, such as Allreduce, used to share training results between graphical processing units (GPUs) are an inevitable bottleneck. We hypothesize that a cache access latency occurred at every Allreduce is a significant bottleneck in the current computational systems with high-bandwidth interconnects for distributed DL. To reduce this frequency of latency, it is important to aggregate data at the network interfaces. We implement a data aggregation circuit in a field-programmable gate array (FPGA). Using this FPGA, we proposed novel Allreduce architecture and training strategy without accuracy degradation. Results of the measurement show Allreduce latency reduction to 1/4. Our system can also conceal about 90% of the communication overhead and improve scalability by 20%. The end-to-end time consumed for training in distributed DL with ResNet-50 and ImageNet is reduced to 87.3% without any degradation in validation accuracy.

关键词： Cache Storage Data Aggregation Deep Learning Artificial Intelligence field programmable gate arrays Graphics Processing Units Neural Chips Distributed Deep Learning GPU FPGA Heterogeneous Computing Collective Communication Algorithms Graphical Processing Units Cache Access Latency High Bandwidth Interconnects Network Interfaces field programmable gate array Novel Allreduce Architecture Communication Overhead Distributed DL Training Strategy Allreduce Latency Reduction Res Net 50 Image Net field programmable gate arrays Random Access Memory Graphics Processing Units Training Data Distributed Databases Bandwidth Data Aggregation Deep Learning

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FPGA based Adaptive Lock-in Amplifier 19

FPGA based Adaptive Lock-in Amplifier

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19th IEEE-India-Council International Conference (INDICON)

作者： Aparna, A., V Sukumar, N. Sumathi, P. Indian Inst Technol Dept Elect Engn Roorkee 247667 Uttarakhand India

ISBN: (纸本)9781665473507

An adaptive Lock-in Amplifier (LIA), which works for sinusoidal signals in the frequency range of 9 - 11 kHz and an amplitude range of 0.3 - 10 V is being proposed. LIAs can extract useful signals from a very high noisy environment. For an adaptive LIA, the reference signal has to be generated by a phase locked loop (PLL) from the incoming signal. The phase and frequency error between the reference and input signals may reduce the accuracy of LIA system. To eliminate this error, a PLL with an enhanced phase detector is proposed. Using this quadrature PLL (QPLL), the accuracy of the LIA has effectively increased in the designed frequency range. The simulation results show that the proposed model can extract the amplitude of the signal buried in noise with a signal-to-noise ratio (SNR) as small as 10 dB and harmonics. The system-on-chip implementation of the adaptive LIA is carried out in the Altera Stratix III FPGA device. Testing the implementation for noise as well as harmonics have been performed in the designed frequency and amplitude range.

关键词： Adaptive Lock-in amplifier field programmable gate array Quadrature phase locked loop Phase detector

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Implementation of a GNSS Rebroadcaster in an All-programmable System-On-Chip Platform 10

Implementation of a GNSS Rebroadcaster in an All-Programmabl...

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10th Workshop on Satellite Navigation Technology (NAVITEC)

作者： Majoral, M. Arribas, J. Fernandez-Prades, C. CTTC CERCA Commun Syst Div Castelldefels Spain

ISBN: (纸本)9781665416160

This paper reports the design, proof-of-concept implementation and preliminary performance assessment of a lowcost, real-time, portable, low power, and small form factor GNSS rebroadcaster. This device can be used both as a GNSS signal generator and as a GNSS signal regenerator. This device can be used to test the addition of new features in GNSS signals, such as new signals for ranging, and to characterize the performance of new and existing spoofing countermeasures for GNSS receivers in real time. This device does not require the use of post-processed GNSS signals, enabling the testing with live signals, for instance in a vehicular test campaign replicating the correct dynamic and channel impairments.

关键词： Software-Defined Radio Embedded Software Signal processing Global Navigation Satellite System All programmable System-On-Chip field programmable gate array

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Fuzzy Logic Control for Solar PV Fed Modular Multilevel Inverter Towards Marine Water Pumping Applications

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IEEE ACCESS 2021年 9卷 88524-88534页

作者： Stonier, Albert Alexander Murugesan, Srinivasan Samikannu, Ravi Krishnamoorthy, Vinoth Subburaj, Senthil Kumar Chinnaraj, Gnanavel Mani, Geetha Kongu Engn Coll Dept Elect & Elect Engn Erode 638060 India Botswana Int Univ Sci & Technol Dept Elect Comp & Telecommun Engn Palapye Botswana Vel Tech Rangarajan Dr Sagunthala Res & Dev Inst Dept Elect & Elect Engn Chennai 600062 Tamil Nadu India New Prince Shri Bhavani Coll Engn & Technol Dept Elect & Elect Engn Chennai 600073 Tamil Nadu India AMET Deemed Univ Dept Elect & Elect Engn Chennai 603112 Tamil Nadu India Vellore Inst Technol Sch Elect Engn Vellore 632014 Tamil Nadu India

This paper presents the design and implementation of Modular Multilevel Inverter (MMI) to control the Induction Motor (IM) drive using intelligent techniques towards marine water pumping applications. The proposed inverter is of eleven levels and has the ability to control the speed of an IM drive which is fed from solar photovoltaics. It is estimated that the energy consumed by pumping schemes in an onboard ship is nearly 50% of the total energy. Considering this fact, this paper investigates and validates the proposed control design with reduced complexity intended for marine water pumping system employing an induction motor (IM) drive and MMI. The analysis of inverter is carried out with Proportional-Integral (PI) and Fuzzy Logic (FL) based controllers for improving the performance. A comparative analysis has been made with respect to better robustness in terms of peak overshoot, settling time of the controller and Total Harmonic Distortion (THD) of the inverter. Simulations are undertaken in MATLAB/Simulink and the detailed experimental implementation is conducted with field programmable gate array (FPGA). The results thus obtained are utilized to analyze the controller performance, improved inverter output voltage, reliable induction motor speed control and power quality improvement by reduction of harmonics. The novelty of the proposed control scheme is the design and integration of MMI, IM drive and intelligent controller exclusively for marine water pumping applications.

关键词： Marine vehicles Induction motors Multilevel inverters Power quality field programmable gate arrays Velocity control Topology field programmable gate array fuzzy logic controller induction motor drive modular multilevel inverter proportional-integral total harmonic distortion

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Energy efficient spiking neural network processing using approximate arithmetic units and variable precision weights

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JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 2021年 158卷 164-175页

作者： Wang, Yi Zhang, Hao Oh, Kwang-Il Lee, Jae-Jin Ko, Seok-Bum Univ Saskatchewan Dept Elect & Comp Engn 57 Campus Dr Saskatoon SK S7N 5A9 Canada ETRI SoC Design Res Grp Daejeon South Korea

Spiking neural networks (SNNs) have been getting more research attention in recent years as the way they process information is suitable for building neuromorphic systems effectively. However, realizing SNNs on hardware is computationally expensive. To improve their efficiency for hardware implementation, a field-programmable gate array (FPGA) based SNN accelerator architecture is proposed and implemented using approximate arithmetic units. To identify the minimal required bit-width for approximate computation without any performance loss, a variable precision method is utilized to represent weights of the SNN. Unlike the conventional reduced precision method applied to all weights uniformly, the proposed variable precision method allows different bit-widths to represent weights and provide the feasibility of maximizing truncation effort for each weight. Four SNNs adopting different network configurations and training datasets are established to compare the performance of proposed accelerator architecture using the variable precision method with the proposed one using the conventional reduced precision method. Based on the experimental results, more than 40% of the weights require less bit-width when applying the variable precision method instead of the reduced precision method. With the variable precision method, the proposed architecture achieves 28% fewer ALUTs and 29% less power consumption than the proposed one using the reduced precision method. (C) 2021 Elsevier Inc. All rights reserved.

关键词： Spiking neural network Approximate computing field programmable gate array Hardware accelerator

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A Low Area FPGA Implementation of Reversible gate Encryption with Heterogeneous Key Generation

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2021年第8期40卷 3836-3865页

作者： Saranya, K. Vijeyakumar, K. N. Dr Mahalingam Coll Engn & Technol Dept Elect & Elect Engn Coimbatore Tamil Nadu India Dr Mahalingam Coll Engn & Technol Dept Elect & Commun Engn Coimbatore Tamil Nadu India

The reversible computation is the process of designing the architecture with reversible logic gates (RLG) and applicable for optical computing, digital signal processing, nanotechnologies and low-power circuits. In this study, integer wavelet transform (IWT) compression technique is applied to the input image to compress the pixel value. The utilization of the IWT is used to improve the quality of the image in terms of peak signal-to-noise ratio (PSNR) and structural similarity index matrix (SSIM). In addition, different types of RLGs are used to perform the encryption and decryption of the images. A random number is generated using the Lorenz chaotic system (LCS) that contains three different stages and each stage is developed using arithmetic blocks. Here, an effective key value is generated from the input image values by connecting the LCS's output with the heterogeneous key generation (HKG) module. The inverse IWT (IIWT) technique is used to retrieve the original data during execution of decryption operation. Application specific integrated circuit and field-programmable gate array (FPGA) performances are calculated for reversible logic cryptographic design (RLCD) IWT-HKG architecture. The results showed that it has achieved better performance compared to conventional methods. Moreover, security analyses such as avalanche effect, side channel attack and session key agreement are performed for the RLCD-IWT-HKG method. The RLCD-IWT-HKG method has achieved 89 LUTs, 52 flip flops and 31 slices for the Virtex 6 FPGA device. After retrieving the decrypted images, values of PSNR and SSIM are evaluated as 39.90 dB and 0.6874, respectively.

关键词： Application specific integrated chip Avalanche effect field programmable gate array Integer wavelet transform Side channel attack

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Comparative Study on Dead-time Compensation for Improvement of Starting Characteristic in High Speed PMSM Drive System 25

Comparative Study on Dead-time Compensation for Improvement ...

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25th International Conference on Electrical Machines and Systems (ICEMS)

作者： Inoue, Yukinori Morimoto, Shigeo Sanada, Masayuki Osaka Metropolitan Univ Osaka Japan

ISBN: (纸本)9781665493024

This study focuses on a high-speed permanent magnet synchronous motor (PMSM) drive system based on direct torque control (DTC) implemented in a field programmable gate array (FPGA). DTC is difficult to start and operate in low speed region because of stator flux estimation based on time integration of the induced voltage. Voltage error due to dead time of the inverter affects estimation and control characteristics. This paper shows influence of dead-time compensation on starting characteristics of high speed PMSM.

关键词： direct torque control field programmable gate array high speed drives permanent magnet synchronous motor

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Drone Detection Sensor With Continuous 2.4 GHz ISM Band Coverage Based on Cost-Effective SDR Platform

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IEEE ACCESS 2021年 9卷 114574-114586页

作者： Flak, Przemyslaw Silesian Tech Univ Fac Automat Control Elect & Comp Sci PhD Sch Inst Automat Control PL-44100 Gliwice Poland

The development of Unmanned Aerial Vehicles (UAVs), commonly referred to as drones, has introduced revolutionary changes in many areas over the past few years. However, aside from opening new possibilities, the usage of drones in an irresponsible and dangerous manner leads to many hazardous incidents. This paper presents a drone detection sensor with a continuous 2.400 GHz-2.483 GHz operational frequency range for detection methods based on passive radio frequency imaging techniques. The implementation based on Software Defined Radio (SDR) and field programmable Logic array (FPGA) hardware that overcomes the 40 MHz real-time bandwidth limit of other popular SDRs is presented utilizing low-cost off-the-shelf components. Furthermore, a hardware realization of the signal processing chain for specific detection algorithms is proposed to minimize the throughput between SDR and the companion computer and offload software computations. The device validation is made in a laboratory and real-life scenario and presented in relation to the sensor used in other works. In addition to the increased real-time bandwidth, the measurements show a 9 dB reduction in detection sensitivity compared to the reference receiver, in line with the analog RF front-end specifications. The final analysis demonstrates the proposed device's relevance as a sensor for obtaining machine learning datasets and as a part of a final anti-drone system.

关键词： Drones Radio frequency Software field programmable gate arrays Bandwidth Hardware Universal Serial Bus Drones field programmable gate array software defined radio surveillance unmanned aerial vehicles

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Deep Convolutional Stack Autoencoder of Process Adaptive VMD Data With Robust Multikernel RVFLN for Power Quality Events Recognition

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2021年 70卷 1-12页

作者： Sahani, Mrutyunjaya Dash, Pradipta Kishore Siksha O Anusandhan Deemed To Be Univ Multidisciplinary Res Cell Bhubaneswar 751030 Odisha India

In this article, an improved particle swarm optimization (PSO)-based variational mode decomposition (VMD) is proposed to compute the most informative band-limited intrinsic mode function (BLIMF) of highly nonstationary single as well as combined power quality events (PQEs). A novel reduced deep convolutional neural network (RDCNN) embedded with stack autoencoder, that is, RDCSAE structure is introduced to extract the most discriminative unsupervised feature data by importing the selected BLIMF of parameter-adaptive VMD (PAVMD) algorithm. A supervised robust multikernel random vector functional link network (RMRVFLN) method is proposed to further train the unsupervised features combined with the deep convoluted Fourier privileged data for the recognition of complex PQEs accurately. Automatic computation of minimum overlapped descriptive features, unified complex feature learning framework, outstanding recognition accuracy, robust antinoise performance, and quick PQEs recognition time prove the superiority of the proposed PAVMD-RDCSAE-RMRVFLN method over RDCNN, PAVMD-RDCNN, PAVMD-RDCSAE, PAVMD-RDCNN-RMRVFLN, and PAVMD-RDCSAE-MRVFLN methods. Finally, the architecture of the proposed method is designed, implemented, and tested in a fast digital field-programmable gate array (FPGA) embedded processor to validate the feasibility, practicability, and performances for the online PQEs monitoring.

关键词： Autoencoder deep convolutional neural network (DCNN) field programmable gate array parameter adaptive variational mode decomposition (PAVMD) power quality analysis random vector functional link network

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FPGA-PLC-based multi-channel position measurement system

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ISA TRANSACTIONS 2021年 115卷 234-249页

作者： Patel, Dhruv M. Shah, Ankit K. Gujarat Technol Univ Instrumentat & Control Engn Ahmadabad Gujarat India Gujarat Technol Univ LD Coll Engn Instrumentat & Control Engn Dept Ahmadabad 380015 Gujarat India Gujarat Technol Univ Instrumentat & Control Engn Ahmadabad Gujarat India Sardar Vallabhbhai Patel Inst Technol SVIT Instrumentat & Control Engn Dept Vasad 388306 Gujarat India

The existing programmable Logic Controller (PLC) based on microprocessors (mu p) or micro-controllers (mu c) are commonly used in the industry for various instrumentation and control applications. PLC exhibits limitations such as less flexibility, poor scanning time, slower speed, and degraded response for high-speed industrial applications due to its fixed hardware and serial execution mechanism. A new field programmable gate array (FPGA) based PLC multi-channel High Speed Counter (HSC) module has been proposed, enhancing performance and flexibility compared to the existing PLC-HSC module. The proposed FPGA-PLC-HSC module has a 2-phase 2-Input counter with resolutions of 1X, 2X, and 4X which improve performance in terms of accuracy for position speed, and direction measurement applications. The FPGA-PLC-HSC module is implemented with the feedback node method and the shift register method inside LabVIEW FPGA along with device utilization. The simulation results show that the FPGA-PLC-HSC module has faster scanning time, good linearity, better resolution, maximum supporting input frequency, and counting frequency. For experimental purposes, an optical encoder M110960 (E8P 512 118 S D M B) with a signal conditioning circuit is connected to the NI-myRIO-1900 FPGA platform. The experimental results point out that the proposed FPGA-PLC-HSC module offers faster scanning time, better accuracy and linearity in 1X, 2X, and 4X resolution. (C) 2021 ISA. Published by Elsevier Ltd. All rights reserved.

关键词： programmable Logic Controller High speed phase counters field programmable gate array Position measurement

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