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A comparative analysis of 1-level multiplier-free discrete wavelet transform implementations on FPGAs

TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2018年第5期26卷 2194-2205页

作者： Alzaq, Husam Ustundag, Burak Berk Istanbul Tech Univ Fac Comp Engn Dept Comp Engn Istanbul Turkey

In this article, we investigated the design and implementation aspects of multilevel discrete wavelet transform (DWT) by employing a finite impulse response filter on field programmable gate array platform. We presented two key multiplication-free architectures, namely, the distributed arithmetic algorithm (DAA) and residue number system (RNS). Our goal is to estimate the performance requirements and hardware resources for each approach, allowing for selection of the proper algorithm and implementation of multilevel DAA- and RNS-based DWT. The design has been implemented and synthesized in Xilinx Virtex 6 ML605, taking advantage of Virtex 6's embedded block RAMs. The results reveal that the DAA-based approach is appropriate for a small number of filter taps, while the RNS-based approach would be more appropriate for more than 10 filter taps, yet both DAA- and RNS-based approaches offer high signal quality with peak signal-to-noise ratio as 73.5 and 56.5 dB, respectively.

关键词： Discrete wavelet transform distributed arithmetic algorithm field programmable gate array residue number system

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Design and evaluation of a low-cost multistatic netted radar system

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IET RADAR SONAR AND NAVIGATION 2007年第5期1卷 362-368页

作者： Derham, T. E. Doughty, S. Woodbridge, K. Baker, C. J. UCL Dept Elect & Elect Engn London WC1E 7JE England NHK Japan Broadcasting Corp Sci & Tech Res Labs Setagaya Ku Tokyo 1578510 Japan

This paper reports on the design and initial evaluation of a low-cost multistatic radar system that exploits digital components. The system is based on a commercial-off-the-shelf and open architecture approach, using a direct digital synthesiser, a field programmable gate array and a digital signal processor as core components. Instrument function testing, calibration and the results of the initial field tests are reported. Some of the first multistatic experimental results are reported and demonstrate a number of aspects of the performance of such a configuration. The advantages and limitations of a low-cost digital radar design are discussed and further system development possibilities outlined. This system will enable the collection of a wide range of novel multistatic data and has the potential to demonstrate a number of new radar applications.

关键词： field programmable gate arrays digital components field programmable gate array direct digital synthesiser low-cost multistatic netted radar system radar digital signal processor Radar and radionavigation low-cost digital radar design

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Hierarchical Watermarking Method for FPGA IP Protection

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IETE TECHNICAL REVIEW 2013年第5期30卷 367-374页

作者： Nie, Tingyuan Zhou, Lijian Li, Yansheng Qingdao Technol Univ Commun & Elect Engn Inst Qingdao 266033 Peoples R China

With the increasing intellectual property (IP) abuse in System-on-a-Chip design, watermarking technique is playing an important role for IP protection. In this paper, we combine watermarking methods at different levels to construct a hierarchical watermarking scheme for field programmable gate array (FPGA) IP protection. We first embed the watermark into the netlist by using a look-up table-SRL transformation. Then we embed the watermark into the bitstream of the same design by using JBits. We test our method on three public FPGA benchmarks. The experimental results show that the overhead of watermarking is significantly reduced due to our judicious strategies. The watermark embedded at high level is well propagated to lower level. Our technique provides a robust and secure watermarking solution.

关键词： field programmable gate array IP protection Watermarking method

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Area- and power-efficient iterative single/double-precision merged floating-point multiplier on FPGA

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IET COMPUTERS AND DIGITAL TECHNIQUES 2017年第4期11卷 149-158页

作者： Zhang, Hao Chen, Dongdong Ko, Seok-Bum Univ Saskatchewan Dept Elect & Comp Engn Saskatoon SK S7N 5A9 Canada Intel Corp San Jose CA USA

In this study, an area and power-efficient iterative floating-point (FP) multiplier architecture is designed and implemented on FPGA devices with pipelined architecture. The proposed multiplier supports both single-precision (SP) and double-precision (DP) operations. The operation mode can be switched during run time by changing the precision selection signal. The Karatsuba algorithm is applied when mapping the mantissa multiplier in order to reduce the number of digital signal processing (DSP) blocks required. For DP operations, the iterative method is applied which require much less hardware than a fully pipelined DP multiplier and thus reduces the power consumption. To further reduce the power consumption, the unused logic blocks for a specific operation mode are disabled. Compared to previous work, the proposed multiplier can achieve 33% reduction of DSP blocks, 4.3% less look-up tables (LUTs), and 31.2% less flip-flops while having 4% faster clock frequency on Virtex-5 devices. Compared to the intellectual property core DP multiplier provided by the FPGA vendors, the proposed multiplier required less DSP blocks and achieves lower-power consumption. The mapping solutions and implementation results of the proposed multiplier on Xilinx Virtex-7 and Altera Arria-10 devices are also presented. In addition, the results of a direct implementation of the proposed architecture on STM-90 nm ASIC platform are reported.

关键词： field programmable gate arrays floating point arithmetic iterative methods floating-point multiplication field programmable gate array DSP blocks power-efficient iterative FP multiplier architecture single-precision operations double-precision operations Karatsuba algorithm pipeline registers Virtex-5 devices Altera Arria-10 devices Xilinx Virtex-7 ASIC platform

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An efficient hybrid learning algorithm for neural network-based speech recognition systems on FPGA chip

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NEURAL COMPUTING & APPLICATIONS 2014年第7-8期24卷 1879-1885页

作者： Pan, Shing-Tai Lan, Min-Lun Natl Univ Kaohsiung Dept Comp Sci & Informat Engn Kaohsiung 811 Taiwan Shu Te Univ Inst Comp Sci & Informat Engn Kaohsiung 824 Taiwan

This paper implemented an artificial neural network (ANN) on a field programmable gate array (FPGA) chip for Mandarin speech measurement and recognition of nonspecific speaker. A three-layer hybrid learning algorithm (HLA), which combines genetic algorithm (GA) and steepest descent method, was proposed to fulfill a faster global search of optimal weights in ANN. Some other popular evolutionary algorithms, such as differential evolution, particle swarm optimization and improve GA, were compared to the proposed HLA. It can be seen that the proposed HLA algorithm outperforms the other algorithms. Finally, the designed system was implemented on an FPGA chip with an SOC architecture to measure and recognize the speech signals.

关键词： field programmable gate array Genetic algorithm Hybrid learning algorithm Speech recognition

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Analytic Model Predictive Controller for Collision-Free Relative Motion Reconfiguration

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JOURNAL OF GUIDANCE CONTROL AND DYNAMICS 2012年第4期35卷 1069-1079页

作者： Sauter, Luke Palmer, P. Univ Surrey Surrey Space Ctr Surrey GU2 7XH England

Large formations of satellites currently require extensive ground-based planning to enable formation-wide collision-free reconfiguration. Allowing satellite formations the flexibility to execute collision-free reconfiguration operations onboard each spacecraft can significantly reduce the ground operations burden and increase the responsiveness of the formation to reconfiguration events. An analytic model predictive controller for fuel-minimized, collision-free trajectory following is developed. The controller exploits the natural dynamics for relative-motion path-following using minimal fuel and requires a minimal computational burden. Constraints are handled implicitly and performance provides 423 times the fuel savings compared with traditional proportional-integral-derivative-type control at the same computational speed. Through hardware testing and comparison with other approaches, results also show that constraints can also be handled explicitly while still performing significantly faster than similar forms of model predictive control for formation reconfiguration.

关键词： Proportional Integral Derivative Monolithic Satellite Quadratic Programming Time Optimal Control Defense Advanced Research Projects Agencies Formation Flying Path Planning Central Processing Unit Fractionated Satellite Systems field programmable gate array

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Chip Implementation of Digital Scalar Space-vector Pulse Width Modulation for Induction Motor Drive

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ELECTRIC POWER COMPONENTS AND SYSTEMS 2011年第16期39卷 1733-1747页

作者： Sung, Guo-Ming Wang, Wei-Yu Hsieh, Hsiang-Yuan Natl Taipei Univ Technol Dept Elect Engn Taipei 10608 Taiwan Natl Taipei Univ Technol Grad Inst Mech & Elect Engn Taipei 10608 Taiwan

This article presents a digital integrated circuit for digital scalar space-vector pulse width modulation in a vector-controlled induction motor drive. All of the blocks, including input stage, calculation, read-only memory, sector decide, sector change, triangular estimation, voltage generator, and voltage transformation vector, are realized in a digital scalar space-vector pulse width modulation integrated circuit as a simple, convenient, high-speed, high-integration and low-cost solution. In the proposed digital scalar space-vector pulse width modulation chip, a feedback trigger signal is utilized to mitigate the problem of asynchronicity, and a four-bit fine tuner is employed to alleviate oscillation at low frequency.

关键词： induction motor field programmable gate array space-vector pulse-width modulation application-specific integrated circuit digital scalar control

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FPGA Implementation of Sparsity Independent Regularized Pursuit for Fast CS Reconstruction

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2022年第4期69卷 1617-1628页

作者： Thomas, Thomas James Rani, J. Sheeba Indian Inst Space Sci & Technol Dept Av Thiruvananthapuram 695547 Kerala India

Sparse recovery algorithms are integral to compressed sensing (CS) as they facilitate the reconstruction of higher dimensional signals from sub-Nyquist measurements. Although Orthogonal Matching Pursuit (OMP) has been ubiquitously adopted in hardware implementations to curb the computational complexity of CS recovery, increasing sparsity levels incur higher reconstruction costs. Sparsity independent regularized pursuit (SIRP) is a recent algorithm that employs parallel index selection and regularization to curtail the number of iterations required to reconstruct the signal and thereby enhance the reconstruction speed. This paper proposes a novel reformulation of the SIRP algorithm from the hardware perspective, incorporating a cheaper regularization strategy and a modified Gram-Schmidt (MGS) based incremental QR decomposition (QRD) approach. The proposed design incorporates an iterative QRD architecture with feedback circuitry to exploit the parallelism of the triangularization step in MGS. Additionally, a fast inverse square block circumvents the need for parallel divider blocks giving considerable hardware and latency savings. The design reuses the iterative QRD block to implement the interdependent computations of the algorithm by sophisticated scheduling techniques. The proposed implementation on a Xilinx Virtex Ultrascale FPGA can recover 1024-dimensional signals from 25% measurements within 77 mu s, which translates to a 37% reduction in processing cycles from state-of-art.

关键词： Matching pursuit algorithms field programmable gate arrays Hardware Indexes Computer architecture Estimation Costs Compressed sensing orthogonal matching pursuit QR decomposition modified Gram Schmidt field programmable gate array

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An accelerator for physics simulations

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COMPUTING IN SCIENCE & ENGINEERING 2007年第5期9卷 16-25页

作者： Danese, Giovanni Leporati, Francesco Bera, Marco Giachero, Mauro Nazzicari, Nelson Spelgatti, Alvaro Univ Pavia Fac Engn Pavia Italy

An accelerator based on field-programmable gate array (FPGA) technology accelerates double-precision floating-point operations present in the energy calculation of Monte Carlo-Metropolis simulations. The accelerator uses COTS components and is scalable in terms of clock frequency, memory capability, and number of computing units. It could also be part of a cluster of accelerated workstations.

关键词： Digital Simulation field programmable gate arrays Floating Point Arithmetic Monte Carlo Methods Physics Computing Workstation Clusters Accelerator Physics Simulations field programmable gate array Floating Point Operations Energy Calculation Monte Carlo Metropolis Simulations Clock Frequency Memory Capability Workstation Cluster COTS Computational Modeling field programmable gate arrays Computer Simulation Clocks Workstations Physics Computing Application Software Acceleration Hardware Circuit Simulation gate arrays Instruction Set Design Parallel Processors Monte Carlo Dynamics

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Low area FPGA implementation of modified histogram estimation architecture with CSAC-DPROM-OBC for medical image enhancement application

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INTERNATIONAL JOURNAL OF NANOTECHNOLOGY 2023年第1-4期20卷 259-280页

作者： Bonagiri, Koteswar Rao Kande, Giri Babu Reddy, P. Chandrasekhar Jawaharlal Nehru Technol Univ Dept Elect & Commun Engn Hyderabad 500085 India Marrilaxman Reddy Inst Technol & Management Domara Pocham Pally 500043 Telangana India Vasireddy Venkatadri Inst Technol Dept Elect & Commun Engn Namburu 522508 Andhrapradesh India

In this work, modified histogram estimation (MHE) architecture is proposed to verify the histogram count in the FPGA platform, and the Basic HE (BHE) architecture is also implemented for comparative purpose. The entire proposed MHE architecture is developed newly so as to reduce the logical elements involved in the HE process. In MHE architecture, dual port read only memory (DPROM), carry select adder based counter (CSAC), and Optimal Bin Counter (OBC) are used to evaluate the HE count with effective accuracy. The amount of percentage reduced by the 256 sample MHE is 17.62%, 15.41% and 23.01% for area, power and delay respectively. Additionally, the performance of the proposed MHE is compared with four existing methods HOG, HBS, MBPA and DMH. The number of flip flops utilised by the MHE architecture is 2177 for Vertex 6 device, which is less compared to the HOG and MBPA.

关键词： area basic histogram estimation CSAC carry select adder based counter delay DPROM dual port read only memory field programmable gate array medical image enhancement MHE modified histogram estimation optimal bin counter power

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