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Area- and power-efficient iterative single/double-precision merged floating-point multiplier on FPGA

IET COMPUTERS AND DIGITAL TECHNIQUES 2017年第4期11卷 149-158页

作者： Zhang, Hao Chen, Dongdong Ko, Seok-Bum Univ Saskatchewan Dept Elect & Comp Engn Saskatoon SK S7N 5A9 Canada Intel Corp San Jose CA USA

In this study, an area and power-efficient iterative floating-point (FP) multiplier architecture is designed and implemented on FPGA devices with pipelined architecture. The proposed multiplier supports both single-precision (SP) and double-precision (DP) operations. The operation mode can be switched during run time by changing the precision selection signal. The Karatsuba algorithm is applied when mapping the mantissa multiplier in order to reduce the number of digital signal processing (DSP) blocks required. For DP operations, the iterative method is applied which require much less hardware than a fully pipelined DP multiplier and thus reduces the power consumption. To further reduce the power consumption, the unused logic blocks for a specific operation mode are disabled. Compared to previous work, the proposed multiplier can achieve 33% reduction of DSP blocks, 4.3% less look-up tables (LUTs), and 31.2% less flip-flops while having 4% faster clock frequency on Virtex-5 devices. Compared to the intellectual property core DP multiplier provided by the FPGA vendors, the proposed multiplier required less DSP blocks and achieves lower-power consumption. The mapping solutions and implementation results of the proposed multiplier on Xilinx Virtex-7 and Altera Arria-10 devices are also presented. In addition, the results of a direct implementation of the proposed architecture on STM-90 nm ASIC platform are reported.

关键词： field programmable gate arrays floating point arithmetic iterative methods floating-point multiplication field programmable gate array DSP blocks power-efficient iterative FP multiplier architecture single-precision operations double-precision operations Karatsuba algorithm pipeline registers Virtex-5 devices Altera Arria-10 devices Xilinx Virtex-7 ASIC platform

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Analytic Model Predictive Controller for Collision-Free Relative Motion Reconfiguration

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JOURNAL OF GUIDANCE CONTROL AND DYNAMICS 2012年第4期35卷 1069-1079页

作者： Sauter, Luke Palmer, P. Univ Surrey Surrey Space Ctr Surrey GU2 7XH England

Large formations of satellites currently require extensive ground-based planning to enable formation-wide collision-free reconfiguration. Allowing satellite formations the flexibility to execute collision-free reconfiguration operations onboard each spacecraft can significantly reduce the ground operations burden and increase the responsiveness of the formation to reconfiguration events. An analytic model predictive controller for fuel-minimized, collision-free trajectory following is developed. The controller exploits the natural dynamics for relative-motion path-following using minimal fuel and requires a minimal computational burden. Constraints are handled implicitly and performance provides 423 times the fuel savings compared with traditional proportional-integral-derivative-type control at the same computational speed. Through hardware testing and comparison with other approaches, results also show that constraints can also be handled explicitly while still performing significantly faster than similar forms of model predictive control for formation reconfiguration.

关键词： Proportional Integral Derivative Monolithic Satellite Quadratic Programming Time Optimal Control Defense Advanced Research Projects Agencies Formation Flying Path Planning Central Processing Unit Fractionated Satellite Systems field programmable gate array

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An efficient hybrid learning algorithm for neural network-based speech recognition systems on FPGA chip

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NEURAL COMPUTING & APPLICATIONS 2014年第7-8期24卷 1879-1885页

作者： Pan, Shing-Tai Lan, Min-Lun Natl Univ Kaohsiung Dept Comp Sci & Informat Engn Kaohsiung 811 Taiwan Shu Te Univ Inst Comp Sci & Informat Engn Kaohsiung 824 Taiwan

This paper implemented an artificial neural network (ANN) on a field programmable gate array (FPGA) chip for Mandarin speech measurement and recognition of nonspecific speaker. A three-layer hybrid learning algorithm (HLA), which combines genetic algorithm (GA) and steepest descent method, was proposed to fulfill a faster global search of optimal weights in ANN. Some other popular evolutionary algorithms, such as differential evolution, particle swarm optimization and improve GA, were compared to the proposed HLA. It can be seen that the proposed HLA algorithm outperforms the other algorithms. Finally, the designed system was implemented on an FPGA chip with an SOC architecture to measure and recognize the speech signals.

关键词： field programmable gate array Genetic algorithm Hybrid learning algorithm Speech recognition

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Chip Implementation of Digital Scalar Space-vector Pulse Width Modulation for Induction Motor Drive

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ELECTRIC POWER COMPONENTS AND SYSTEMS 2011年第16期39卷 1733-1747页

作者： Sung, Guo-Ming Wang, Wei-Yu Hsieh, Hsiang-Yuan Natl Taipei Univ Technol Dept Elect Engn Taipei 10608 Taiwan Natl Taipei Univ Technol Grad Inst Mech & Elect Engn Taipei 10608 Taiwan

This article presents a digital integrated circuit for digital scalar space-vector pulse width modulation in a vector-controlled induction motor drive. All of the blocks, including input stage, calculation, read-only memory, sector decide, sector change, triangular estimation, voltage generator, and voltage transformation vector, are realized in a digital scalar space-vector pulse width modulation integrated circuit as a simple, convenient, high-speed, high-integration and low-cost solution. In the proposed digital scalar space-vector pulse width modulation chip, a feedback trigger signal is utilized to mitigate the problem of asynchronicity, and a four-bit fine tuner is employed to alleviate oscillation at low frequency.

关键词： induction motor field programmable gate array space-vector pulse-width modulation application-specific integrated circuit digital scalar control

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Very large scale integration architecture for block-matching motion estimation using adaptive rood pattern search algorithm

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IET CIRCUITS DEVICES & SYSTEMS 2016年第4期10卷 309-316页

作者： Puthenpurayil, Shiju Padmanabhan Chakrabarti, Indrajit Virdi, Rishi Kaushik, Harsh Indian Inst Technol Elect & Elect Commun Engn Dept Kharagpur 721302 W Bengal India

This study introduces an architecture for motion estimation block of the video encoder using adaptive rood pattern search (ARPS) algorithm. The architecture has been designed for field programmable gate array (FPGA) as well as application specific integrated circuit (ASIC) implementations. Experimental results show that the speed of ARPS algorithm is ahead of several existing fast motion estimation algorithms without compromising the peak signal-to-noise ratio values. The Virtex-4 FPGA implementation of the proposed architecture using Xilinx 14.2 attains a maximum frequency of 103 MHz with <3% usage of slices. ASIC implementation of the proposed architecture with Synopsys design vision tool (0.18 mu m) using 100 MHz frequency involves power consumption of 4.54 mW and occupies 0.073 mm(2). A maximum frequency of 333 MHz has been achieved for the ASIC implementation with 16 x 16 blocks and it can process 651 frames of slow motion video such as Akiyo and 280 frames of fast motion video such as Football of CIF format (352 x 288 resolution) per second. Moreover, the ASIC implementation can process up to 31 frames of HD (1920 x 1080 resolution) video per second. Hence, the proposed architecture fits well in applications such as video conferencing and video phones.

关键词： motion estimation image matching video coding search problems VLSI field programmable gate arrays application specific integrated circuits very large scale integration architecture adaptive rood pattern search algorithm block-matching motion estimation video encoder ARPS algorithm field programmable gate array application specific integrated circuit ASIC peak signal-to-noise ratio Virtex-4 FPGA Xilinx 14 2 Synopsys design vision tool size 0 18 mum frequency 100 MHz power 4 54 mW

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FPGA Implementation of Sparsity Independent Regularized Pursuit for Fast CS Reconstruction

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2022年第4期69卷 1617-1628页

作者： Thomas, Thomas James Rani, J. Sheeba Indian Inst Space Sci & Technol Dept Av Thiruvananthapuram 695547 Kerala India

Sparse recovery algorithms are integral to compressed sensing (CS) as they facilitate the reconstruction of higher dimensional signals from sub-Nyquist measurements. Although Orthogonal Matching Pursuit (OMP) has been ubiquitously adopted in hardware implementations to curb the computational complexity of CS recovery, increasing sparsity levels incur higher reconstruction costs. Sparsity independent regularized pursuit (SIRP) is a recent algorithm that employs parallel index selection and regularization to curtail the number of iterations required to reconstruct the signal and thereby enhance the reconstruction speed. This paper proposes a novel reformulation of the SIRP algorithm from the hardware perspective, incorporating a cheaper regularization strategy and a modified Gram-Schmidt (MGS) based incremental QR decomposition (QRD) approach. The proposed design incorporates an iterative QRD architecture with feedback circuitry to exploit the parallelism of the triangularization step in MGS. Additionally, a fast inverse square block circumvents the need for parallel divider blocks giving considerable hardware and latency savings. The design reuses the iterative QRD block to implement the interdependent computations of the algorithm by sophisticated scheduling techniques. The proposed implementation on a Xilinx Virtex Ultrascale FPGA can recover 1024-dimensional signals from 25% measurements within 77 mu s, which translates to a 37% reduction in processing cycles from state-of-art.

关键词： Matching pursuit algorithms field programmable gate arrays Hardware Indexes Computer architecture Estimation Costs Compressed sensing orthogonal matching pursuit QR decomposition modified Gram Schmidt field programmable gate array

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An accelerator for physics simulations

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COMPUTING IN SCIENCE & ENGINEERING 2007年第5期9卷 16-25页

作者： Danese, Giovanni Leporati, Francesco Bera, Marco Giachero, Mauro Nazzicari, Nelson Spelgatti, Alvaro Univ Pavia Fac Engn Pavia Italy

An accelerator based on field-programmable gate array (FPGA) technology accelerates double-precision floating-point operations present in the energy calculation of Monte Carlo-Metropolis simulations. The accelerator uses COTS components and is scalable in terms of clock frequency, memory capability, and number of computing units. It could also be part of a cluster of accelerated workstations.

关键词： Digital Simulation field programmable gate arrays Floating Point Arithmetic Monte Carlo Methods Physics Computing Workstation Clusters Accelerator Physics Simulations field programmable gate array Floating Point Operations Energy Calculation Monte Carlo Metropolis Simulations Clock Frequency Memory Capability Workstation Cluster COTS Computational Modeling field programmable gate arrays Computer Simulation Clocks Workstations Physics Computing Application Software Acceleration Hardware Circuit Simulation gate arrays Instruction Set Design Parallel Processors Monte Carlo Dynamics

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Low area FPGA implementation of modified histogram estimation architecture with CSAC-DPROM-OBC for medical image enhancement application

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INTERNATIONAL JOURNAL OF NANOTECHNOLOGY 2023年第1-4期20卷 259-280页

作者： Bonagiri, Koteswar Rao Kande, Giri Babu Reddy, P. Chandrasekhar Jawaharlal Nehru Technol Univ Dept Elect & Commun Engn Hyderabad 500085 India Marrilaxman Reddy Inst Technol & Management Domara Pocham Pally 500043 Telangana India Vasireddy Venkatadri Inst Technol Dept Elect & Commun Engn Namburu 522508 Andhrapradesh India

In this work, modified histogram estimation (MHE) architecture is proposed to verify the histogram count in the FPGA platform, and the Basic HE (BHE) architecture is also implemented for comparative purpose. The entire proposed MHE architecture is developed newly so as to reduce the logical elements involved in the HE process. In MHE architecture, dual port read only memory (DPROM), carry select adder based counter (CSAC), and Optimal Bin Counter (OBC) are used to evaluate the HE count with effective accuracy. The amount of percentage reduced by the 256 sample MHE is 17.62%, 15.41% and 23.01% for area, power and delay respectively. Additionally, the performance of the proposed MHE is compared with four existing methods HOG, HBS, MBPA and DMH. The number of flip flops utilised by the MHE architecture is 2177 for Vertex 6 device, which is less compared to the HOG and MBPA.

关键词： area basic histogram estimation CSAC carry select adder based counter delay DPROM dual port read only memory field programmable gate array medical image enhancement MHE modified histogram estimation optimal bin counter power

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An experimental investigation on a multilevel inverter for solar energy applications

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INTERNATIONAL JOURNAL OF ELECTRICAL POWER & ENERGY SYSTEMS 2013年第1期47卷 157-167页

作者： Chinnaiyan, Venkatachalam Kumar Jerome, Jovitha Karpagam, J. Dr NGP Inst Technol Dept Elect & Elect Engn Coimbatore 641048 Tamil Nadu India PSG Coll Technol Dept Instrumentat & Control Syst Engn Coimbatore 641004 Tamil Nadu India Dr NGP Inst Technol Dept Elect & Commun Engn Coimbatore 641048 Tamil Nadu India

The main objective of the proposed work is to design, develop and test a three phase multilevel inverter with the modern power electronic switches to reduce the power quality issues in solar power conversion system. Due to the increased usage of power electronic converters for processing the power in all walks of our life, the power quality problem become the hot research topic in the recent years. As the power level increases, the voltage level is increased accordingly to obtain satisfactory efficiency. The multilevel power converter has shown growing popularity. The fundamental advantages of multilevel converter topologies are low distorted output waveforms and limited voltage stress on the switching devices and hence the reduced electromagnetic interferences. The main disadvantages are higher complexity and more difficult control;it can be overcome by using modern digital controllers. In this paper, the performance parameters are analyzed with the developed prototype of the three phase cascaded multilevel inverter for solar energy conversion designed with digital controller for reduced power quality issues with three phase AC motor drive. The main objective is to obtain the better quality of output waveform on the inverter output with suitable control strategy on the experimental hardware setup. (c) 2012 Elsevier Ltd. All rights reserved.

关键词： Inverters Power electronics Solar energy Drives Power converters Multi level inverter field programmable gate array

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FPGA implementation of adaptive segmentation for non-stationary biomedical signals

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IET CIRCUITS DEVICES & SYSTEMS 2010年第3期4卷 239-250页

作者： Jiao, B. Krishnan, S. Kabbani, A. Ryerson Univ Dept Elect & Comp Engn Toronto ON Canada

A novel field programmable gate array (FPGA) implementation of adaptive segmentation for non-stationary biomedical signals is presented. The design uses Simulink-to-FPGA methodology and has been successfully implemented onto Xilinx Virtex II Pro device. The implementation is based on the recursive least-squares lattice (RLSL) algorithm using double-precision floating-point arithmetic and is programmable for users providing data length, system order and threshold selection functions. The implemented RLSL design provides very good performance in obtaining accurate conversion factor values with a mean correlation above 99% and detecting segment boundaries with high accuracy for both synthesised and real-world biomedical signals.

关键词： nonstationary biomedical signals recursive least-squares lattice algorithm segment boundary detection medical signal processing least squares approximations Simulink-to-FPGA methodology adaptive segmentation field programmable gate array double-precision floating-point arithmetic field programmable gate arrays

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