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Fast OMP algorithm and its FPGA implementation for compressed sensing-based sparse signal acquisition systems

IET CIRCUITS DEVICES & SYSTEMS 2021年第6期15卷 511-521页

作者： Roy, Shirshendu Acharya, Debiprasad P. Sahoo, Ajit K. Natl Inst Technol Elect & Commun Rourkela Odisha India

Compressed sensing-based radio frequency signal acquisition systems call for higher reconstruction speed and low dynamic power. In this study, a novel low power fast orthogonal matching pursuit (LPF-OMP) algorithm is proposed for faster reconstruction of sparse signals from their compressively sensed samples and the reconstruction circuit consumes very low dynamic power. The searching time to find the best column is reduced by reducing the number of columns to be searched in successive iterations. A novel architecture of the proposed LPF-OMP algorithm is also presented here. The proposed architecture is implemented on field programmable gate array for demonstrating the performance enhancement. Computation of pseudoinverse in OMP is avoided to save time and storage requirement to store the pseudoinverse matrix. The proposed design incorporates a novel strategy to stop the algorithm without consuming any extra circuitry. A case study is carried out to reconstruct the RADAR test pulses. The design is implemented for K = 256, N = 1024 using XILINX Virtex6 device and supports maximum of K/4 iterations. The proposed design is faster, hardware efficient and consumes very less dynamic power than the previous implementations of OMP. In addition, the proposed implementation proves to be efficient in reconstructing low sparse signals.

关键词： LPF-OMP algorithm searching time compressed sensing compressed sensing-based radio frequency signal acquisition systems field programmable gate array signal detection low sparse signals compressively sensed samples logic design reconstruction circuit faster reconstruction compressed sensing-based sparse signal acquisition systems storage requirement low dynamic power higher reconstruction speed field programmable gate arrays low-pass filters image reconstruction FPGA implementation low power fast orthogonal matching pursuit fast OMP algorithm

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Improving security against cache memory attacks for dual field multiplier design based on elliptic curve cryptography

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JOURNAL OF AMBIENT INTELLIGENCE AND HUMANIZED COMPUTING 2021年 1-13页

作者： Sai, R. Vijay Upadhyay, Har Narayan SASTRA Deemed Univ Sch Comp Thanjavur Tamil Nadu India SASTRA Deemed Univ Sch Elect & Elect Engn Thanjavur Tamil Nadu India

The elliptic curve cryptographic (ECC) technique is employed for various security standards like security key management, digital signature and data authentication. The ECC technique is capable of undertaking sequential and equivalent mode processes through the unified design that is used equally for binary field and in the leading area of cryptosystems. Furthermore, a progressive transposition method and control information route are combined with the ECC mainframe, which offers efficient throughput, and adaptive calculation with low power. The dual-field Montgomery multiplier-carry save adder (DMM-CSA) structure is designed for the ECC system. The DMM structure has been developed using CSA in this method. The adder requires more number of Full Adders for the circuit design, which has occupied more area. To overcome this problem, this work introduces the dual field Vedic multiplier-look up table carry select adder (DVM-LCSLA) which is used to increase the performance of the ECC scheme for 256 bit. The first aim of the methods mentioned above is to develop a high-performance modular inversion for the ECC technique by employing application specified integrated chip and field programmable gate array (FPGA) implementation with the help of Verilog code. FPGA results indicate the analysis of power utilization, time delay information and Hardware area overhead in DVM-LCSLA used in ECC system compared to the state-of-art methods.

关键词： Application specified integrated circuit Dual-field Vedic multiplier Elliptic curve cryptography field programmable gate array Lookup table carry select adder

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FPGA application for wireless monitoring in power plant

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NUCLEAR ENGINEERING AND TECHNOLOGY 2021年第4期53卷 1167-1175页

作者： Kumar, Adesh Bansal, Kamal Kumar, Deepak Devrari, Aakanksha Kumar, Roushan Mani, Prashant Univ Petr & Energy Studies UPES Sch Engn Dept Elect & Elect Engn Dehra Dun Uttarakhand India Uttaratech Polytech Roorkee Uttar Pradesh India Univ Petr & Energy Studies UPES Dept Mech Engn Sch Engn Dehra Dun Uttarakhand India SRM Inst Sci & Technol Fac Engn & Technol Dept Elect & Commun Engn NCR CampusDelhi Meerut Rd Modinagar UP India

The process of automation and monitoring in industrial control system involves the use of many types of sensors. A programmable logic controller plays an important role in the automation of the different processes in the power plant system. The major control units are boiler for temperature and pressure, turbine for speed of motor, generator for voltage, conveyer belt for fuel. The power plant units are controlled using microcontrollers and PLCs, but FPGA can be the feasible solution. The paper focused on the design and simulation of hardware chip to monitor boiler, turbine, generator and conveyer belt. The hardware chip of the plant is designed in Xilinx Vivado Simulator 17.4 software using VHDL programming. The methodology includes VHDL code design, simulation, verification and testing on Virtex-5 FPGA hardware. The system has four independent buzzers used to indicate the status of the boiler, generator, turbine motor and conveyer belt in on/off conditions respectively. The GSM is used to display corresponding message on the mobile to know the status of the device in on/off condition. The system is very much helpful for the industries working on plant automation with FPGA hardware integration. (c) 2020 Korean Nuclear Society, Published by Elsevier Korea LLC. This is an open access article under the CC BY-NC-ND license (http://***/licenses/by-nc-nd/4.0/).

关键词： Power plant field programmable gate array VHDL programming Wireless monitoring

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Design, FEM analysis and development of switched reluctance motor electric drive for TRI-wheeler E-vehicle application

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AUTOMATIKA 2024年第3期65卷 813-829页

作者： Anand, M. Jebarani Evangeline, S. Deva Priya, W. Chitra Selvi, S. PSG Coll Technol Dept Elect & Elect Engn Coimbatore India SNS Coll Engn Dept Elect & Elect Engn Coimbatore India Saveetha Univ Saveetha Inst Med & Tech Sci SIMATS Univ Saveetha Sch Engn Dept Comp Sci & Engn Chennai India Anna Univ Chennai Univ Coll Engn Dindigul Constituent Coll Dept Elect & Elect Engn Dindigul India PSG Coll Technol Dept Elect & Elect Engn Coimbatore Tamilnadu India

Electric vehicles have seen substantial growth in recent years in the emerging economies of the world. The current market scenario of E-vehicles is dominated by PMSM or BLDC motors due to their higher torque-to-power density, and efficiency with added performance metrics of the motor. However, the higher capital cost of permanent magnets makes the motor designers to consider an alternative to magnetic motors, the so-called Switched Reluctance Motors (SRM). With proper FEM analysis and controller design, if SRMs can able to achieve the performance metrics of a PMSM/BLDC, it will be a breakthrough in the automotive sector with affordable prices. Based on the aforementioned facts, this research work focuses on SRM as a viable alternative to the existing PMSM/BLDC motor. The work concentrates on the design and development of an 8/6 SRM for a Tri-wheeler E-vehicle application. The designed motor is fabricated, tested and controlled by WAVECT, an FPGA-based real-time digital controller which is used to control the commutation of the 8/6 SRM. The yielded response satisfactorily proves that the designed 8/6 SRM can be effectively used for the Tri-wheeler E-vehicle application, thereby paving the way for sustainable energy conservation in the automotive sector.

关键词： Electric vehicle switched reluctance motor permanent magnet synchronous motor brushless direct current motor WAVECT field programmable gate array

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FPGA Implementation of Particle Filters for Robotic Source Localization

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IEEE ACCESS 2021年 9卷 98185-98203页

作者： Krishna, Adithya van Schaik, Andre Thakur, Chetan Singh Indian Inst Sci Dept Elect Syst Engn Bengaluru 560012 India Western Sydney Univ MARCS Inst Int Ctr Neuromorph Syst Kingswood NSW 2747 Australia

Particle filtering is very reliable in modelling non-Gaussian and non-linear elements of physical systems, which makes it ideal for tracking and localization applications. However, a major drawback of particle filters is their computational complexity, which inhibits their use in real-time applications with conventional CPU or DSP based implementation schemes. The re-sampling step in the particle filters creates a computational bottleneck since it is inherently sequential and cannot be parallelized. This paper proposes a modification to the existing particle filter algorithm, which enables parallel re-sampling and reduces the effect of the re-sampling bottleneck. We then present a high-speed and dedicated hardware architecture incorporating pipe-lining and parallelization design strategies to supplement the modified algorithm and lower the execution time considerably. From an application standpoint, we propose a novel source localization model to estimate the position of a source in a noisy environment using the particle filter algorithm implemented on hardware. The design has been prototyped using Artix-7 field-programmable gate array (FPGA), and resource utilization for the proposed system is presented. Further, we show the execution time and estimation accuracy of the high-speed architecture and observe a significant reduction in computational time. Our implementation of particle filters on FPGA is scalable and modular, with a low execution time of about 5 :62 mu s for processing 1024 particles (compared to 64 ms on Intel Core i7-7700 CPU with eight cores clocking at 3 :60 GHz) and can be deployed for real-time applications.

关键词： Particle filters field programmable gate array bearings-only tracking Bayesian filtering unmanned ground vehicle hardware architectures real-time processing

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Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support

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JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 2021年 151卷 13-23页

作者： Palchaudhuri, Ayan Dhar, Anindya Sundar Indian Inst Technol Kharagpur Dept Elect & Elect Commun Engn Kharagpur 721302 W Bengal India

In this paper, we have addressed a speed-area efficient VLSI implementation of a cellular automaton (CA) based random number generator (RNG) on field programmable gate arrays (FPGAs), in which each CA cell was proposed to be a multi-bit word in the original algorithm. This is in contrast to typical CA algorithms comprising one bit per CA cell. The original algorithm is shown favorable for FPGA implementations on adopting a fabric conscious approach involving instantiation of physical FPGA primitives. We have supplemented the original architecture with scan path and alternating logic to facilitate fault localization without area and delay overhead. The overheads have been carefully nullified by increasing the utilization ratio of the configured primitives, and exploiting the fast hard wired fabric of the FPGA. Generation of the hardware description of the RNG through Verilog has been automated. Our proposed designs outperform equivalent behavioral implementations expressed at higher levels of abstraction, both in speed and area. (C) 2021 Elsevier Inc. All rights reserved.

关键词： Cellular automata field programmable gate array Primitive instantiation Bit-sliced design Fault localization

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An FPGA-based reconfigurable data acquisition system for LIDAR signal detection

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INTERNATIONAL JOURNAL OF EMBEDDED SYSTEMS 2021年第6期14卷 527-534页

作者： Lacomi, Hector A. di Fiore, Tomas Urbano Pintos, Nicolas Larosa, Facundo S. Inst Invest Cient & Tecn Def CITEDEF Div Radar Laser Av Juan Bautista de la Salle 4397 Buenos Aires DF Argentina Univ Tecnol Nacl Fac Reg Haedo Grp Aplicac Sistemas Embebidos Paris 532 Buenos Aires DF Argentina

Commercial equipment to detect backscattering LIDAR signals is extremely expensive and is not flexible, making it cost prohibitive and unpractical in the long-term for ad hoc detection systems where it is necessary to perform continuous improvement in the field and/or depending on the application. In this paper the development, construction and evaluation of a data acquisition system based on field programmable gate array (FPGA) technology to capture and process backscattering LIDAR signals is presented. The system performance was evaluated using laboratory generated signals which resulted in a similar performance compared with commercial equipment. Results obtained with the system were compared with several similar published implementations in order to contrast several aspects of the systems. This comparison is encouraging since it shows that this kind of scientific-grade system can be implemented using the described approach thus reaching lower costs and, at the same time, gaining in modularity, reusability, reconfigurability and flexibility.

关键词： field programmable gate array FPGA detection system LIDAR backscatter

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FPGA Implementation of Image Registration Using Accelerated CNN

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SENSORS 2023年第14期23卷 6590-6590页

作者： Aydin, Seda Guzel Bilge, Hasan Sakir Bingol Univ Dept Elect & Elect Engn TR-12000 Bingol Turkiye Gazi Univ Biomed Calibrat & Res Ctr BIYOKAM TR-06560 Ankara Turkiye

Background: Accurate and fast image registration (IR) is critical during surgical interventions where the ultrasound (US) modality is used for image-guided intervention. Convolutional neural network (CNN)-based IR methods have resulted in applications that respond faster than traditional iterative IR methods. However, general-purpose processors are unable to operate at the maximum speed possible for real-time CNN algorithms. Due to its reconfigurable structure and low power consumption, the field programmable gate array (FPGA) has gained prominence for accelerating the inference phase of CNN applications. Methods: This study proposes an FPGA-based ultrasound IR CNN (FUIR-CNN) to regress three rigid registration parameters from image pairs. To speed up the estimation process, the proposed design makes use of fixed-point data and parallel operations carried out by unrolling and pipelining techniques. Experiments were performed on three US datasets in real time using the xc7z020, and the xcku5p was also used during implementation. Results: The FUIR-CNN produced results for the inference phase 139 times faster than the software-based network while retaining a negligible drop in regression performance of under 200 MHz clock frequency. Conclusions: Comprehensive experimental results demonstrate that the proposed end-to-end FPGA-based accelerated CNN achieves a negligible loss, a high speed for registration parameters, less power when compared to the CPU, and the potential for real-time medical imaging.

关键词： accelerated CNN field programmable gate array image registration ultrasound

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Three-Port Bi-Directional DC-DC Converter with Solar PV System Fed BLDC Motor Drive Using FPGA

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ENERGIES 2023年第2期16卷 624页

作者： Udayakumar, Arun Kumar Raghavan, Raghavendra Rajan Vijaya Houran, Mohamad Abou Elavarasan, Rajvikram Madurai Kalavathy, Anushkannan Nedumaran Hossain, Eklas SRM Inst Sci & Technol Dept Elect & Elect Engn Ramapuram Campus Chennai 600089 Tamilnadu India Harman Connected Serv India Pvt Ltd Automot Dept Bengaluru 560095 Karnataka India Xi An Jiao Tong Univ Sch Elect Engn Xian 710049 Peoples R China Univ Queensland Sch Informat Technol & Elect Engn St Lucia Qld 4072 Australia Kathir Coll Engn Dept Elect & Commun Engn Coimbatore 641062 Tamilnadu India Boise State Univ Dept Elect & Comp Engn Boise ID 83725 USA

The increased need for renewable energy systems to generate power, store energy, and connect energy storage devices with applications has become a major challenge. Energy storage using batteries is most appropriate for energy sources like solar, wind, etc. A non-isolated three-port DC-DC-converter energy conversion unit is implemented feeding the brushless DCmotor drive. In this paper, a non-isolated three-port converter is designed and simulated for battery energy storage, interfaced with an output drive. Based on the requirements, the power extracted from the solar panel during the daytime is used to charge the batteries through the three-port converter. The proposed three-port converter is analyzed in terms of operating principles and power flow. An FPGA-based NI LabView PXI with SbRio interface is used to develop the suggested approach's control hardware, and prototype model results are obtained to test the proposed three-port converter control system's effectiveness and practicality. The overall efficiency of the converter's output improves as a result. The success rate is 96.5 percent while charging an ESS, 98.1 percent when discharging an ESS, and 95.7 percent overall.

关键词： BLDC motor DC-DC converter field programmable gate array MPP tracking solar PV system three-portconverter (TPC) energy storage device (ESD)

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Analysis of the error susceptibility of a field programmable gate array-based image compressor through random event injection simulation

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IET COMPUTERS AND DIGITAL TECHNIQUES 2012年第3期6卷 160-165页

作者： Lopes Filho, A. d'Amore, R. Natl Inst Space Res INPE Div Eletron Aeroespacial Sao Jose Dos Campos SP Brazil ITA Dept Eletron Aplicada Sao Jose Dos Campos SP Brazil

The successful use of commercial-off-the-shelf (COTS) devices on board space applications requires the use of fault mitigation methods because of the effects of space radiation in microelectronics devices. This study describes a scheme for the random injection of single event transients/upsets to evaluate the viability of employing COTS field programmable gate array for an onboard, low-complexity, remote-sensing image data compressor. The fault injection features are added to the application to be tested by modifying its hardware description language source code. Then the tests are executed by simulation, with or without the inclusion of fault mitigation methods, so that comparative evaluations can be quickly obtained. The evaluation results (robustness enhancement against area) of different fault mitigation methods are presented, with good estimates of the behaviour of the hardware implementation of the application in a space radiation environment.

关键词： COTS device image compressor random event injection simulation single event transient Logic and switching circuits Image and video coding hardware description languages commercial-off-the-shelf single event upset error susceptibility Logic circuits field programmable gate arrays Logic design methods fault injection features Computer vision and image processing techniques field programmable gate array image coding radiation effects Radiation effects (semiconductor technology) board space application space radiation Digital circuit design, modelling and testing microelectronics device hardware description language source code fault mitigation method

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