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An experimental investigation on a multilevel inverter for solar energy applications

INTERNATIONAL JOURNAL OF ELECTRICAL POWER & ENERGY SYSTEMS 2013年第1期47卷 157-167页

作者： Chinnaiyan, Venkatachalam Kumar Jerome, Jovitha Karpagam, J. Dr NGP Inst Technol Dept Elect & Elect Engn Coimbatore 641048 Tamil Nadu India PSG Coll Technol Dept Instrumentat & Control Syst Engn Coimbatore 641004 Tamil Nadu India Dr NGP Inst Technol Dept Elect & Commun Engn Coimbatore 641048 Tamil Nadu India

The main objective of the proposed work is to design, develop and test a three phase multilevel inverter with the modern power electronic switches to reduce the power quality issues in solar power conversion system. Due to the increased usage of power electronic converters for processing the power in all walks of our life, the power quality problem become the hot research topic in the recent years. As the power level increases, the voltage level is increased accordingly to obtain satisfactory efficiency. The multilevel power converter has shown growing popularity. The fundamental advantages of multilevel converter topologies are low distorted output waveforms and limited voltage stress on the switching devices and hence the reduced electromagnetic interferences. The main disadvantages are higher complexity and more difficult control;it can be overcome by using modern digital controllers. In this paper, the performance parameters are analyzed with the developed prototype of the three phase cascaded multilevel inverter for solar energy conversion designed with digital controller for reduced power quality issues with three phase AC motor drive. The main objective is to obtain the better quality of output waveform on the inverter output with suitable control strategy on the experimental hardware setup. (c) 2012 Elsevier Ltd. All rights reserved.

关键词： Inverters Power electronics Solar energy Drives Power converters Multi level inverter field programmable gate array

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FPGA implementation of adaptive segmentation for non-stationary biomedical signals

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IET CIRCUITS DEVICES & SYSTEMS 2010年第3期4卷 239-250页

作者： Jiao, B. Krishnan, S. Kabbani, A. Ryerson Univ Dept Elect & Comp Engn Toronto ON Canada

A novel field programmable gate array (FPGA) implementation of adaptive segmentation for non-stationary biomedical signals is presented. The design uses Simulink-to-FPGA methodology and has been successfully implemented onto Xilinx Virtex II Pro device. The implementation is based on the recursive least-squares lattice (RLSL) algorithm using double-precision floating-point arithmetic and is programmable for users providing data length, system order and threshold selection functions. The implemented RLSL design provides very good performance in obtaining accurate conversion factor values with a mean correlation above 99% and detecting segment boundaries with high accuracy for both synthesised and real-world biomedical signals.

关键词： nonstationary biomedical signals recursive least-squares lattice algorithm segment boundary detection medical signal processing least squares approximations Simulink-to-FPGA methodology adaptive segmentation field programmable gate array double-precision floating-point arithmetic field programmable gate arrays

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Janus: An FPGA-Based System for High-Performance Scientific Computing

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COMPUTING IN SCIENCE & ENGINEERING 2009年第1期11卷 48-58页

作者： Belletti, F. Guidetti, M. Maiorano, A. Mantovani, F. Schifano, S. F. Tripiccione, R. Cotallo, M. Perez-Gaviro, S. Sciretti, D. Velasco, J. L. Cruz, A. Navarro, D. Tarancon, A. Fernandez, L. A. Martin-Mayor, V. Munoz-Sudupe, A. Yllanes, D. Gordillo-Guerrero, A. Ruiz-Lorenzo, J. J. Marinari, E. Parisi, G. Rossi, M. Zanier, G. Univ Ferrara Dept Phys I-44100 Ferrara Italy Univ Zaragoza Elect & Commun Dept E-50009 Zaragoza Spain Univ Complutense Madrid E-28040 Madrid Spain Univ Extremadura E-06071 Badajoz Spain Univ Roma La Sapienza Rome Italy

Janus is a modular, massively parallel, and reconfigurable FPGA-based computing system that's tailored to a class of hard scientific applications. Monte Carlo statistical mechanics simulations provide a good examp... 详细信息

关键词： field programmable gate arrays Mathematics Computing Monte Carlo Methods Scientific Information Systems Statistical Mechanics Ubiquitous Computing Janus FPGA Based System High Performance Scientific Computing Megabits Database Monte Carlo Simulations Statistical Mechanics Scientific Computing Computational Modeling Lattices Monte Carlo Methods Parallel Processing Physics Computing Computer Simulation Pervasive Computing Biology Computing Application Software Nobel Prize Monte Carlo Simulations field programmable gate array FPGA Scientific Computing Janus

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Resource efficient LDPC decoders for multimedia communication

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INTEGRATION-THE VLSI JOURNAL 2015年第1期48卷 213-220页

作者： Chandrasetty, Vikram Arkalgud Aziz, Syed Mahfuzul Univ S Australia Sch Engn Mawson Lakes SA 5095 Australia

Achieving high image quality is an important aspect in an increasing number of wireless multimedia applications. These applications require resource efficient error correction hardware to detect and correct errors introduced by the communication channel. This paper presents an innovative flexible architecture for error correction using Low-Density Parity-Check (LDPC) codes. The proposed partially-parallel decoder architecture utilizes a novel code construction technique based on multi-level Hierarchical Quasi-Cyclic (HQC) matrix. The proposed architecture is resource efficient, provides scalable throughput and requires substantially less power compared to other decoders reported to date. The proposed decoder has been implemented on a Xilinx FPGA suitable for WiMAX application and achieves a throughput of 548 Mbps. Performance evaluation of the decoder has been carried out by transmitting JPEG images over a wireless noisy channel and comparing the quality of the reconstructed images with those from other similar decoders. (C) 2014 Elsevier B.V. All rights reserved.

关键词： Image communication Error correction codes Cyclic codes Codecs field programmable gate array

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Fuzzy Logic Control for Solar PV Fed Modular Multilevel Inverter Towards Marine Water Pumping Applications

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IEEE ACCESS 2021年 9卷 88524-88534页

作者： Stonier, Albert Alexander Murugesan, Srinivasan Samikannu, Ravi Krishnamoorthy, Vinoth Subburaj, Senthil Kumar Chinnaraj, Gnanavel Mani, Geetha Kongu Engn Coll Dept Elect & Elect Engn Erode 638060 India Botswana Int Univ Sci & Technol Dept Elect Comp & Telecommun Engn Palapye Botswana Vel Tech Rangarajan Dr Sagunthala Res & Dev Inst Dept Elect & Elect Engn Chennai 600062 Tamil Nadu India New Prince Shri Bhavani Coll Engn & Technol Dept Elect & Elect Engn Chennai 600073 Tamil Nadu India AMET Deemed Univ Dept Elect & Elect Engn Chennai 603112 Tamil Nadu India Vellore Inst Technol Sch Elect Engn Vellore 632014 Tamil Nadu India

This paper presents the design and implementation of Modular Multilevel Inverter (MMI) to control the Induction Motor (IM) drive using intelligent techniques towards marine water pumping applications. The proposed inverter is of eleven levels and has the ability to control the speed of an IM drive which is fed from solar photovoltaics. It is estimated that the energy consumed by pumping schemes in an onboard ship is nearly 50% of the total energy. Considering this fact, this paper investigates and validates the proposed control design with reduced complexity intended for marine water pumping system employing an induction motor (IM) drive and MMI. The analysis of inverter is carried out with Proportional-Integral (PI) and Fuzzy Logic (FL) based controllers for improving the performance. A comparative analysis has been made with respect to better robustness in terms of peak overshoot, settling time of the controller and Total Harmonic Distortion (THD) of the inverter. Simulations are undertaken in MATLAB/Simulink and the detailed experimental implementation is conducted with field programmable gate array (FPGA). The results thus obtained are utilized to analyze the controller performance, improved inverter output voltage, reliable induction motor speed control and power quality improvement by reduction of harmonics. The novelty of the proposed control scheme is the design and integration of MMI, IM drive and intelligent controller exclusively for marine water pumping applications.

关键词： Marine vehicles Induction motors Multilevel inverters Power quality field programmable gate arrays Velocity control Topology field programmable gate array fuzzy logic controller induction motor drive modular multilevel inverter proportional-integral total harmonic distortion

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Speed optimal FPGA implementation of the encryption algorithms for telecom applications

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MICROPROCESSORS AND MICROSYSTEMS 2020年 79卷 103324-103324页

作者： Sikka, Prateek Asati, Abhijit R. Shekhar, Chandra Birla Inst Technol & Sci Dept EEE Pilani Rajasthan India Birla Inst Technol & Sci Dept EEE Vidya Vihar Campus Pilani Rajasthan India

The last two decades have seen a revolution in telecom technology with the evolution of three wireless mobile communication standards, namely, GPRS to 3G, 3G to 4G, and 4G to 5G. 5G offers faster download speeds and enables high connectivity between devices such as mobile phones, displays, smart homes, and smart cars because of its high reliability and high bandwidths (up to 10 Gbps). However, at the same time, data and personal information are also more susceptible to theft because of the high connectivity. Such threats can be addressed using electronic data encryption using the advanced encryption standard (AES). Because of their reconfigurable and parallel architectures, field-programmable gate arrays (FPGAs) are getting popular in VLSI design flows to enable the pre-silicon validation of designs faster data rates in real-time. FPGAs also serve as platforms for software development in the pre-silicon environment owing to their faster speeds. The design community is also heavily relying on High-Level Synthesis (HLS) tools in VLSI design flows. HLS platforms enable the new designs to improve the process with sustained authentication between two analytical selections from conventional functional specifications. We propose a high-throughput FPGA implementation based on high-level Synthesis for the AES algorithm. The implementation uses a 128-bit key and is highly suited for telecom applications such as 5G. Researchers have developed and tested the setup and then used the Vivado HLS tool to evaluate various HLS guidelines as per the implementation. The generated Verilog RTL was verified and implemented on Xilinx Kintex 7 and Virtex 6 FPGAs. Since using the same resources, we have seen significant results than existing methods achieved by individual investigators. We have also verified the design for functionality by checking the ciphertext output from our design against a reference design output for the same input plaintext.

关键词： Advanced encryption standard field programmable gate array Register transfer level Telecom Xilinx high-level synthesis

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Experimental Quantification of Hardware Requirements for FPGA-Based Reconfigurable PMUs

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IEEE ACCESS 2019年 7卷 57527-57538页

作者： Adhikari, Prottay M. Hooshyar, Hossein Vanfretti, Luigi Rensselaer Polytech Inst Dept Elect Comp & Syst Engn Troy NY 12180 USA Elect Power Res Inst 3412 Hillview Ave Palo Alto CA 94304 USA

Phasor Measurement Units (PMUs) are becoming intrinsic components of modern power systems. The synchrophasor estimation algorithms in PMUs pose stringent computational demands, which makes the application of field programmable gate arrays (FPGA) highly attractive. Previous works reported the implementation of PMU algorithms on specific FPGA-targets using a particular PMU design. This paper explores the implementation of different PMU designs on multiple FPGA targets using Xilinx and NI software and hardware infrastructures and toolsets. In this process, a metric has been formulated to predict FPGA-target hardware requirements. The metric allows predicting if an FPGA-target meets the needs to deploy a given PMU design resulting in significant engineering design time savings. Since the compilation/synthesis on FPGAs is a time-consuming job, this metric can reduce the implementation time for FPGA-based PMUs drastically and can help in determining if additional functionalities can be added.

关键词： Phasor measurement unit field programmable gate array

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A real-time near infrared image acquisition system based on image quality assessment

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JOURNAL OF REAL-TIME IMAGE PROCESSING 2017年第1期13卷 103-120页

作者： Lee, Y. H. Khalil-Hani, M. Bakhteri, Rabia Nambiar, Vishnu P. Univ Teknol Malaysia Fac Elect Engn VeCAD Res Lab Utm Skudai 81310 Johor Bahru Malaysia

This paper presents a real-time image acquisition system with an improved image quality assessment module to acquire high-quality near infrared (NIR) images. Thermal imaging plays a vital role in a wide range of medical and military applications. The demand for high-throughput image acquisition and image processing has continuously increased especially for critical medical and military purposes where executions under real-time constraints are required. This work implements an NIR image quality assessment module, which utilizes improved two-dimensional entropy and mask-based edge detection algorithms. The effectiveness of the proposed image quality assessment algorithms is demonstrated through the implementation of a complete finger-vein biometric system. The proposed model is implemented as an embedded system on a field programmable gate array prototyping platform. By including the image quality assessment module, the proposed system is able to achieve a recognition accuracy of 0.87 % equal error rate, and can handle real-time processing at 15 frames/s (live video rate). This is achieved through hardware acceleration of the proposed image quality assessment algorithms via a novel streaming architecture.

关键词： Real-time image acquisition Image quality assessment field programmable gate array Biometrics Finger-vein

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Hardware variant NSP with security-aware automated preferential algorithm

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IET COMPUTERS AND DIGITAL TECHNIQUES 2018年第5期12卷 192-205页

作者： Paul, Rourab Sikder, Gitesh Chakrabarti, Amlan Ghosh, Ranjan Univ Calcutta Sch IT Kolkata India

Efficient and cost-effective hardware design of network security processor (NSP) is of vital importance in the present era due to the increasing need of security infrastructure in a wide range of computing applications. Here, the authors propose an NSP in field programmable gate array (FPGA) platform where according to a strict power, throughput, resource, and security priorities, a proposed preferential algorithm chooses a cipher suite to program the hardware. The choice is based on a rank list of available cipher suites depending on efficient system index evaluated in terms of power, throughput, resource, and security data and their given weights by the user. Encryption, hash, and key exchange algorithm along with their architectural variants serve excellent hardware flexibility whose bit files are stored in secure digital memory. The proposed design used an isolated key memory where secret keys are stored in encrypted form along with the hash value. The design is implemented using ISE14.4 suite with ZYNQ7z020-clg484 FPGA platform. The performances of the variants architecture of the crypto algorithms are considerably better in terms of power, throughput, and resource than the existing works reported in the literature.

关键词： field programmable gate arrays microprocessor chips cryptography logic design hardware variant NSP security-aware automated preferential algorithm cost-effective hardware design network security processor security infrastructure field programmable gate array preferential algorithm cipher suites system index security data key exchange algorithm architectural variants secure digital memory encryption secret keys hash value ZYNQ7z020-clg484 FPGA platform ISE14 4 suite crypto algorithms

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BFT: a placement algorithm for non-rectangle task model in reconfigurable computing system

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IET COMPUTERS AND DIGITAL TECHNIQUES 2016年第3期10卷 128-137页

作者： Wang, Chaohui Wu, Weiguo Nie, Shiqiang Qian, Depei Xi An Jiao Tong Univ Dept Comp Sci & Technol Xian Shaanxi Peoples R China Beihang Univ Sch Comp Sci & Engn Beijing 100191 Peoples R China

Task scheduling and placement problem is one of the most significant and time-consuming parts in reconfigurable computing (RC) system. Many investigators have explored on the subject, and most of the traditional studies are concentrated on the rectangle task model, which is inconsistent with objective task shape placed in a field programmable gate array (FPGA) but simplifies the system complexity. Rectangle task model produces inner fragments which reduces utilisation of reconfigurable resources in an FPGA. In this study, a task model transformation strategy and an innovative best-fit transformation (BFT) placement algorithm are proposed for a non-rectangle task model to improve the performance of an RC system in rejection rate and total execution time. According to simulation experiments, BFT algorithm reduced the rejection rate by 15% and 7% compared with that of the first-fit algorithm and the best-fit algorithm, respectively. Multi-shape placement algorithm and 3D compaction algorithm are also cited to compare with the BFT algorithm. The result shows that the BFT algorithm has less total execution time in short laxity period and lower rejection rate in large laxity period. Compared with 3D compaction algorithm, the proposed algorithm reduced the total execution time up to 10.79%.

关键词： reconfigurable architectures field programmable gate arrays processor scheduling BFT nonrectangle task model reconfigurable computing system task scheduling and placement problem RC system field programmable gate array FPGA system complexity reconfigurable resources task model transformation strategy innovative best-fit transformation placement algorithm total execution time rejection rate first-fit algorithm multishape placement algorithm 3D compaction algorithm

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