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Analysis of the error susceptibility of a field programmable gate array-based image compressor through random event injection simulation

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IET COMPUTERS AND DIGITAL TECHNIQUES 2012年第3期6卷 160-165页

作者： Lopes Filho, A. d'Amore, R. Natl Inst Space Res INPE Div Eletron Aeroespacial Sao Jose Dos Campos SP Brazil ITA Dept Eletron Aplicada Sao Jose Dos Campos SP Brazil

The successful use of commercial-off-the-shelf (COTS) devices on board space applications requires the use of fault mitigation methods because of the effects of space radiation in microelectronics devices. This study describes a scheme for the random injection of single event transients/upsets to evaluate the viability of employing COTS field programmable gate array for an onboard, low-complexity, remote-sensing image data compressor. The fault injection features are added to the application to be tested by modifying its hardware description language source code. Then the tests are executed by simulation, with or without the inclusion of fault mitigation methods, so that comparative evaluations can be quickly obtained. The evaluation results (robustness enhancement against area) of different fault mitigation methods are presented, with good estimates of the behaviour of the hardware implementation of the application in a space radiation environment.

关键词： COTS device image compressor random event injection simulation single event transient Logic and switching circuits Image and video coding hardware description languages commercial-off-the-shelf single event upset error susceptibility Logic circuits field programmable gate arrays Logic design methods fault injection features Computer vision and image processing techniques field programmable gate array image coding radiation effects Radiation effects (semiconductor technology) board space application space radiation Digital circuit design, modelling and testing microelectronics device hardware description language source code fault mitigation method

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FPGA Implementation of a Binarized Dual Stream Convolutional Neural Network for Service Robots

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JOURNAL OF ROBOTICS AND MECHATRONICS 2021年第2期33卷 386-399页

作者： Yoshimoto, Yuma Tamukoh, Hakaru Kyushu Inst Technol Grad Sch Life Sci & Syst Engn Wakamatsu Ku 2-4 Hibikino Kitakyushu Fukuoka 8080196 Japan Japan Soc Promot Sci Wakamatsu Ku 2-4 Hibikino Kitakyushu Fukuoka 8080196 Japan Kyushu Inst Technol Res Ctr Neuromorph AI Hardware Wakamatsu Ku 2-4 Hibikino Kitakyushu Fukuoka 8080196 Japan

In this study, with the aim of installing an object recognition algorithm on the hardware device of a service robot, we propose a Binarized Dual Stream VGG-16 (BDS-VGG16) network model to realize high-speed computations and low power consumption. The BDS-VGG16 model has improved in terms of the object recognition accuracy by using not only RGB images but also depth images. It achieved a 99.3% accuracy in tests using an RGB-D Object Dataset. We have also confirmed that the proposed model can be installed in a field-programmable gate array (FPGA). We have further installed BDS-VGG16 Tiny, a small BDS-VGG16 model in XCZU9EG, a system on a chip with a CPU and a middle-scale FPGA on a single chip that can be installed in robots. We have also integrated the BDS-VGG16 Tiny with a robot operating system. As a result, the BDS-VGG16 Tiny installed in the XCZU9EG FPGA realizes approximately 1.9-times more computations than the one installed in the graphics processing unit (GPU) with a power efficiency approximately 8-times higher than that installed in the GPU.

关键词： convolutional neural network depth image dual stream field programmable gate array object recognition

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ECG R-Wave Detection and Its Application in Left Ventricular Assist Device

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2023年第18期32卷 2350308-2350308页

作者： Yan, Rongguo Wang, Jie Wang, Jiahui Shao, Hongran Fang, Xuchen Univ Shanghai Sci & Technol Sch Hlth Sci & Engn Shanghai 200093 Peoples R China Shidong Hosp Dept Intens Care Unit Shanghai 200438 Peoples R China

Heart failure is one of the major diseases endangering human life. As a transitional support treatment before heart transplantation, the left ventricular assist device (LVAD) has significantly improved the quality of life and survival rate of patients with end-stage heart failure. In the automatic detection of electrocardiogram (ECG), the detection of QRS wave groups is the most critical aspect, which affects the correctness and accuracy of subsequent data analysis and processing. The paper used the data from the MIT-BIH database and the data collected from human ECG as the original number of samples for further processing. It processed the data through a high-order finite impulse response (FIR) low-pass filter and Shannon energy algorithm, and added the use of a high-order adaptive median filter algorithm on a field programmable gate array (FPGA) to minimize the noise of the processed real-time data. Finally, the tested ECG R-wave was used to drive the LVAD. After successful simulation by MATLAB and Modelsim software, the scheme of the real-time ECG signal controlling blood pump system was realized on the FPGA platform. The experiment showed that the method proposed could accurately extract the R-wave and control the LVAD to pump blood simultaneously.

关键词： Real-time R-wave detection field programmable gate array ECG signal left ventricular assist Shannon energy

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FPGA Implementation of Efficient CFAR Algorithm for Radar Systems

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SENSORS 2023年第2期23卷 954-954页

作者： Sim, Yunseong Heo, Jinmoo Jung, Yongchul Lee, Seongjoo Jung, Yunho Korea Aerosp Univ Sch Elect & Informat Engn Goyang Si 10540 South Korea Korea Aerosp Univ Dept Smart Air Mobil Goyang Si 10540 South Korea Korea Elect Technol Inst KETI Seongnam 13509 South Korea Sejong Univ Dept Informat & Commun Engn Seoul 05006 South Korea Sejong Univ Dept Convergence Engn Intelligent Drone Seoul 05006 South Korea

The constant false-alarm rate (CFAR) algorithm is essential for detecting targets during radar signal processing. It has been improved to accurately detect targets, especially in nonhomogeneous environments, such as multitarget or clutter edge environments. For example, there are sort-based and variable index-based algorithms. However, these algorithms require large amounts of computation, making them difficult to apply in radar applications that require real-time target detection. We propose a new CFAR algorithm that determines the environment of a received signal through a new decision criterion and applies the optimal CFAR algorithms such as the modified variable index (MVI) and automatic censored cell averaging-based ordered data variability (ACCA-ODV). The Monte Carlo simulation results of the proposed CFAR algorithm showed a high detection probability of 93.8% in homogeneous and nonhomogeneous environments based on an SNR of 25 dB. In addition, this paper presents the hardware design, field-programmable gate array (FPGA)-based implementation, and verification results for the practical application of the proposed algorithm. We reduced the hardware complexity by time-sharing sum and square operations and by replacing division operations with multiplication operations when calculating decision parameters. We also developed a low-complexity and high-speed sorter architecture that performs sorting for the partial data in leading and lagging windows. As a result, the implementation used 8260 LUTs and 3823 registers and took 0.6 mu s to operate. Compared with the previously proposed FPGA implementation results, it is confirmed that the complexity and operation speed of the proposed CFAR processor are very suitable for real-time implementation.

关键词： radar signal processing constant false alarm rate target detection field programmable gate array automotive radar drone detection radar

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Improved design debugging architecture using low power serial communication protocols for signal processing applications

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INTERNATIONAL JOURNAL OF SPEECH TECHNOLOGY 2021年第2期24卷 291-302页

作者： Murali, A. Kakarla, Hari Kishore Anitha Priyadarshini, G. M. Koneru Lakshmaiah Educ Fdn Dept ECE Guntur Andhra Pradesh India Sri Venkateswara Coll Engn & Technol Dept ECE Chittoor AP India

Now-a-days FPGA designers are facing the problem of unprecedented challenges in debugging their designs. In the past, designers debugged their FPGAs by plugging them onto a board and then analyzing them with probes and logic analyzers. But right now the vendors of FPGA are offering tools that make it somewhat easier to probe internal design signals inside the FPGA, Once unexpected behavior is observed, on-chip debug is notoriously difficult;typically a design is instrumented with on-chip trace buffers that record the run-time behavior for later interrogation. Based on the demand for verification leads to an increase in FPGA-based tools that improves the performance of the architecture. The low power communication protocols can run at much higher operating frequencies with less *** provide a promising implementation option for many DSP applications particularly in speech signal processing devices such as data converters, digital filters, etc. This work improves the performance of current debugging techniques and makes them more reliable. This work proposes a novel design debugging architecture based on implementation of reconfigurable insertion technique with the help of low power communication protocols used in the FIR filter to debug the entire architecture with less area. If there is any possibility of bug occurs in the UART protocol then the data is transferred through SPI protocol. SPI protocol worked in the operating frequency of 330.12 MHz. According to the power consumption, the UART protocol consumes 0.0135W which is far better than other protocols like SPI, I2C etc. Moreover, the area overhead is reduced. This is achieved by implementing the extra instrumentation. The design debugging architecture is developed using Verilog HDL and implemented on FPGA with the help of Xilinx ISE tool.

关键词： field programmable gate array FIR filter SPI UART FSM controller Reconfigurable buffers

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Spectrum sensing in cognitive radio using recurrence diagrams

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INTERNATIONAL JOURNAL OF EMBEDDED SYSTEMS 2021年第6期14卷 535-543页

作者： Antonelli, Maximiliano Castineira Moreira, Jorge De Micco, Luciana Natl Univ Mar del Plata Phys Chaot Syst LabICYTE Inst Sci & Technol Res Elect CONICET Natl Council Sci & Tech ResFIUNMDP Fac E Juan B Justo 4302 RA-7600 Mar Del Plata Buenos Aires Argentina Natl Univ Mar del Plata ICYTE Inst Sci & Technol Res Elect CONICET Natl Council Sci & Tech Res FIUNMDP Fac EngnElectCommun Lab Juan B Justo 4302 RA-7600 Mar Del Plata Buenos Aires Argentina Natl Univ Mar del Plata ElectChaot Syst Lab ICYTE Inst Sci & Technol Res Elect CONICET Natl Council Sci & Tech ResFIUNMDP Fac E Juan B Justo 4302 RA-7600 Mar Del Plata Buenos Aires Argentina

In this article, a new technique for the detection of primary users in cognitive radio (CR) is presented. The proposed technique is based on statistical quantifiers that take into account causal information from the received signal. Results show that a quick decision about the transmission of the data is possible by sensing a very short time. Furthermore, heavily noise-contaminated signals are detectable, even without prior information about the level of noise in the channel. We show the performance of the method and conclude that is comparable to those used classically. Finally, we present the hardware implementation and the resources employed.

关键词： cognitive radio spectrum sensing recurrence diagrams field programmable gate array hardware implementation

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Certification of the efficient random number generation technique based on single-photon detector arrays and time-to-digital converters

IET QUANTUM COMMUNICATION

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IET QUANTUM COMMUNICATION 2021年第3期2卷 74-79页

作者： Stanco, Andrea Marangon, Davide G. Vallone, Giuseppe Burri, Samuel Charbon, Edoardo Villoresi, Paolo Univ Padua Dipartimento Ingn Informaz Padua Italy Toshiba Europe Ltd Cambridge Res Lab Cambridge England Univ Padua Dipartimento Fis & Astron Padua Italy Ecole Polytech Fed Lausanne EPFL Neuchatel Switzerland Univ Padua Dipartimento Ingn Informaz Via 8 Febbraio 2 I-35122 Padua Italy

True random number generators (TRNGs) allow the generation of true random bit sequences, guaranteeing the unpredictability and perfect balancing of the generated values. TRNGs can be realised from the sampling of quantum phenomena, for instance, the detection of single photons. Here, a recently proposed technique, which implements a quantum random number generator (QRNG) out of a device that was realised for a different scope, is further analysed and certified [1]. The combination of a CMOS single-photon avalanche diode (SPAD) array, a high-resolution time-to-digital converter (TDC) implemented on a field programmable gate array (FPGA), the exploitation of a single-photon temporal degree of freedom, and an unbiased procedure provided by H. Zhou and J. Bruck [2, 3] allows the generation of true random bits with a high bitrate in a compact and easy-to-calibrate device. Indeed, the use of the 'Zhou-Bruck' method allows the removal of any correlation from the binary representation of decimal data. This perfectly fits with the usage of a device with non-idealities like SPAD's afterpulses, pixel cross-correlation, and time-to-digital converter non-uniform conversion. In this work, an in-depth analysis and certification of the technique presented in [1] is provided by processing the data with the NIST suite tests in order to prove the effectiveness and validity of this approach.

关键词： random sequences decimal data random number generators integrated optics random number generation time-to-digital converter nonuniform conversion efficient random number generation technique true random bit sequences SPAD array compact device unbiased procedure Zhou-Bruck method CMOS integrated circuits easy-to-calibrate device field programmable gate array avalanche photodiodes high-resolution time-to-digital converter TDC perfect balancing field programmable gate arrays pixel cross-correlation time-digital conversion single photon detector arrays quantum phenomena certification optical arrays single-photon temporal degree of freedom NIST suite tests photodetectors calibration quantum random number generator CMOS single-photon avalanche diode array QRNG binary representation FPGA TRNGs

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Hardware implementation of deep neural network for seizure prediction

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AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS 2023年 172卷

作者： Massoud, Yasmin M. Ahmad, Ahmad A. Abdelzaher, Mennatallah Kuhlmann, Levin Abd El Ghany, Mohamed A. German Univ Cairo Cairo Egypt Univ Melbourne Parkville Australia Swinbourne Univ Brain Dynam Lab Melbourne Australia Tech Univ Darmstadt Integrated Elect Syst Lab Darmstadt Germany

Epilepsy is a neurological disorder characterized by seizures, which are caused by a sudden, uncontrollable electrical disturbance in the brain. Recently, machine learning and deep learning techniques have been used in seizure prediction algorithms, which greatly aids epilepsy patients. Moreover, the usage of hardware that is available for both medical practitioners and epilepsy patients would help enhance the quality of life for epilepsy patients. For this purpose, a field-programmable gate array (FPGA) is used in this work to implement a hardware model of a neural network that is able to predict seizures. In this research, the main aim is to implement an FPGA-based general and patient-specific seizure prediction algorithm that detects seizures for epilepsy patients using Multilayer Perceptron (MLP) neural network models. Moreover, the work will also tackle ways to optimize the FPGA resources and the computational time of the seizure prediction models. The data available for training and testing are raw electroencephalogram (EEG) signal samples provided by the Melbourne-NeuroVista seizure trial and the Melbourne-University AES-MathWorks-NIH Seizure Prediction Challenge. The results show that the general model had an Area under curve (AUC) score of 0.72 while the

关键词： Seizure prediction Machine learning Deep learning field programmable gate array

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A parallel decision-making design for highly speedy packet classification

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MICROPROCESSORS AND MICROSYSTEMS 2023年第1期99卷

作者： Adiseshaiah, Midde Sailaja, Maruvada Jawaharlal Nehru Technol Univ Kakinada Dept Elect & Commun Engn Kakinada 533003 Andhra Pradesh India

Packet classification is crucial in computer networks to increase network security because of developments in high-speed data communication. To support different network services including Quality of Service (QoS), se-curity, and resource reservation, network packet classification is a crucial network kernel function. It became extremely challenging to classify arriving packets using the traditional packet classification algorithms at a decent pace due to the rapidly increasing size of rulesets and rule fields in current networks. In addition to hardware-based solutions, numerous contemporary software-based classification techniques have been put out to speed up packet classification. In general, it's critical to manage low latency, fast throughput, and higher energy efficiency with minimal memory needs while designing a packet classification method. In this paper, proposed the architecture makes use of the parallelism provided by current hardware technologies to classify numerous packets at once to improve throughput, reduce energy consumption, and significantly decrease the latency. The suggested high-speed parallel classification procedure uses two DPRAMs (DPRAM1 and DPRAM2) to support multiple read of the data. DPRAMs(Dual Port Random Access Memories) are preferred for stage memory because of their low latency performance, which enables quick rate packet lookup. The packet scheduling module re-ceives the data from the DPRAM. The four successive packet splitter modules receive the packets in parallel. As a result, the packet classification throughput increased. To optimize throughput, and latency while maintaining low energy consumption, facilitating parallel packet classification architecture on FPGA is discussed in this work. Several parameters, including throughput, latency, energy efficiency, and memory requirements, will be eval-uated and compared to traditional methods to assess performance. The classifier offers less latency of 51 ns and the lowest energy

关键词： Dual port random access memory field programmable gate array Packet classification Packet scheduling Software -defined networking

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Development of a High-Voltage Pulsed Electric field Sterilization Power Supply Using a New Topology Circuit

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ENERGIES 2023年第6期16卷 2741页

作者： Zhu, Bo Su, He Fang, Zhihan Wu, Guoyan Wei, Xinlao Harbin Univ Sci & Technol Coll Elect & Elect Engn Harbin 150080 Peoples R China

Traditional thermal sterilization technology is easy to implement and safe, but it will destroy food nutrition and change food taste. Therefore, people began to turn their attention to non-thermal sterilization. High-voltage pulsed electric field sterilization technology is one of them;it has attracted much attention because of its high efficiency and little damage to food. Different types of loads will cause serious trailing of the pulse falling edge. In view of this situation, this paper proposes a new topology circuit that combines a solid-state switch with a half-bridge Marx generator. It can be used for high-voltage pulsed electric field sterilization. By improving the structure of the classical Marx circuit, the high-voltage pulse power supply of the new topology circuit has the characteristics of steep rising edge and short falling edge delay;does not require isolation inductance or isolation resistance, which solves the isolation problem between the DC charging power supply and the high-voltage terminal;and has a good voltage-clamping function and load adaptability. The working process of the topology circuit under resistive, capacitive and inductive loads and the voltage clamping effect when the solid-state switch does not work properly in the discharge process are analyzed in detail. The power supply is composed of an adjustable DC power supply, five-stage half-bridge Marx generator and control protection circuit. A field programmable gate array (FPGA) is used as the controller to generate control signals, and optical fiber isolation is used to provide control signals for the main loop. The power supply can output a high-voltage square wave pulse with a voltage amplitude of 10 kV, maximum pulse number of 1000 per second, maximum pulse width of 20 mu s, pulse rise time of smaller than 300 ns and short pulse drop time, and the repeated voltage amplitude, frequency and pulse width are adjustable, which can meet the requirements of a high-voltage pulse sterili

关键词： high-voltage pulse power supply pulsed electric field Marx generator all-solid-state field programmable gate array liquid sterilization

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