检索结果-内蒙古大学图书馆

QPACE: Quantum Chromodynamics Parallel Computing on the Cell Broadband Engine

COMPUTING IN SCIENCE & ENGINEERING 2008年第6期10卷 46-54页

作者： Goldrian, Gottfried Huth, Thomas Krill, Benjamin Lauritsen, Jack Schick, Heiko Ouda, Ibrahim Heybrock, Simon Hierl, Dieter Maurer, Thilo Meyer, Nils Schaefer, Andreas Solbrig, Stefan Streuer, Thomas Wettig, Tilo Pleiter, Dirk Sulanke, Karl-Heinz Winter, Frank Simma, Hubert Schifano, Sebastiano Fabio Tripiccione, Raffaele Nobile, Andrea Drochner, Matthias Lippert, Thomas Fodor, Zoltan IBM Res & Dev Lab Boblingen Germany IBM Lab Boblingen Germany IBM Syst & Technol Grp Rochester MN USA IBM Lab Rochester MN USA Univ Regensburg D-8400 Regensburg Germany DESY Zeuthen Germany Univ Milan I-20122 Milan Italy Univ Ferrara I-44100 Ferrara Italy European Ctr Theoret Studies Trento Italy Res Ctr Julich Inst Adv Simulat Julich Germany Julich Supercomp Ctr Julich Germany Univ Wuppertal Wuppertal Germany

Application-driven computers for Lattice Gauge Theory simulations have often been based on system-on-chip designs, but the development costs can be prohibitive for academic project budgets. An alternative approach uses compute nodes based on a commercial processor tightly coupled to a custom-designed network processor. Preliminary analysis shows that this solution offers good performance, but it also entails several challenges, including those arising from the processor's multicore structure and from implementing the network processor on a field-programmable gate array.

关键词： field programmable gate arrays gauge field theory parallel machines quantum chromodynamics system-on-chip cell broadband engine field programmable gate array lattice gauge theory parallel computing system-on-chip designs QCD field-programmable gate array quantum chromodynamics chip scale packaging Network Processor String theory field programmable gate arrays parallel machines PARALLEL PROCESSING (COMPUTERS) system-on-chip Lattice gauge theory

来源：评论

学校读者我要写书评

暂无评论

RTL implementations and FPGA benchmarking of selected CAESAR Round Two authenticated ciphers

引用

MICROPROCESSORS AND MICROSYSTEMS 2017年 52卷 202-218页

作者： Diehl, William Gaj, Kris George Mason Univ Dept Elect & Comp Engn Fairfax VA 22033 USA George Mason Univ Cryptog Engn Res Grp Fairfax VA 22033 USA

Authenticated ciphers are cryptographic transformations which combine the functionality of confidentiality, integrity, and authentication. This research uses register transfer-level (RTL) design to describe selected authenticated ciphers using a hardware description language (HDL), verifies their proper operation through functional simulation, and implements them on target FPGAs. The authenticated ciphers chosen for this research are the CAESAR Round Two variants of SCREAM, POET, Minalpher, and OMD. Ciphers are discussed from an engineering standpoint, and are compared and contrasted in terms of design features. To ensure conformity and standardization in evaluation, all four candidates are implemented with an identical version of the CAESAR Hardware API for authenticated ciphers. Functionally correct implementations of all four ciphers are realized, and results are compared against each other and previous results in terms of throughput, area, and throughput-to-area (TP/A) ratio. SCREAM is found to have the highest TP/A ratio of these four ciphers in the Virtex-6 FPGA, while Minalpher has the highest TP/A ratio in the Virtex-7 FPGA. (C) 2017 Elsevier B.V. All rights reserved.

关键词： Authentication Cipher Cryptography Encryption field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Efficient parallel architecture for implementation of the CMA adaptive antenna

引用

IETE TECHNICAL REVIEW 2013年第4期30卷 303-312页

作者： Boonpoonga, Akkarat Sirisuk, Phaophak Krairiksh, Monai King Mongkuts Univ Technol North Bangkok Fac Engn Dept Elect & Comp Engn Bangkok 10800 Thailand King Mongkuts Inst Technol Ladkrabang Int Coll Bangkok Thailand King Mongkuts Inst Technol Ladkrabang Fac Engn Bangkok Thailand

This paper presents an efficient parallel architecture for implementation of a constant modulus algorithm (CMA) adaptive array antenna. By inserting delay units into the original CMA, a novel delayed CMA (DCMA) that can significantly reduce the associated critical path is derived. Consequently, a pipelining architecture that supports parallel processing is introduced for implementation of the DCMA. In addition to the pipelining technique, a power-of-two multiplier is proposed for the DCMA leading to the efficient FPGA implementation. The effects of delays and finite word-length on the convergence property of CMA are investigated via simulations. Moreover, the synthesized results demonstrate that FPGA implementation of the proposed architecture using power-of-two arithmetic achieves 26.9% resource reduction in comparison with that of fixed-point arithmetic and operating clock frequency higher than 65 MHz. The implemented FPGA was tested to confirm that the designed architecture operates well for CMA.

关键词： Adaptive antenna Constant modulus algorithm field programmable gate array Pipelining

来源：评论

学校读者我要写书评

暂无评论

Low-Complexity FPGA Implementation of 106.24Gbps DP-QPSK Coherent Optical Receiver With Fractional Oversampling Rate Based on One FIR Filter for Resampling, Retiming and Equalizing

引用

JOURNAL OF LIGHTWAVE TECHNOLOGY 2023年第16期41卷 5244-5251页

作者： Song, Jingwei Li, Yan Qiu, Jifang Hong, Xiaobin Guo, Hongxiang Yang, Zhisheng Wu, Jian Beijing Univ Posts & Telecommun State Key Lab Informat Photon & Opt Commun Beijing 100876 Peoples R China

A novel low-complexity combined resampling, retiming and equalizing (RRE) algorithm is proposed. The RRE algorithm uses a single FIR filter for resampling, retiming and equalizing and thus lower the complexity. In the numerical simulation, with an oversampling rate of 32/27, compared to the traditional time-domain scheme with a 15-tap CMA equalizer and the frequency-domain scheme based on 256-point FFT, the RRE algorithm with a 15-tap RRE filter lowers the error vector magnitude (EVM) by 0.036 dB and 0.043 dB and the complexity is lowered by 48.3% and 31.9%, respectively. In the offline experiment, with a received optical power of -35 dBm, compared to the traditional time-domain scheme with a 15-tap CMA equalizer and the frequency-domain scheme based on 256-point FFT, the RRE algorithm with a 15-tap RRE filter lowers the EVM by 0.26 dB and 0.36 dB. And the RRE algorithm respectively lowers the complexity by 48.3% and 31.9%. The RRE algorithm also enables a real-time 106.24 Gbps (26.56 GBaud) DP-QPSK coherent optical receiver based on a single FPGA chip using four 6-bit ADCs with a sampling rate of similar to 31.48 GSa/s. The FPGA-based receiver achieves a sensitivity of -34 dBm at BER of 1E-3. As far as we know, this is the highest reported bit rate of a coherent receiver based on a single FPGA chip.

关键词： Clock recovery coherent optical communication digital signal processing field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

An efficient implementation of novel Paillier encryption with polar encoder for 5G systems in VLSI

引用

COMPUTERS & ELECTRICAL ENGINEERING 2018年 65卷 153-164页

作者： Ganesan, Indumathi Balasubramanian, Aarthi Alias Ananthakirupa Muthusamy, Ramesh Mepco Schlenk Engn Coll ECE Sivakasi Tamil Nadu India Mepco Schlenk Engn Coll Sivakasi Tamil Nadu India Kamaraj Coll Engn & Technol Elect & Commun Engn Virudunagar Tamil Nadu India

In this paper, a novel design of Paillier encryption with a modified polar encoding is proposed and analyzed. A new cross-partitioned add shift processing element based on perfect reconstruction technique is designed for the realization of encryption with proper distribution of adders and shifters to minimize the logical component and register usage. In addition, a modified architecture for the polar encoder with optimal delay/minimized hardware resource is achieved by presenting a novel delay calculation methodology followed by register allocation grouped as the Reduced Register Delay Allocation (RRDA) algorithm. Resource utilization, including slice registers, lookuptables (LUTs) and DSP blocks are measured along with operating speed and throughput for the proposed paillier encryption and polar encoder. Finally, the performance is analyzed with the existing designs. The proposed sequential encoding-encryption can be deployed in imminent 5G systems. (C) 2017 Elsevier Ltd. All rights reserved.

关键词： Paillier encryption Polar encoder field programmable gate array Hardware utilization 5G

来源：评论

学校读者我要写书评

暂无评论

Structure and Online Self-Repair Mechanisms for Digital Systems Based on System-on-programmable-Chip

引用

JOURNAL OF AEROSPACE INFORMATION SYSTEMS 2018年第10期15卷 604-610页

作者： Yao, Rui Du, Junjie Zhu, Ping Wang, Meiqun Nanjing Univ Aeronaut & Astronaut Coll Automat & Engn Nanjing 211106 Jiangsu Peoples R China

来源：评论

学校读者我要写书评

暂无评论

Testing configurable LUT-based FPGA's

引用

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1998年第2期6卷 276-283页

作者： Huang, WK Meyer, FJ Chen, XT Lombardi, F Fudan Univ Dept Elect Engn Shanghai 200433 Peoples R China Texas A&M Univ Dept Comp Sci College Stn TX 77843 USA Lucent Technol FPGA Software Core Grp Allentown PA 18103 USA

We present a new technique for testing field programmable gate arrays (FPGA's) based on look-up tables (LUT's). We consider a generalized structure for the basic FPGA logic element (cell);it includes devices such as LUT's, sequential elements (flip-flops), multiplexers and control circuitry. We use a hybrid fault model for these devices. The model is based on a physical as well as a behavioral characterization. This permits detection of all single faults (either stuck-at or functional) and some multiple faults using repeated FPGA reprogramming. We show that different arrangements of disjoint one-dimensional (1-D) cell arrays with cascaded horizontal connections and common vertical input lines provide a good logic testing regimen. The testing time is independent of the number of cells in the array (C-testability), We define new conditions for C-testability of programmable/reconfigurable arrays. These conditions do not suffer from limited I/O pins. Cell configuration affects the controllability/observability of the iterative array. We apply the approach to various Xilinx FPGA families and compare it to prior work.

关键词： C-testability field programmable gate array programmability reconfigurability testing

来源：评论

学校读者我要写书评

暂无评论

Comparative Analysis of Present and Future Space-Grade Processors with Device Metrics

引用

JOURNAL OF AEROSPACE INFORMATION SYSTEMS 2017年第3期14卷 184-197页

作者： Lovelly, Tyler M. George, Alan D. Univ Florida Dept Elect & Comp Engn NSF Ctr High Performance Reconfigurable Comp 330 Benton Hall Gainesville FL 32611 USA Univ Florida Dept Elect & Comp Engn NSF Ctr High Performance Reconfigurable Comp 327 Larsen Hall Gainesville FL 32611 USA

Due to harsh and inaccessible operating environments, space computing presents many unique challenges and constraints that limit onboard computing performance. However, the increasing need for real-time sensor and autonomous processing, coupled with limited communication bandwidth with ground stations, is increasing onboard computing demands for next-generation space missions. Because currently available space-grade processors cannot satisfy this growing demand, research into various processors is conducted to ensure that potential new processors are based upon architectures that will best meet the computing needs of space missions. Device metrics are used to measure and compare the theoretical capabilities of processors based upon vendor-provided data and tools, enabling the study of large and diverse sets of architectures. Architectural tradeoffs are determined that can be considered when comparing or designing space-grade processors. Results demonstrate how onboard computing capabilities are increasing due to emerging architectures that support high levels of parallelism in terms of computational units, internal memories, and input/output resources;and that performance varies between applications, depending on the compute-intensive kernels used. Furthermore, the overheads incurred by radiation hardening are quantified and used to analyze low-power commercial-off-the-shelf processors for potential hardening and use in future space missions.

关键词： Commercial off the Shelf Space Missions Onboard Computing Performance Space Computing Sensor Technology Ground Station Central Processing Unit BAE Systems field programmable gate array Graphics Processing Unit

来源：评论

学校读者我要写书评

暂无评论

High-speed fingerprint verification using an optical correlator

引用

OPTICAL ENGINEERING 1999年第1期38卷 99-107页

作者： Stoianov, A Souter, C Graham, A Mytec Technol Inc Toronto ON M2K 2S5 Canada

A real-time, VanderLugt-type optical correlator using a single SLM is developed. A field programmable gate array is used to capture and process images obtained from a CCD camera at a rate of 60 video fields/s. During both enrollment and verification, a finger slides over a glass prism and is input to the system via the frustration of the total internal reflection process. An autoenrollment procedure captures the optimal image during each slide. An optimal composite filter is implemented. The correlation detection process comprises real-time tracking of the correlation peak while the finger is sliding and a decision process based on projective decision boundaries. Real-life tests yielded a false rejection rate of 1% and a false acceptance rate of 0.2%. (C) 1999 Society of Photo-Optical Instrumentation Engineers. [S0091-3286(99)00901-0].

关键词： optical correlators field programmable gate array peak tracking projective decision boundaries false rejection/acceptance rate

来源：评论

学校读者我要写书评

暂无评论

Design and implementation of a genetic algorithm IP core on an FPGA for path planning of mobile robots

引用

TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2016年第6期24卷 5055-5067页

作者： Tuncer, Adem Yildirim, Mehmet Yalova Univ Fac Engn Dept Comp Engn Yalova Turkey Kocaeli Univ Fac Engn Dept Informat Syst Engn Kocaeli Turkey

This paper presents a hardware realization of a genetic algorithm (GA) for the path planning problem of mobile robots on a field programmable gate array (FPGA). A customized GA intellectual property (IP) core was designed and implemented on an FPGA. A Xilinx xupv5-1x110t FPGA device was used as the hardware platform. The proposed GA IP core was applied to a Pioneer 3-DX mobile robot to confirm its path planning performance. For localization tasks, a camera mounted on the ceiling of the laboratory was utilized to receive images and allow the robot to determine its own location and the obstacles in the environment. In this way, procedures of path planning were tested in a real laboratory environment. An impressive time speedup was achieved when compared with its software implementation. Experimental results illustrate the effectiveness of the GA IP core hardware.

关键词： Genetic algorithm path planning mobile robot field programmable gate array intellectual property core

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：