Radar systems often use low power, continuous waveform radio frequency (RF) modulations and require high-speed adaptive signal processors to provide the necessary processing gain to detect small radar cross-section ta...
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Radar systems often use low power, continuous waveform radio frequency (RF) modulations and require high-speed adaptive signal processors to provide the necessary processing gain to detect small radar cross-section targets in clutter on range-Doppler maps. Counter-radar technologies include digital RF memories (DRFMs) that attempt to provide multiple, structured false targets with clutter, for example, using a pipelined, finite impulse response arrangement of complex range bin processors. This thesis investigates high-capacity field-programmablegatearray (FPGA) technology to enable on-the-fly flexibility and reconfigurability for both radar signal processing and DRFM electronic attack using a Xilinx Virtex Ultrascale+. A three-stage range, Doppler, post-detection integration radar modulation compression circuit is designed and quantified. A range compression circuit with a peak power consumption of 6.100W and a post-implementation utilization of 11% was designed. The Doppler filter bank was designed at 400 MHz with a peak power consumption of 2.688W and a post-implementation utilization of 9%. A coherent integration processor at 400 MHz had a peak power consumption of 2.517W and a post-implementation utilization of 9%. In addition, a DRFM complex range bin processor was designed and quantified at 500 MHz and had a peak power 2.543W with a post-implementation utilization of 11%.
Gasoline controlled auto-ignition combustion offers high potential for CO2 emission reduction, but faces challenges regarding combustion stability and high sensitivity to changing boundary conditions. Combustion chamb...
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Gasoline controlled auto-ignition combustion offers high potential for CO2 emission reduction, but faces challenges regarding combustion stability and high sensitivity to changing boundary conditions. Combustion chamber recirculation allows a wide operation range, but results in a strong coupling of consecutive cycles due to residuals that are transferred to the subsequent combustion cycle. The cycle coupling leads to phases of unstable operation with reduced efficiency and increased emission levels. State-of-the-art control algorithms use data-driven models of gasoline controlled autoignition combustion to achieve cycle-to-cycle control of the process or use offline calibration and optimization. A closed-loop control is proposed and implemented on a rapid control prototyping engine control unit. The control algorithm continuously calculates the current residual fuel in the combustion chamber. The heat release is observed and compared with the theoretical heat release of the injected fuel mass. The rate of unburned fuel mass transferred to the subsequent cycle is calculated offline by a detailed gas exchange model. Based on this information, the control algorithm adapts the injected fuel quantity for each cycle individually using an inverse injector model. In this article, a concept for decoupling consecutive cycles is presented to reduce the deviations of the indicated mean effective pressure and thus the heat release. Unstable sequences are analyzed in the time domain, and unburned residuals are identified as a strong correlating factor for consecutive cycles. Using real-time cylinder pressure analysis based on a field programmable gate array enables the online calculation of unburned residual fuel. Based on this calculation, the injection of each cycle can be adapted individually to decouple consecutive cycles and avoid unstable operation. The results of the control algorithm and the stabilization of the gasoline controlled auto-ignition combustion are validated
The next generation of adaptive optics (AO) systems on large telescopes will require immense computation performance and memory bandwidth, both of which are challenging with the technology available today. The objecti...
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The next generation of adaptive optics (AO) systems on large telescopes will require immense computation performance and memory bandwidth, both of which are challenging with the technology available today. The objective of this work is to create a future-proof AO platform on a field programmable gate array (FPGA) architecture, which scales with the number of subapertures, pixels per subaperture, and external memory. We have created a scalable AO platform with an off-the-shelf FPGA development board, which provides an AO reconstruction time only limited by the external memory bandwidth. SPARC uses the same logic resources irrespective of the number of subapertures in the AO system. This paper is aimed at embedded developers who are interested in the FPGA design and the accompanying hardware interfaces. The central theme of this paper is to show how scalability is incorporated at different levels of the FPGA implementation. This work is a continuation of part 1 of the paper, which explains the concept, objectives, control scheme, and method of validation used for testing the platform. (C) 2018 Society of Photo-Optical Instrumentation Engineers (SPIE).
The numerical substructure of a real-time hybrid simulation (RTHS) has been considerably simplified through condensation methods to relieve the burden incurred by computation. However, this simplification severely lim...
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The numerical substructure of a real-time hybrid simulation (RTHS) has been considerably simplified through condensation methods to relieve the burden incurred by computation. However, this simplification severely limits the application of RTHS to structures whose numerical parts are complex and require a large number of degrees of freedom (DOFs) to model. Thus, in this study, a vector form intrinsic finite element (VFIFE) analysis is introduced to RTHS with numerical substructures containing a large number of DOFs. A field programmable gate array (FPGA) is also employed to speed-up the numerical simulation of the VFIFE through parallel computing in RTHS. The characteristics of this parallel RTHS platform using VFIFE and FPGA are discussed in detail in this paper. A simple RTHS was carried out to verify the feasibility of this new platform, followed by a complex virtual RTHS to show its powerful computational capability.
This article presents a security module based on a field programmable gate array (FPGA) to mitigate man-in-the-middle cyber attacks. Nowadays, the FPGA is considered to be the state of the art in nuclear power plants ...
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This article presents a security module based on a field programmable gate array (FPGA) to mitigate man-in-the-middle cyber attacks. Nowadays, the FPGA is considered to be the state of the art in nuclear power plants I&C systems due to its flexibility, reconfigurability, and maintainability of the FPGA technology;it also provides acceptable solutions for embedded computing applications that require cybersecurity. The proposed FPGA-based security module is developed to mitigate information-gathering attacks, which can be made by gaining physical access to the network, e.g., a man-in-the-middle attack, using a cryptographic process to ensure data confidentiality and integrity and prevent injecting malware or malicious data into the critical digital assets of a nuclear power plant data communication system. A model-based system engineering approach is applied. System requirements analysis and enhanced function flow block diagrams are created and simulated using CORE9 to compare the performance of the current and developed systems. Hardware description language code for encryption and serial communication is developed using Vivado Design Suite 2017.2 as a programming tool to run the system synthesis and implementation for performance simulation and design verification. Simple windows are developed using Java for physical testing and communication between a personal computer and the FPGA. (C) 2018 Korean Nuclear Society, Published by Elsevier Korea LLC.
Accurate estimation of power signal frequency is an important requirement for many application areas that include system protection, energy quality monitoring and instrumentation. Though significant efforts have been ...
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Accurate estimation of power signal frequency is an important requirement for many application areas that include system protection, energy quality monitoring and instrumentation. Though significant efforts have been made since long to develop potent algorithms for accurate estimation of power signal frequency, still their accuracy and convergence speed are a challenge under sudden frequency drift and variations. Therefore, this study focuses on a low complexity adaptive linear element filter using quadratic signal model, whose parameters are adjusted using a fast variable step size fuzzy logic-based learning algorithm to provide better convergence and noise rejection properties for the estimation of frequency from noisy and distorted signals. In addition, the new filter has also been implemented on a field programmable gate array hardware and Xilinx 14.2 with Sysgen software for the tracking of dynamic signal parameters in single and three phase power networks. Various numerical and experimental results are addressed for estimation of frequency of time varying sinusoids.
The objective of this paper is to describe an implementation of a Dynamic Matrix Control (DMC) algorithm for a field programmable gate array (FPGA). The DMC algorithm is implemented in a universal version for multiple...
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The objective of this paper is to describe an implementation of a Dynamic Matrix Control (DMC) algorithm for a field programmable gate array (FPGA). The DMC algorithm is implemented in a universal version for multiple-input multiple-output dynamic processes. The results of real experiments are presented in which the DE2i-150 development board produced by Terasic with Intel Cyclone IV GX chip is used. As the controlled process a laboratory stand especially developed for this work is used, which is a dynamic system with two manipulated inputs and two controlled outputs. The implemented DMC controller is very fast, it may be used for controlling processed which need sampling periods of a millisecond order. (C) 2018, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.
GaN devices used to drive a three-phase inverter drive motor can greatly improve the switching frequency and increase the power density. However, the traditional microcontroller unit (MCU) controller cannot achieve hi...
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GaN devices used to drive a three-phase inverter drive motor can greatly improve the switching frequency and increase the power density. However, the traditional microcontroller unit (MCU) controller cannot achieve high switching frequency single-cycle control. This paper describes the use of GaN devices in the design of a three-phase motor drive system to drive a permanent magnet synchronous motor and vector control algorithm, that is completely implemented in a field programmable gate array. The system achieves 200-kHz switching frequency single-cycle precise control, as verified by the experimental results.
In this work, the design of a low-cost, field programmable gate array (FPGA)-based digital hardware platform that implements image processing algorithms for real-time distance measurement is presented. Using embedded ...
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In this work, the design of a low-cost, field programmable gate array (FPGA)-based digital hardware platform that implements image processing algorithms for real-time distance measurement is presented. Using embedded development kit (EDK) tools from Xilinx, the system is developed on a spartan3 / xc3s400, one of the common and low cost field programmable gate arrays from the Xilinx Spartan family. Latency of the hardware is less than 100 mu s in 5000 clock cycles with 50MHz maximum frequency which is way less than MATLAB software performance about 82ms. Simulation and experimental results clearly indicate the potential of the presented FGPA-based platform for realtime distance measurement of images acquired from our camera setup. Thus, this platform can be used in any system with the needs of real-time or semi real-time machine vision.
We present a field-programmablegatearray (FPGA) based control system that has been implemented to control a strontium optical lattice clock at the National Physical Laboratory, UK. Bespoke printed circuit boards hav...
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We present a field-programmablegatearray (FPGA) based control system that has been implemented to control a strontium optical lattice clock at the National Physical Laboratory, UK. Bespoke printed circuit boards have been designed and manufactured, including an 8-channel, 16-bit digital to analog converter board with a 2 mu s update rate and a 4-channel direct-digital synthesis board clocked at 1 GHz. Each board includes its own FPGA with 28 digital output lines available alongside the specialized analog or radio frequency outputs. The system is scalable to a large number of control lines by stacking the individual boards in a master-slave arrangement. The timing of the digital and analog outputs is based on the FPGA clock and is thus very predictable and exhibits low jitter. A particular advantage of our hardware is its large data buffers that, when combined with a pseudoclock structure, allow complex waveforms to be created. A high reliability of the system has been demonstrated during extended atomic clock frequency comparisons. Published under license by AIP Publishing.
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