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AIAA Propulsion and Energy Forum / IEEE Electric Aircraft Technologies Symposium (EATS)

作者： Jiang, Zhenhua Beigh, Kelly Univ Dayton Res Inst Dayton OH 45469 USA

ISBN: (数字)9781624106118

ISBN: (纸本)9781624106118

This paper presents modeling and prediction of the unknown dynamics from a variety of real-time operation data in complex physical processes or systems based on machine learning. More generally, this is a data-driven modeling approach based on physical knowledge at time of design and machine learning at runtime. The learning process may apply to the entire or partial system dynamics, while portions of the physical system dynamics may be known or given. The learned models together with the known physics-based equations can be widely used in control system design, for instance, as one component in a model predictive control (MPC) framework for integrated dynamic systems. Long short-term memory (LSTM) neural networks are chosen here, because they have additional stored states resulting from the past output, and the state storage can be internally controlled subject to the network status itself. Such controlled states can be regarded as gated states or memory blocks in a neural network, and they serve as key components of the LSTM neural network in controlling the information flow throughout the network. This paper provides technical details about the concept of a LSTM neural network that can be used to model and predict energy production in renewable sources, battery state of charge, engine fuel use (or energy efficiency), or energy demand of the payload in aerospace or energy system applications. The most compute-intensive part of the learning algorithm is solving a nonlinear optimization problem to minimize the total error between the predicted and actual outputs. After updating the learned model and parameters, the LSTM model implementation may perform certain computational steps in parallel, so as to accelerate the computing. The model learning and prediction processes can be implemented on a field programmable gate array (FPGA - a reconfigurable parallel computing device), for instance, on NI's CompactRIO modules or PXI FPGA modules. As an example, an application

关键词： Feedforward Neural Network field programmable gate array Machine Learning Energy Production Model Predictive Control Computing Framework Control System Design Energy Efficiency Parallel Computing Energy Systems

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Model Parallelism Optimization for CNN FPGA Accelerator

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ALGORITHMS 2023年第2期16卷 110-110页

作者： Wang, Jinnan Tong, Weiqin Zhi, Xiaoli Shanghai Univ Sch Comp Engn & Sci Shanghai 200444 Peoples R China Shanghai Univ Shanghai Engn Res Ctr Intelligent Comp Syst Shanghai 200444 Peoples R China

Convolutional neural networks (CNNs) have made impressive achievements in image classification and object detection. For hardware with limited resources, it is not easy to achieve CNN inference with a large number of parameters without external storage. Model parallelism is an effective way to reduce resource usage by distributing CNN inference among several devices. However, parallelizing a CNN model is not easy, because CNN models have an essentially tightly-coupled structure. In this work, we propose a novel model parallelism method to decouple the CNN structure with group convolution and a new channel shuffle procedure. Our method could eliminate inter-device synchronization while reducing the memory footprint of each device. Using the proposed model parallelism method, we designed a parallel FPGA accelerator for the classic CNN model ShuffleNet. This accelerator was further optimized with features such as aggregate read and kernel vectorization to fully exploit the hardware-level parallelism of the FPGA. We conducted experiments with ShuffleNet on two FPGA boards, each of which had an Intel Arria 10 GX1150 and 16GB DDR3 memory. The experimental results showed that when using two devices, ShuffleNet achieved a 1.42x speed increase and reduced its memory footprint by 34%, as compared to its non-parallel counterpart, while maintaining accuracy.

关键词： convolution neural network model parallelism field programmable gate array inference accelerating

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Scanning Probe Microscopy controller with advanced sampling support

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HARDWAREX 2023年 15卷 e00451页

作者： Valtr, Miroslav Klapetek, Petr Martinek, Jan Novotny, Ondrej Jelinek, Zdenek Hortvik, Vaclav Necas, David Czech Metrol Inst Okruzni 31 Brno 63800 Czech Republic Brno Univ Technol CEITEC Purkynova 123 Brno 61200 Czech Republic Nenovision Purkynova 127 Brno 61200 Czech Republic

A low-cost Digital Signal Processor (DSP) unit for advanced Scanning Probe Microscopy measurements is presented. It is based on Red Pitaya board and custom built electronic boards with additional high bit depth AD and DA converters. By providing all the necessary information (position and time) with each data point collected it can be used for any scan path, using either existing libraries for scan path generation or creating adaptive scan paths using Lua scripting interface. The DSP is also capable of performing statistical calculations, that can be used for decision making during scan or for the scan path optimisation on the DSP level.& COPY;2023 The Author(s). Published by Elsevier Ltd. This is an open access article under the CC BY license (http://***/licenses/by/4.0/).

关键词： Scanning probe microscopy Adaptive sampling field programmable gate array

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A T-Shape Connected Multilevel Inverter Topology with a Reduced Number of Switching Devices

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INTERNATIONAL JOURNAL OF RENEWABLE ENERGY RESEARCH 2023年第4期13卷 1556-1565页

作者： Anusuya, M. Geetha, R. Ilango, R. Annamalai Univ Dept Elect Engn Chidambaram Tamilnadu India Annamalai Univ Dept Elect Engn Annamalainagar Tamilnadu India K Ramakrishna Coll Engn Dept Elect & Elect Engn Trichy India

This research endeavors a novel configuration for a single-phase Cascaded H-Bridge Multilevel Inverter (CHBMLI) using a stacked T-shape voltage generation module with a view to attaining reduced current conducting switches in the path of load. It involves the use of the collection of a string of voltage generation modules and a two-leg inverter to arrive at a novel Multilevel Inverter (MLI) topology. The MLI permits showcasing the facility of the structural design in an attempt to enlarge the scope of the CHBMLI. It follows a Multicarrier Pulse Width Modulation (MCPWM) approach for synthesizing the Pulse Width Modulation (PWM) output voltage. The prototype augurs the role of a digital PWM controller using field programmable gate array (FPGA) and the experimental outcomes validate the simulated performance in a wide range of modulation indices. The approach claims a new option of a particular topology for the MLI to suit specific applications in the real world.

关键词： Multilevel inverter Multicarrier pulse width modulation field programmable gate array Power switches

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Design and implementation of FPGA-based integrated missile actuation system and control synthesis

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INTERNATIONAL JOURNAL OF AUTOMATION AND CONTROL 2023年第5期17卷 506-528页

作者： Abozied, Mohammed Abozied Hassan Shelan, Sameh Fathey Elhalwagy, Yehia Zakarya Hendy, Hossam Mil Tech Coll Guidance Dept Cairo Egypt Mil Tech Coll Space Res Ctr Cairo Egypt

The missile's overall accuracy and autonomy are potentially affected by its actuation system and controller design. The current paper presents an integrated missile's actuation system design process in the presence of different mechanical and electrical constraints, a reliable electric actuation system (EAS) and its related control system are developed based on missile mechanical and electrical requirements. A real-time motion simulation is performed using solid work software to guarantee compatibility with the actual size, weight, and load constraints. The actuation system model is performed using a system identification technique based on real-time input-output data extraction utilising a predesigned test and control setup. A real-time floating-point PID controller based on the genetic algorithm optimisation approach is designed using MATLAB, simulated using hardware simulation utilising Modalism software, and then implemented by an embedded FPGA-based board. The novelty of this paper is the design, control, and implementation of a real-time embedded aerodynamic missile actuation system based on aerodynamic fin loading exerted in missile control surfaces. Hardware in the loop simulation is carried out with a simulated missile trajectory which presents the proposed actuation system performance, robustness, and reliability achieved through highly professional design and implementation steps and results.

关键词： missile actuation system nonlinear modelling system identification field programmable gate array FPGA PID controller

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A charge pump phase-locked loop with dual-voltage controlled VCO applied to 28nm process FPGA

A charge pump phase-locked loop with dual-voltage controlled...

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IEEE International Conference on Consumer Electronics and Computer Engineering (ICCECE)

作者： Shan, Chengyi Chen, Lei Li, Xuewu Geng, Xiaoyuan Wang, Kedi Beijing Microelect Technol Inst Beijing Peoples R China

ISBN: (纸本)9781728183190

In order to meet the increasing clock requirements of FPGAs, Phase-locked loop has been widely used in FPGAs as clock management unit. This paper introduces a charge pump phase-locked loop with dual voltage-controlled oscillator applied on a 28nm FPGA platform. On the basis of the traditional charge pump phase-locked loop, this paper designs a configurable filter, a new structure of VCO with amplification and shaping circuit. The simulation results show that the structure can effectively improve the frequency locking speed of the VCO.

关键词： Phase Locked Loop field programmable gate array Voltage Controlled Oscillator

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A study on VLSI implementation of image enhancement techniques

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2022年第10期34卷

作者： Aklak, Annis Fathima Pugazhenthi, Murugesh Yadhav Alex, John Sahaya Rani Vellore Inst Technol Sch Elect Engn Chennai Tamil Nadu India BlueBird Electromech Contracting LLC Ajman U Arab Emirates Vellore Inst Technol Ctr Healthcare Adv Innovat & Res Chennai Tamil Nadu India

In real-time, the images captured are not always appreciable for visual perception. The quality of the image relies on the illumination condition. Contrast enhancement is required to improve the visual quality of the image. In this article, the image enhancement techniques that are adaptable for real-time images are studied. Further, an investigation is done on implementing the image processing algorithms in very large-scale integration (VLSI) hardware. As the image data are comparatively larger, the computational complexity and the memory requirement are more. From the study, the need for efficient computation of such image processing algorithms is realized. The efficient computation of image processing algorithms on hardware platforms, in particular on field programmable gate array (FPGA), is reviewed. As an experiment, the gamma-transformation technique used for image enhancement is realized. Initially, the prototype is modeled using MATLAB, and then it is implemented using an FPGA.

关键词： field programmable gate array floating point multiplier image enhancement

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Bayesian Source Localization using Stochastic Computation 53

Bayesian Source Localization using Stochastic Computation

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IEEE International Symposium on Circuits and Systems (IEEE ISCAS)

作者： Krishna, Adithya Thakur, Chetan Singh Indian Inst Sci Bengaluru India

ISBN: (纸本)9781728192017

Bayesian models are challenging to implement on hardware with the conventional design methodologies due to their high computational complexity. Conventional digital architectures are designed for deterministic computation and are not optimal for implementing probabilistic algorithms on hardware. In this work, we propose an alternative method to implement the probabilistic algorithms such as Bayesian models on hardware using a stochastic computation (SC) framework. This framework leverages on the probabilistic nature of the Bayesian models and facilitates the implementation of complex probabilistic models using simple logic gates. From an application standpoint, we propose a novel Bayesian source localization model (BSLM) that estimates a source's position in a noisy environment by solving the Bayesian recursive equation implemented on field programmable gate array (FPGA) with low resource utilization. The proposed SC design framework will pave the way to build complex probabilistic algorithms for real-time edge computing applications.

关键词： Bayesian Inference field programmable gate array Unmanned Ground Vehicle Hardware Architectures

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Modeling A Loop Back Test For Radar Phased array Digital Receiver Exciters Using Python

Modeling A Loop Back Test For Radar Phased Array Digital Rec...

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IEEE Radio and Wireless Symposium (RWS) / IEEE Space Hardware and Radio Conference (SHaRC)

作者： Mortensen, John Wickert, Mark Univ Colorado Dept Elect & Comp Engn Colorado Springs CO 80918 USA

ISBN: (纸本)9781665415835

Active Electronically Scanned arrays (AESAs) used in radar systems typically use digital receiver exciters (DREX) units. Functional testing of DREX units can be challenging due to their complexity. This is true for lab testing but is especially true for field testing. This work describes a method for testing that uses a loop back approach. Three loop back tests are described which essentially involves one or more signals from transmit channels routed to one or more receive channels. An example digital receiver exciter is described along with the data converters and field programmable gate array. The loop back test method is then described, and a Python program is developed that simulates the approach. Initial testing of the receive section is then presented.

关键词： phased arrays digital receiver exciter (DREX) field programmable gate array

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Accelerating the Activation Function Selection for Hybrid Deep Neural Networks - FPGA Implementation

Accelerating the Activation Function Selection for Hybrid De...

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IEEE Region 10 Symposium (TENSYMP) - Good Technologies for Creating Future

作者： Waseem, Shaik Mohammed Suraj, Alavala Venkata Roy, Subir Kumar IIIT Bangalore VLSI Syst Res Grp Bangalore Karnataka India

ISBN: (纸本)9781665400268

Much of the work in literature about hardware implementations of deep neural networks illustrates the multiplication of input signal with weights and summing up the data. Work in this paper is focused on the hardware implementation of non-linear functions (activation functions), along with hardware rendition of the automatic selection of activation function for each layer in the neural network in order to increase the accuracy. We have used field programmable gate array (FPGA) based hardware development platform to add in the advantages of the power efficiency and edge deployment. Our novel hardware design modules to this extent are capable of accelerating the entire process of activation function selection and activation function output generation along with its derivative. The tabulated results in this paper, for power and resource utilization generated through Xilinx (R) Vivado platform by targeting our design modules towards Avnet (R) Ultra96 v2 Evaluation board prove the sheer hardware novelty in terms of less hardware foot print and energy efficiency in comparison to the GPU (Graphics Processing Unit) and CPU (Central Processing Unit) based executions along with FPGA based implementations of few activation functions reported in literature.

关键词： Activation Function field programmable gate array Hybrid Deep neural networks Hardware Accelerator

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