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检索条件"主题词=Field Programmable Gate array"

共 1335 条记录，以下是311-320 订阅

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FPGA Implementation of Memory-Based Digital Predistorters with High-Level Synthesis

FPGA Implementation of Memory-Based Digital Predistorters wi...

引用

IEEE Topical Conference on RF/Microwave Power Amplifiers for Radio and Wireless Applications (PAWR)

作者： Li, Wantao Guillena, Estefania Montoro, Gabriel Gilabert, Pere L. UPC Barcelona Tech Dept Sig Theory Comm Castelldefels Spain

ISBN: (纸本)9781665404099

This paper presents a scalable look-up table (LUT) architecture for implementing digital predistortion (DPD) linearizers in a field programmable gate array (FPGA) by using the high-level synthesis (HLS) software. This architecture can be used in most memory-based DPD behavioral models whose basis functions can be expressed as a combination of basic predistortion cells (BPCs). The advantages of the proposed LUT-based architecture are evidenced in terms of resources usage, throughput. and power consumption of the corresponding programmable logic (PL). The DPD linearization performance was tested considering different LUT sizes on a load-modulated balanced amplifier (LMBA), using two LTE 20 MHz signals over a total 60 MHz instantaneous bandwidth.

关键词： field programmable gate array load-modulated balanced amplifier power efficiency digital predistortion

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Neural Network Based Glitch Physically Unclonable Function 12

Neural Network Based Glitch Physically Unclonable Function

引用

12th IEEE Annual Ubiquitous Computing, Electronics and Mobile Communication Conference (UEMCON)

作者： Nozaki, Yusuke Yoshikawa, Masaya Meijo Univ Dept Informat Engn Nagoya Aichi Japan

ISBN: (纸本)9781665406901

The security issues of artificial intelligence (AI) system are attracting attention. The neural network physically unclonable function (NN PUF) have been proposed to improve the security of AI devices. The NN PUF combines two functions: AI inference and device authentication. In device authentication, a unique ID is generated for each device by using the manufacturing variation of large-scale integration (LSI). The NN PUF uses the delay difference of NN computation time for ID generation. However, the conventional NN PUF is known to have low uniqueness in field programmable gate array (FPGA) implementation. Therefore, the present study proposes a new NN PUF that improves uniqueness. Evaluation experiments with FPGAs showed that the proposed NN PUF significantly improved uniqueness compared to the conventional NN PUF.

关键词： physically unclonable function neural network glitch physically unclonable function hardware security field programmable gate array

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Synthesis of Temporal Machines with Operational Transformation of State Codes 31

Synthesis of Temporal Machines with Operational Transformati...

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31st International Scientific Symposium on Metrology and Metrology Assurance (MMA)

作者： Miroshnyk, Marina Zaichenko, Olga Miroshnyk, Anatolii Zaichenko, Nataliia Ukrainian State Univ Railway Transport Spesialised Comp Syst Kharkiv Ukraine Kharkiv Natl Univ Radioelelect Design & Operat Elect Devices Kharkiv Ukraine Natl Tech Univ Kharkiv Polytech Inst Spesialised Comp Syst Kharkiv Ukraine Kharkiv Natl Univ Radioelelect Microelect Elect Devices & Appliances Kharkiv Ukraine

ISBN: (纸本)9781665445375

The actual scientific problem of development methods aimed at reducing of hardware expenses in the logical circuit of the finite state machine, is solved by adaptation of the finite state machine (FSM) circuit to the characteristics of the implemented control algorithm. The object of the research encompasses process of optimization of finite state machines circuits. The subject of the research is the models and methods of synthesis of finite state machines, aimed at reducing the hardware expenses in the circuit of the machine. The research is based on a systematic analysis of the results of modern theoretical and applied developments made by domestic and foreign scientists in the digital control units sphere. The theoretical novelty is distinguished by the fact that a method is proposed for choosing constants in operations for operational state transitions on the base of the determinant of the matrix. The practical novelty lies in the implementation in Quartus by the behavioral method, in contrast to the classical method.

关键词： operational transformation of state codes finite state machines FSM hardware description language VHDL temporal automata field programmable gate array FPGA graph scheme of algorithm GSA

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Temperature Characterisation of the DSP Delay Line 7

Temperature Characterisation of the DSP Delay Line

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7th International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP)

作者： Tancock, Scott Rarity, John Dahnoun, Naim Univ Bristol Sch Comp Sci Elect Engn & Engn Math Bristol Avon England Univ Bristol Ctr Quantum Photon Bristol Avon England

ISBN: (纸本)9781665436977

Time-to-Digital Converters (TDCs) are important measurement devices for fields such as quantum computing and range-finding. To implement these devices, FPGAs are an attractive option due to their low cost relative to ASICs, reconfigurability, updatability and off-the-shelf availability. However, these devices are often sensitive to changes in temperature due to temperature-dependent changes in electrical characteristics (Process-Voltage-Temperature, PVT variations), and thus must be characterised to avoid erroneous measurements. In our past papers, we demonstrated the implementation of Tapped Delay Line (TDL) TDCs using the DSP blocks available on Xilinx FPGAs. In this paper, we characterise the variability of the TDC core with respect to temperature in terms of Single-Shot Precision (SSP), resolution, Integral Non-Linearity (INL) and Differential Non-Linearity (DNL). Over a temperature range of 68.3 degrees C, we demonstrate an 8.23 ps difference in SSP, a 3.89 ps difference in cubic-mean resolution, a 247 ps difference in INL and a 19.4 ps difference in DNL.

关键词： field programmable gate array Time to Digital Converter DSP Xilinx Temperature Characterisation Time Measurement

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Developments in Time-to-Digital Converters during 2020 7

Developments in Time-to-Digital Converters during 2020

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7th International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP)

作者： Tancock, Scott Rarity, John Dahnoun, Naim Univ Bristol Sch Comp Sci Elect Engn & Engn Math Bristol Avon England Univ Bristol Ctr Quantum Photon Bristol Avon England

ISBN: (纸本)9781665436977

Time-to-Digital Converters (TDCs) are important devices in many systems, such as Time-of-Flight, frequency locking, nuclear experiments and metrology, and quantum versions of all these. Therefore, research into TDCs is important to bring these technologies to wider audiences. There was plenty of TDC innovation in 2020 despite the global pandemic, and in this review paper we summarise the research related to TDC architectures. We show four review and analysis papers, eight papers on application-specific integrated circuits, five papers on field-programmable gate arrays, one paper on discrete TDCs, and four papers on novel applications of the TDC core. This trend of excellent research looks set to continue into 2021, with 21 papers already mentioning TDC despite major conferences such as NoMeTDC and I2MTC not having occurred as of writing.

关键词： Time to Digital Converter Review field programmable gate array Application Specific Integrated Circuit Time Measurement

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A Multimode FPGA-based Modem with Embedded Σ-Δ Analog-to-Digital Converter for Software Defined Radio 20

A Multimode FPGA-based Modem with Embedded Σ-Δ Analog-to-D...

引用

12th Annual Wireless Telecommunications Symposium (WTS)

作者： Duarte-Junior, J. G. Brito-Filho, E. A. Univ Fed Rio Grande do Norte Natal RN Brazil Fed Univ Semiarid Reg Mossoro Brazil

ISBN: (纸本)9781728184807

field programmable gate arrays (FPGAs) have been widely used in applications involving hard signal processing with reconfiguration capabilities. One promising application that requires those capabilities is Software Defined Radio (SDR). In this work a novel design of SDR modem based on FPGA is proposed. Using an experimental setup with an embedded sigma-delta A/D converter and a multimode (ASK, FSK and PSK) modem as proof of concept and with most of the tasks running in FPGA. The modem was tested and proved to be efficient using just about 1 % of available logic blocks of the adopted FPGA with a maximum operating frequency as high as 148 MHz for low cost devices, being possible the implementation in several models of FPGAs available in the market.

关键词： Software Defined Radio field programmable gate array Analog-to-Digital Converters Sigma-Delta Modem Hardware Description Language

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Lossless Compression of Bitstream Configuration Files: Towards FPGA Cloud 19

Lossless Compression of Bitstream Configuration Files: Towar...

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19th IEEE International Symposium on Parallel and Distributed Processing with Applications (IEEE ISPA)

作者： Wang, Jinyu Kang, Yifei Feng, Yaqi Li, Yiwen Wu, Weiguo Xing, Guoliang Xi An Jiao Tong Univ Sch Comp Sci & Technol Xian Peoples R China Chinese Univ Hong Kong Dept Informat Engn Hong Kong Peoples R China

ISBN: (纸本)9781665435741

With the development of integrated circuit technology, the scale of field programmable gate array (FPGA) devices and the quantity of on-chip resources have been increased dramatically, as well as the size of configuration files, rendering the configuration process time-consuming. Especially, in the cloud-based multiple FPGAs co-designs, the transmission of large scale bitstream configuration files in public networks may suffer unpredictable delay, which causes circuits with high real-time requirements failed to be timely executed. To address this challenge, we divide a configuration file into three portions which have different data structures, and different compression methods are proposed to fit the data structure of each part to obtain a lower compression rate. For the portion which describes the FPGA on-chip resources, an LSTM and ID-CNN based arithmetic coding compression method is introduced. In this way, the compression problem is converted to an estimation of a conditional probability distribution problem. Finally, to improve the prediction efficiency of the neural network, a cache based neural network inference acceleration method is proposed. Our approach is validated on the standard benchmark data sets and the average compression rate is 28.89%. Compared with seven different compression methods, our approach improves the compression rate by up to 39.45%.

关键词： bitstream configuration file field programmable gate array arithmetic coding neural network inference acceleration

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Resource and Energy Efficient Implementation of ECG Classifier using Binarized CNN for Edge AI Devices 53

Resource and Energy Efficient Implementation of ECG Classifi...

引用

IEEE International Symposium on Circuits and Systems (IEEE ISCAS)

作者： Wong, David Liang Tai Li, Yongfu John, Deepu Ho, Weng Khuen Heng, Chun Huat Natl Univ Singapore Elect & Comp Engn Singapore Singapore Shanghai Jiao Tong Univ Dept Micronano Elect Shanghai Peoples R China Shanghai Jiao Tong Univ MoE Key Lab Artificial Intelligence Shanghai Peoples R China Univ Coll Dublin Sch Elect & Elect Engn Dublin Ireland

ISBN: (纸本)9781728192017

Wearable Artificial Intelligence-of-Things (AIoT) devices demand smart gadgets that are both resource and energy-efficient. In this paper, we explore efficient implementation of binary convolutional neural network employing function merging and block reuse techniques. The hardware implemented in field programmable gate array (FPGA) platform can classify ventricular beat in electrocardiogram achieving accuracy of 97.5%, sensitivity of 85.7%, specificity of 99.0%, precision of 92.3%, and F1-score of 88.9% while consuming only 10.5-mu W of dynamic power dissipation.

关键词： Artificial Intelligence-of-Things low-power design wearable field programmable gate array ECG co-design convolutional neural network inference fusion state machine

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Real-time Performance Evaluation of Single Phase 7 Level Z-Source Boost Inverter 7

Real-time Performance Evaluation of Single Phase 7 Level Z-S...

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7th International Conference on Electrical Energy Systems (ICEES)

作者： Prasad, Hanuman Bhadane, Kishor V. Kumar, Parveen Model Inst Engn & Technol Dept Elect Engn Jammu India Amrutvahini Coll Engn Dept Elect Engn Sangamner Maharashtra India

ISBN: (纸本)9781728176123

Multilevel inverter has been familiarized as a popular topology for DC-AC power conversion. This paper illustrates the real-time performance evolution of seven level z-source diode clamp multilevel inverter. The field programmable gate array (FPGA) integrated real time simulators consists of multiprocessor and computer clusters are the main hardware platforms for real-time simulations. The real time (RT) lab software enables the parallel simulation of an electrical circuit on clusters of personal computer running at sampling time 10 mu s. The integration of multilevel inverter and z-source energy conversion are used for DC-AC converter for high power applications with low total harmonics distortion. An impedance network has two passive elements such as two inductors and two capacitors connected between DC power source and multilevel inverter circuit. It provides a unique feature such as the boost the inverter output voltage and reduces the harmonic content in the output voltage as compared to the classic multilevel inverter. The real time results are verified the proposed system with a specified time step 10 mu s andfrequency is 10 KHz.

关键词： Real-time digital simulators field programmable gate array Software in the loop multilevel inverter hardware in the loop etc

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FPGA Implementation of Interleaved Modular Multiplier with Improved Area-time Efficiency 11

FPGA Implementation of Interleaved Modular Multiplier with I...

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11th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems - Technology and Applications (IDAACS)

作者： Coliban, Radu-Mihai Transilvania Univ Dept Elect & Comp Bd Eroilor 29 Brasov 500036 Romania

ISBN: (纸本)9781665426053

Modular multiplication is the fundamental operation in Elliptic Curve Cryptography (ECC) and a multitude of hardware implementations have been developed so far. In this paper, a series of modifications to a high performance radix-2 interleaved modular multiplication architecture are proposed. The design was implemented on a Virtex-7 FPGA for five prime fields recommended for ECC by the National Institute of Standards and Technology (NIST), showing a significant improvement in area-time efficiency in comparison to the original architecture.

关键词： modular multiplication interleaved multiplication field programmable gate array elliptic curve cryptography

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