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High-frequency pulse width modulation implementation using FPGA and CPLD ICs

JOURNAL OF SYSTEMS ARCHITECTURE 2006年第6期52卷 332-344页

作者： Koutroulis, Eftichios Dollas, Apostolos Kalaitzakis, Kostas Tech Univ Crete Dept Elect & Comp Engn GR-73100 Khania Greece

Pulse width modulation (PWM) has been widely used in power converter control. Most high power level converters operate at switching frequencies up to 500 kHz, while operating frequencies in excess of 1 MHz at high power levels can be achieved using the planar transformer technology. The contribution of this paper is the development of a high-frequency PWM generator architecture for power converter control using FPGA and CPLD ICs. The resulting PWM frequency depends on the target FPGA or CPLD device speed grade and the duty cycle resolution requirements. The post-layout timing simulation results are presented, showing that PWM frequencies up to 3.985 MHz can be produced with a duty cycle resolution of 1.56%. Additionally, experimental results are also presented for low cost functional verification of the proposed architecture. (c) 2005 Elsevier B.V. All rights reserved.

关键词： pulse width modulation power converters field programmable gate array CPLD counter

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Development of mass spectrometry by high energy focused heavy ion beam: MeV SIMS with 8 MeV Cl⁷⁺ beam

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NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION B-BEAM INTERACTIONS WITH MATERIALS AND ATOMS 2014年 332卷 22-27页

作者： Jeromel, Luka Siketic, Zdravko Potocnik, Nina Ogrinc Vavpetic, Primoz Rupnik, Zdravko Bucar, Klemen Pelicon, Primoz Jozef Stefan Inst SI-1000 Ljubljana Slovenia Rudjer Boskovic Inst Zagreb 10000 Croatia LOTRIC Metrol Ltd SI-4227 Selca Slovenia

Particle induced X-ray emission (PIXE) at microprobe of jozef Stefan Institute is used to measure two-dimensional quantitative elemental maps of biological tissue. To improve chemical and biological understanding of the processes in vivo, supplementary information about chemical bonding and/or molecular distributions could be obtained by heavy-ion induced molecular desorption and a corresponding mass spectroscopy with Time-Of-Flight (TOF) mass spectrometer. As the method combines the use of heavy focused ions in MeV energy range and TOF Secondary Ion Mass Spectrometry, it is denoted as MeV SIMS. At jozef Stefan Institute, we constructed a linear TOF spectrometer and mount it to our multipurpose nuclear microprobe. A beam of 8 MeV Cl-35(7+) could be focused to a diameter of better than 3 mu m x 3 mu m and pulsed by electrostatic deflection at the high-energy side of accelerator. TOF mass spectrometer incorporates an 1 m long drift tube and a double stack microchannel plate (MCP) as a stop detector positioned at the end of the drift path. Secondary ions are focused at MCP using electrostatic cylindrical einzel lens. Time of flight spectra are currently acquired with a single-hit time-to-digital converter. Pulsed ion beam produces a shower of secondary ions that are ejected from positively biased target and accelerated towards MCP. We start our time measurement simultaneously with the start of the beam pulse. Signal of the first ion hitting MCP is used to stop the time measurement. Standard pulses proportional to the time of flight are produced with time to analog converter (TAC) and fed into analog-to-digital converter to obtain a time histogram. To enable efficient detection of desorbed fragments with higher molecular masses, which are of particular interest, we recently implemented a state-of art field programmable gate array (FPGA)-based multi-hit TOF acquisition. To test the system we used focused 8 MeV Cl-35(7+) ion beam with pulse length of 180 ns. Mass resoluti

关键词： Mass spectrometry Focused ion beam field programmable gate array Micro-PIXE MeV-SIMS Dual imaging mode

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Efficient FPGA-based real-time implementation of an SVPWM algorithm for a delta inverter

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IET POWER ELECTRONICS 2018年第9期11卷 1611-1619页

作者： Alouane, Asma Ben Rhouma, Asma Hamouda, Mahmoud Khedher, Adel Univ Sousse Erriadh Lab LATIS Natl Engn Sch Sousse ENISO Sousse 4023 Tunisia

This study proposes an efficient field programmable gate array (FPGA) implementation method of an enhanced space vector pulse width modulation (SVPWM) algorithm for a delta inverter. The overall hardware configuration of the FPGA is made graphically using the high-level Xilinx system generator (XSG) programming tools. The proposed descriptive XSG model is first evaluated by running a hardware co-simulation test. The comparative study with computer simulations performed with Simulink shows a good agreement between the results of both methods, which approves the accuracy of the proposed descriptive XSG model. Moreover, an experimental test is carried out on a laboratory prototype of the delta inverter feeding an induction machine. The obtained high quality of the load currents confirms the feasibility of the proposed enhanced SVPWM algorithm and the effectiveness of its implementation method on FPGA.

关键词： field programmable gate arrays PWM invertors Efficient FPGA-based real-time implementation SVPWM algorithm delta inverter field programmable gate array enhanced space vector pulse width modulation algorithm hardware configuration high-level Xilinx system generator programming tools XSG programming tools hardware co-simulation test computer simulations Simulink descriptive XSG model induction machine load currents

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Development design and demonstration of very high-speed multi-antenna digital receiver

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IET RADAR SONAR AND NAVIGATION 2018年第5期12卷 523-529页

作者： Sun, Weiwei Vertatschitsch, Laura Sahr, John D. Univ Washington Dept Elect Engn Seattle WA 98195 USA Syst & Technol Res Woburn MA USA

The authors present initial results from the fourth-generation receiver for the Manastash Ridge radar, which is a distributed passive radar system used for ionospheric physics and engineering studies. This receiver permits simultaneous access to the high-frequency (HF), very HF (VHF), and ultra HF (UHF) spectrum by sampling at speeds up to 5 billion samples/s on multiple antennas. This system has large aggregate bandwidth;it can simultaneously collect the entire VHF FM broadcast band as well as several UHF DTV broadcasts. The receiver adopts direct sampling architecture;therefore, high dynamic range is achieved with decimation for narrowband signals. Most of the analogue signal path is eliminated, yielding excellent linearity, and high-speed digital signal processing in the field programmable gate array (FPGA) yields low-latency real-time operation. The authors also discuss algorithms to make effective use of the FPGA. For example, the sampler runs 16 times faster than the FPGA, so initial FPGA processing requires parallel algorithms. In the authors design, the downconverter passband centre frequencies and spectral widths are selectable at run time, and can be changed in a few milliseconds. The authors FPGA computes in fixed point math, which presents both opportunities and challenges in managing precision during the signal processing for networking and for subsequent signal processing.

关键词： antenna arrays radar antennas radar receivers passive radar radar signal processing signal sampling field programmable gate arrays parallel algorithms fixed point arithmetic very high-speed multiantenna digital receiver demonstration very high-speed multiantenna digital receiver Development design fourth-generation receiver Manastash Ridge radar distributed passive radar system high-frequency spectrum ultra HF spectrum very HF spectrum VHF FM broadcast UHF DTV broadcasts direct sampling architecture high dynamic range high-speed digital signal processing field programmable gate array FPGA low-latency real-time operation parallel algorithms fixed point math

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Hardware architectures for eigenvalue computation of real symmetric matrices

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IET COMPUTERS AND DIGITAL TECHNIQUES 2009年第1期3卷 72-84页

作者： Liu, Y. Bouganis, C. -S. Cheung, P. Y. K. Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn London SW7 2AZ England

Computation of eigenvalues is essential in many applications in the fields of science and engineering. When the application of interest requires the computation of eigenvalues of high throughput or real-time performance, a hardware implementation of an eigenvalue computation block is often employed. The problem of eigenvalue computation of real symmetric matrices is focused upon. For the general case of a symmetric matrix eigenvalue problem, the approximate Jacobi method is proposed, where for the special case of a 3 x 3 symmetric matrix, an algebraic-based method is introduced. The proposed methods are compared with various other approaches reported in the literature. Results obtained by mapping the above architectures on a field programmble gate array device illustrate the advantages of the proposed methods over the existing ones.

关键词： algebraic-based method real symmetric matrices hardware architectures reconfigurable architectures approximate Jacobi method eigenvalues and eigenfunctions eigenvalue computation block eigenvalue computation field programmable gate arrays Jacobian matrices field programmable gate array process algebra

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High-Throughput, Sorted QR Accelerator for Non-Linear Processing in Open-RAN Systems

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IEEE ACCESS 2024年 12卷 44564-44572页

作者： Thomas, Thomas James Filo, Marcin Nikitopoulos, Konstantinos Univ Surrey Inst Commun Syst 5G & 6G Innovat Ctr Wireless Syst Lab Guildford GU27XH England

Open Radio Access Networks (Open-RANs) require cost- and energy-efficient solutions to facilitate their large-scale deployment. A significant concern in multiple-input multiple-output (MIMO) systems employing traditional linear processing is the substantial number of radio frequency (RF) chains at the base station (BS), which is required to ensure accurate decoding of the spatially multiplexed streams. Recently, however, practical non-linear approaches, which facilitate near-optimal parallelizable tree searches, have been successfully implemented on actual systems and have demonstrated the capability to considerably reduce the required RF chains without affecting user performance. Similar to QR decomposition (QRD), which is used to perform channel inversion in linear systems, these non-linear approaches employ a sorted QRD (SQRD) to curtail the search complexity. However, this can be a significant bottleneck for general software-based non-linear solutions, preventing them from fully exploiting their gains. To address the latency limitations of SQRD, this work presents a high-throughput hardware accelerator based on reformulating the underlying Modified Gram Schmidt process (MGS) to extract further parallelism than previous designs. Implementations of the proposed architecture demonstrate at least 2-fold improvements in the achievable throughput and processing latency over existing 4 x 4 and 8 x 8 field-programmable gate array (FPGA) implementations and can be scaled up to 16 x 16 MIMO systems. Furthermore, the proposed accelerator was integrated with a software framework that can considerably offload the processing burden for a higher number of streams under strict latency conditions.

关键词： Streams MIMO communication Software Throughput Complexity theory Sorting Hardware acceleration Open radio access network multiple-input multiple-output sorted QR decomposition non-linear detection field programmable gate array

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On chip novel video streaming system for bi-network multicasting protocols

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INTEGRATION-THE VLSI JOURNAL 2009年第3期42卷 356-366页

作者： Elkeelany, O. Tennessee Technol Univ Dept Elect & Comp Engn Cookeville TN 38505 USA

In the past three decades, tremendous Ethernet-related research has been done, which has led to today's ubiquitous Ethernet technology. On the other hand, with the emergence of new network needs, a new protocol, the IEEE 1394 standard serial bus (or Firewire) was introduced. Firewire is suitable for high-quality audio/video applications which do not perform well in the best-effort-based Ethernet technology. However, since Firewire is a serial bus, it has harsh cable length limitations as compared to Ethernet capabilities. In this paper, we present a novel on-chip system that receives Firewire video and transmits it in multicast mode using Ethernet protocol. A major advantage of this novel system is to utilize the existing Ethernet infrastructure to extend the range of Firewire video streaming to reach remote nodes and make it even accessible to nodes with a single Ethernet interface. This will have tremendous impact on Firewire applications such as deploying Firewire cameras in big-scale security-sensitive buildings or industrial facilities with image-based remote quality control. This novel chip utilizes the concept of Ethernet multicasting transmission mode for video streaming. The proposed chip design converts the IEEE 1394 isochromous traffic to the Ethernet multicast frame format via two off-chip asynchronous write and read buffers. The goal of this research is to design an On Chip Novel Video Streaming System that avoids performance bottlenecks in the software protocol conversion of these two important network protocols. The author decided to study these two networks because of their broad use and cable power provisioning capabilities. The novel system design is implemented using a customized field programmable gate array (FPGA), which enables the integration of various system components on one chip. The designed prototype is studied using both network monitoring tools and analytical techniques, to verify its function and compare it with the existing approache

关键词： field programmable gate array Network ready devices Low-power design Hardware description language Synthesis Simulation

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A Low Area FPGA Implementation of Reversible gate Encryption with Heterogeneous Key Generation

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2021年第8期40卷 3836-3865页

作者： Saranya, K. Vijeyakumar, K. N. Dr Mahalingam Coll Engn & Technol Dept Elect & Elect Engn Coimbatore Tamil Nadu India Dr Mahalingam Coll Engn & Technol Dept Elect & Commun Engn Coimbatore Tamil Nadu India

The reversible computation is the process of designing the architecture with reversible logic gates (RLG) and applicable for optical computing, digital signal processing, nanotechnologies and low-power circuits. In this study, integer wavelet transform (IWT) compression technique is applied to the input image to compress the pixel value. The utilization of the IWT is used to improve the quality of the image in terms of peak signal-to-noise ratio (PSNR) and structural similarity index matrix (SSIM). In addition, different types of RLGs are used to perform the encryption and decryption of the images. A random number is generated using the Lorenz chaotic system (LCS) that contains three different stages and each stage is developed using arithmetic blocks. Here, an effective key value is generated from the input image values by connecting the LCS's output with the heterogeneous key generation (HKG) module. The inverse IWT (IIWT) technique is used to retrieve the original data during execution of decryption operation. Application specific integrated circuit and field-programmable gate array (FPGA) performances are calculated for reversible logic cryptographic design (RLCD) IWT-HKG architecture. The results showed that it has achieved better performance compared to conventional methods. Moreover, security analyses such as avalanche effect, side channel attack and session key agreement are performed for the RLCD-IWT-HKG method. The RLCD-IWT-HKG method has achieved 89 LUTs, 52 flip flops and 31 slices for the Virtex 6 FPGA device. After retrieving the decrypted images, values of PSNR and SSIM are evaluated as 39.90 dB and 0.6874, respectively.

关键词： Application specific integrated chip Avalanche effect field programmable gate array Integer wavelet transform Side channel attack

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MoniThor: A complete monitoring tool for machining data acquisition based on FPGA programming

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SOFTWAREX 2020年 11卷

作者： Urbikain, G. de Lacalle, L. N. Lopez Univ Basque Country Dept Mech Engn High Performance Mfg Grp Plaza Europa 1 Donostia San Sebastian 20018 Basque Country Spain Univ Basque Country Dept Mech Engn High Performance Mfg Grp Plaza Ingn Torres Quevedo 1 Bilbao 48013 Basque Country Spain

Today requirements by machine-tool users point towards knowing more about the machining processes. In a globalized and competitive market as manufacturing is, future engineers will be urged to develop transversal skills on diverse science domains such as Mechanics, Mechatronics or Electrics. Monitoring of machining processes allows determining possible errors and deviations from the desirable conditions (aged machine-tools, bad machining conditions, most energetically / cost-effective conditions) as well as saving historical data of the workpieces manufactured by the same machine. In order to strengthen students' skills, the Department of Mechanical Engineering of the University of the Basque Country (UPV/EHU) developed a monitoring tool using Labview (c) programming. The application, built from the combination of reconfigurable Input/Output (I/O) architecture and field programmable gate arrays (FPGA), was applied to practical classes in the machine shop to improve students' skills. (C) 2019 The Authors. Published by Elsevier B.V.

关键词： Monitoring tool Machining data field programmable gate array

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Interlaced photoacoustic and ultrasound imaging system with real-time coregistration for ovarian tissue characterization

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JOURNAL OF BIOMEDICAL OPTICS 2014年第7期19卷 76020-1-76020-8页

作者： Alqasemi, Umar Li, Hai Yuan, Guangqian Kumavor, Patrick Zanganeh, Saeid Zhu, Quing King Abdulaziz Univ Dept Elect & Comp Engn Jeddah 21589 Saudi Arabia Univ Connecticut Dept Biomed Engn Storrs CT 06269 USA Univ Connecticut Dept Elect Storrs CT 06269 USA Univ Connecticut Dept Comp Engn Storrs CT 06269 USA

Coregistered ultrasound (US) and photoacoustic imaging are emerging techniques for mapping the echogenic anatomical structure of tissue and its corresponding optical absorption. We report a 128-channel imaging system with real-time coregistration of the two modalities, which provides up to 15 coregistered frames per second limited by the laser pulse repetition rate. In addition, the system integrates a compact transvaginal imaging probe with a custom-designed fiber optic assembly for in vivo detection and characterization of human ovarian tissue. We present the coregistered US and photoacoustic imaging system structure, the optimal design of the PC interfacing software, and the reconfigurable field programmable gate array operation and optimization. Phantom experiments of system lateral resolution and axial sensitivity evaluation, examples of the real-time scanning of a tumor-bearing mouse, and ex vivo human ovaries studies are demonstrated. (C) 2014 Society of Photo-Optical Instrumentation Engineers (SPIE)

关键词： coregistered ultrasound and photoacoustic imaging ovarian cancer field programmable gate array peripheral component interconnect express interfacing reconfigurable computing

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