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IEEE International Conference on Consumer Electronics and Computer Engineering (ICCECE)

作者： Shan, Chengyi Chen, Lei Li, Xuewu Geng, Xiaoyuan Wang, Kedi Beijing Microelect Technol Inst Beijing Peoples R China

ISBN: (纸本)9781728183190

In order to meet the increasing clock requirements of FPGAs, Phase-locked loop has been widely used in FPGAs as clock management unit. This paper introduces a charge pump phase-locked loop with dual voltage-controlled oscillator applied on a 28nm FPGA platform. On the basis of the traditional charge pump phase-locked loop, this paper designs a configurable filter, a new structure of VCO with amplification and shaping circuit. The simulation results show that the structure can effectively improve the frequency locking speed of the VCO.

关键词： Phase Locked Loop field programmable gate array Voltage Controlled Oscillator

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A study on VLSI implementation of image enhancement techniques

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2022年第10期34卷

作者： Aklak, Annis Fathima Pugazhenthi, Murugesh Yadhav Alex, John Sahaya Rani Vellore Inst Technol Sch Elect Engn Chennai Tamil Nadu India BlueBird Electromech Contracting LLC Ajman U Arab Emirates Vellore Inst Technol Ctr Healthcare Adv Innovat & Res Chennai Tamil Nadu India

In real-time, the images captured are not always appreciable for visual perception. The quality of the image relies on the illumination condition. Contrast enhancement is required to improve the visual quality of the image. In this article, the image enhancement techniques that are adaptable for real-time images are studied. Further, an investigation is done on implementing the image processing algorithms in very large-scale integration (VLSI) hardware. As the image data are comparatively larger, the computational complexity and the memory requirement are more. From the study, the need for efficient computation of such image processing algorithms is realized. The efficient computation of image processing algorithms on hardware platforms, in particular on field programmable gate array (FPGA), is reviewed. As an experiment, the gamma-transformation technique used for image enhancement is realized. Initially, the prototype is modeled using MATLAB, and then it is implemented using an FPGA.

关键词： field programmable gate array floating point multiplier image enhancement

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Bayesian Source Localization using Stochastic Computation 53

Bayesian Source Localization using Stochastic Computation

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IEEE International Symposium on Circuits and Systems (IEEE ISCAS)

作者： Krishna, Adithya Thakur, Chetan Singh Indian Inst Sci Bengaluru India

ISBN: (纸本)9781728192017

Bayesian models are challenging to implement on hardware with the conventional design methodologies due to their high computational complexity. Conventional digital architectures are designed for deterministic computation and are not optimal for implementing probabilistic algorithms on hardware. In this work, we propose an alternative method to implement the probabilistic algorithms such as Bayesian models on hardware using a stochastic computation (SC) framework. This framework leverages on the probabilistic nature of the Bayesian models and facilitates the implementation of complex probabilistic models using simple logic gates. From an application standpoint, we propose a novel Bayesian source localization model (BSLM) that estimates a source's position in a noisy environment by solving the Bayesian recursive equation implemented on field programmable gate array (FPGA) with low resource utilization. The proposed SC design framework will pave the way to build complex probabilistic algorithms for real-time edge computing applications.

关键词： Bayesian Inference field programmable gate array Unmanned Ground Vehicle Hardware Architectures

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Modeling A Loop Back Test For Radar Phased array Digital Receiver Exciters Using Python

Modeling A Loop Back Test For Radar Phased Array Digital Rec...

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IEEE Radio and Wireless Symposium (RWS) / IEEE Space Hardware and Radio Conference (SHaRC)

作者： Mortensen, John Wickert, Mark Univ Colorado Dept Elect & Comp Engn Colorado Springs CO 80918 USA

ISBN: (纸本)9781665415835

Active Electronically Scanned arrays (AESAs) used in radar systems typically use digital receiver exciters (DREX) units. Functional testing of DREX units can be challenging due to their complexity. This is true for lab testing but is especially true for field testing. This work describes a method for testing that uses a loop back approach. Three loop back tests are described which essentially involves one or more signals from transmit channels routed to one or more receive channels. An example digital receiver exciter is described along with the data converters and field programmable gate array. The loop back test method is then described, and a Python program is developed that simulates the approach. Initial testing of the receive section is then presented.

关键词： phased arrays digital receiver exciter (DREX) field programmable gate array

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Accelerating the Activation Function Selection for Hybrid Deep Neural Networks - FPGA Implementation

Accelerating the Activation Function Selection for Hybrid De...

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IEEE Region 10 Symposium (TENSYMP) - Good Technologies for Creating Future

作者： Waseem, Shaik Mohammed Suraj, Alavala Venkata Roy, Subir Kumar IIIT Bangalore VLSI Syst Res Grp Bangalore Karnataka India

ISBN: (纸本)9781665400268

Much of the work in literature about hardware implementations of deep neural networks illustrates the multiplication of input signal with weights and summing up the data. Work in this paper is focused on the hardware implementation of non-linear functions (activation functions), along with hardware rendition of the automatic selection of activation function for each layer in the neural network in order to increase the accuracy. We have used field programmable gate array (FPGA) based hardware development platform to add in the advantages of the power efficiency and edge deployment. Our novel hardware design modules to this extent are capable of accelerating the entire process of activation function selection and activation function output generation along with its derivative. The tabulated results in this paper, for power and resource utilization generated through Xilinx (R) Vivado platform by targeting our design modules towards Avnet (R) Ultra96 v2 Evaluation board prove the sheer hardware novelty in terms of less hardware foot print and energy efficiency in comparison to the GPU (Graphics Processing Unit) and CPU (Central Processing Unit) based executions along with FPGA based implementations of few activation functions reported in literature.

关键词： Activation Function field programmable gate array Hybrid Deep neural networks Hardware Accelerator

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FPGA Implementation of Memory-Based Digital Predistorters with High-Level Synthesis

FPGA Implementation of Memory-Based Digital Predistorters wi...

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IEEE Topical Conference on RF/Microwave Power Amplifiers for Radio and Wireless Applications (PAWR)

作者： Li, Wantao Guillena, Estefania Montoro, Gabriel Gilabert, Pere L. UPC Barcelona Tech Dept Sig Theory Comm Castelldefels Spain

ISBN: (纸本)9781665404099

This paper presents a scalable look-up table (LUT) architecture for implementing digital predistortion (DPD) linearizers in a field programmable gate array (FPGA) by using the high-level synthesis (HLS) software. This architecture can be used in most memory-based DPD behavioral models whose basis functions can be expressed as a combination of basic predistortion cells (BPCs). The advantages of the proposed LUT-based architecture are evidenced in terms of resources usage, throughput. and power consumption of the corresponding programmable logic (PL). The DPD linearization performance was tested considering different LUT sizes on a load-modulated balanced amplifier (LMBA), using two LTE 20 MHz signals over a total 60 MHz instantaneous bandwidth.

关键词： field programmable gate array load-modulated balanced amplifier power efficiency digital predistortion

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Neural Network Based Glitch Physically Unclonable Function 12

Neural Network Based Glitch Physically Unclonable Function

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12th IEEE Annual Ubiquitous Computing, Electronics and Mobile Communication Conference (UEMCON)

作者： Nozaki, Yusuke Yoshikawa, Masaya Meijo Univ Dept Informat Engn Nagoya Aichi Japan

ISBN: (纸本)9781665406901

The security issues of artificial intelligence (AI) system are attracting attention. The neural network physically unclonable function (NN PUF) have been proposed to improve the security of AI devices. The NN PUF combines two functions: AI inference and device authentication. In device authentication, a unique ID is generated for each device by using the manufacturing variation of large-scale integration (LSI). The NN PUF uses the delay difference of NN computation time for ID generation. However, the conventional NN PUF is known to have low uniqueness in field programmable gate array (FPGA) implementation. Therefore, the present study proposes a new NN PUF that improves uniqueness. Evaluation experiments with FPGAs showed that the proposed NN PUF significantly improved uniqueness compared to the conventional NN PUF.

关键词： physically unclonable function neural network glitch physically unclonable function hardware security field programmable gate array

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Synthesis of Temporal Machines with Operational Transformation of State Codes 31

Synthesis of Temporal Machines with Operational Transformati...

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31st International Scientific Symposium on Metrology and Metrology Assurance (MMA)

作者： Miroshnyk, Marina Zaichenko, Olga Miroshnyk, Anatolii Zaichenko, Nataliia Ukrainian State Univ Railway Transport Spesialised Comp Syst Kharkiv Ukraine Kharkiv Natl Univ Radioelelect Design & Operat Elect Devices Kharkiv Ukraine Natl Tech Univ Kharkiv Polytech Inst Spesialised Comp Syst Kharkiv Ukraine Kharkiv Natl Univ Radioelelect Microelect Elect Devices & Appliances Kharkiv Ukraine

ISBN: (纸本)9781665445375

The actual scientific problem of development methods aimed at reducing of hardware expenses in the logical circuit of the finite state machine, is solved by adaptation of the finite state machine (FSM) circuit to the characteristics of the implemented control algorithm. The object of the research encompasses process of optimization of finite state machines circuits. The subject of the research is the models and methods of synthesis of finite state machines, aimed at reducing the hardware expenses in the circuit of the machine. The research is based on a systematic analysis of the results of modern theoretical and applied developments made by domestic and foreign scientists in the digital control units sphere. The theoretical novelty is distinguished by the fact that a method is proposed for choosing constants in operations for operational state transitions on the base of the determinant of the matrix. The practical novelty lies in the implementation in Quartus by the behavioral method, in contrast to the classical method.

关键词： operational transformation of state codes finite state machines FSM hardware description language VHDL temporal automata field programmable gate array FPGA graph scheme of algorithm GSA

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Developments in Time-to-Digital Converters during 2020 7

Developments in Time-to-Digital Converters during 2020

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7th International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP)

作者： Tancock, Scott Rarity, John Dahnoun, Naim Univ Bristol Sch Comp Sci Elect Engn & Engn Math Bristol Avon England Univ Bristol Ctr Quantum Photon Bristol Avon England

ISBN: (纸本)9781665436977

Time-to-Digital Converters (TDCs) are important devices in many systems, such as Time-of-Flight, frequency locking, nuclear experiments and metrology, and quantum versions of all these. Therefore, research into TDCs is important to bring these technologies to wider audiences. There was plenty of TDC innovation in 2020 despite the global pandemic, and in this review paper we summarise the research related to TDC architectures. We show four review and analysis papers, eight papers on application-specific integrated circuits, five papers on field-programmable gate arrays, one paper on discrete TDCs, and four papers on novel applications of the TDC core. This trend of excellent research looks set to continue into 2021, with 21 papers already mentioning TDC despite major conferences such as NoMeTDC and I2MTC not having occurred as of writing.

关键词： Time to Digital Converter Review field programmable gate array Application Specific Integrated Circuit Time Measurement

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Temperature Characterisation of the DSP Delay Line 7

Temperature Characterisation of the DSP Delay Line

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7th International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP)

作者： Tancock, Scott Rarity, John Dahnoun, Naim Univ Bristol Sch Comp Sci Elect Engn & Engn Math Bristol Avon England Univ Bristol Ctr Quantum Photon Bristol Avon England

ISBN: (纸本)9781665436977

Time-to-Digital Converters (TDCs) are important measurement devices for fields such as quantum computing and range-finding. To implement these devices, FPGAs are an attractive option due to their low cost relative to ASICs, reconfigurability, updatability and off-the-shelf availability. However, these devices are often sensitive to changes in temperature due to temperature-dependent changes in electrical characteristics (Process-Voltage-Temperature, PVT variations), and thus must be characterised to avoid erroneous measurements. In our past papers, we demonstrated the implementation of Tapped Delay Line (TDL) TDCs using the DSP blocks available on Xilinx FPGAs. In this paper, we characterise the variability of the TDC core with respect to temperature in terms of Single-Shot Precision (SSP), resolution, Integral Non-Linearity (INL) and Differential Non-Linearity (DNL). Over a temperature range of 68.3 degrees C, we demonstrate an 8.23 ps difference in SSP, a 3.89 ps difference in cubic-mean resolution, a 247 ps difference in INL and a 19.4 ps difference in DNL.

关键词： field programmable gate array Time to Digital Converter DSP Xilinx Temperature Characterisation Time Measurement

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