检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

727 篇 期刊文献
580 篇 会议
30 篇 学位论文
1 册 图书
1 篇 科技报告

馆藏范围

1,339 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,231 篇 工学
- 749 篇 电气工程
- 543 篇 计算机科学与技术...
- 185 篇 信息与通信工程
- 129 篇 控制科学与工程
- 122 篇 电子科学与技术（可...
- 102 篇 仪器科学与技术
- 82 篇 软件工程
- 61 篇 机械工程
- 48 篇 航空宇航科学与技...
- 44 篇 材料科学与工程（可...
- 44 篇 核科学与技术
- 40 篇 石油与天然气工程
- 28 篇 动力工程及工程热...
- 18 篇 力学（可授工学、理...
- 18 篇 生物医学工程（可授...
- 13 篇 交通运输工程
- 11 篇 网络空间安全
- 10 篇 光学工程
- 10 篇 测绘科学与技术
- 8 篇 生物工程
204 篇 理学
- 138 篇 物理学
- 27 篇 数学
- 26 篇 化学
- 25 篇 生物学
82 篇 管理学
- 71 篇 管理科学与工程(可...
- 8 篇 公共管理
- 8 篇 图书情报与档案管...
69 篇 医学
- 43 篇 临床医学
- 12 篇 基础医学(可授医学...
- 7 篇 特种医学
5 篇 法学
5 篇 农学
4 篇 军事学
2 篇 经济学
2 篇 教育学
2 篇 文学
1 篇 艺术学

主题

1,339 篇 field programmab...
195 篇 field programmab...
108 篇 fpga
35 篇 digital signal p...
34 篇 hardware
23 篇 cryptography
21 篇 system-on-chip
19 篇 hardware descrip...
19 篇 convolutional ne...
18 篇 image processing
17 篇 logic circuits
17 篇 digital signal p...
17 篇 vhdl
15 篇 computer archite...
15 篇 real-time system...
14 篇 signal processin...
14 篇 graphics process...
14 篇 reconfigurable a...
14 篇 power consumptio...
14 篇 machine learning

机构

6 篇 george mason uni...
5 篇 univ sci & techn...
5 篇 kyushu inst tech...
4 篇 beihang univ sch...
4 篇 indian inst tech...
4 篇 weifang univ inf...
4 篇 huazhong univ sc...
4 篇 naval postgradua...
4 篇 auburn univ dept...
4 篇 shanghai univ sc...
3 篇 lodz univ techno...
3 篇 univ london impe...
3 篇 shanghai jiao to...
3 篇 harbin univ sci ...
3 篇 kyushu inst tech...
3 篇 univ burdwan uni...
3 篇 indian inst tech...
3 篇 univ washington ...
3 篇 tennessee techno...
3 篇 univ sci & techn...

作者

8 篇 diehl william
8 篇 gaj kris
7 篇 tamukoh hakaru
7 篇 wang peng
6 篇 monmasson e.
6 篇 makowski d.
6 篇 de castro angel
5 篇 jablonski g.
5 篇 wang yonggang
5 篇 garrido javier
5 篇 mielczarek a.
5 篇 napieralski a.
5 篇 perek p.
4 篇 sanchez alberto
4 篇 torikai hiroyuki
4 篇 tsang p. w. m.
4 篇 watanabe minoru
4 篇 luk wayne
4 篇 xu tongge
4 篇 wang fan

语言

1,277 篇 英文
41 篇 其他
19 篇 中文
2 篇 土耳其文

检索条件"主题词=Field Programmable Gate array"

共 1339 条记录，以下是311-320 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

FPGA Implementation of Memory-Based Digital Predistorters with High-Level Synthesis

FPGA Implementation of Memory-Based Digital Predistorters wi...

引用

IEEE Topical Conference on RF/Microwave Power Amplifiers for Radio and Wireless Applications (PAWR)

作者： Li, Wantao Guillena, Estefania Montoro, Gabriel Gilabert, Pere L. UPC Barcelona Tech Dept Sig Theory Comm Castelldefels Spain

ISBN: (纸本)9781665404099

This paper presents a scalable look-up table (LUT) architecture for implementing digital predistortion (DPD) linearizers in a field programmable gate array (FPGA) by using the high-level synthesis (HLS) software. This architecture can be used in most memory-based DPD behavioral models whose basis functions can be expressed as a combination of basic predistortion cells (BPCs). The advantages of the proposed LUT-based architecture are evidenced in terms of resources usage, throughput. and power consumption of the corresponding programmable logic (PL). The DPD linearization performance was tested considering different LUT sizes on a load-modulated balanced amplifier (LMBA), using two LTE 20 MHz signals over a total 60 MHz instantaneous bandwidth.

关键词： field programmable gate array load-modulated balanced amplifier power efficiency digital predistortion

来源：评论

学校读者我要写书评

暂无评论

Neural Network Based Glitch Physically Unclonable Function 12

Neural Network Based Glitch Physically Unclonable Function

引用

12th IEEE Annual Ubiquitous Computing, Electronics and Mobile Communication Conference (UEMCON)

作者： Nozaki, Yusuke Yoshikawa, Masaya Meijo Univ Dept Informat Engn Nagoya Aichi Japan

ISBN: (纸本)9781665406901

The security issues of artificial intelligence (AI) system are attracting attention. The neural network physically unclonable function (NN PUF) have been proposed to improve the security of AI devices. The NN PUF combines two functions: AI inference and device authentication. In device authentication, a unique ID is generated for each device by using the manufacturing variation of large-scale integration (LSI). The NN PUF uses the delay difference of NN computation time for ID generation. However, the conventional NN PUF is known to have low uniqueness in field programmable gate array (FPGA) implementation. Therefore, the present study proposes a new NN PUF that improves uniqueness. Evaluation experiments with FPGAs showed that the proposed NN PUF significantly improved uniqueness compared to the conventional NN PUF.

关键词： physically unclonable function neural network glitch physically unclonable function hardware security field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Synthesis of Temporal Machines with Operational Transformation of State Codes 31

Synthesis of Temporal Machines with Operational Transformati...

引用

31st International Scientific Symposium on Metrology and Metrology Assurance (MMA)

作者： Miroshnyk, Marina Zaichenko, Olga Miroshnyk, Anatolii Zaichenko, Nataliia Ukrainian State Univ Railway Transport Spesialised Comp Syst Kharkiv Ukraine Kharkiv Natl Univ Radioelelect Design & Operat Elect Devices Kharkiv Ukraine Natl Tech Univ Kharkiv Polytech Inst Spesialised Comp Syst Kharkiv Ukraine Kharkiv Natl Univ Radioelelect Microelect Elect Devices & Appliances Kharkiv Ukraine

ISBN: (纸本)9781665445375

The actual scientific problem of development methods aimed at reducing of hardware expenses in the logical circuit of the finite state machine, is solved by adaptation of the finite state machine (FSM) circuit to the characteristics of the implemented control algorithm. The object of the research encompasses process of optimization of finite state machines circuits. The subject of the research is the models and methods of synthesis of finite state machines, aimed at reducing the hardware expenses in the circuit of the machine. The research is based on a systematic analysis of the results of modern theoretical and applied developments made by domestic and foreign scientists in the digital control units sphere. The theoretical novelty is distinguished by the fact that a method is proposed for choosing constants in operations for operational state transitions on the base of the determinant of the matrix. The practical novelty lies in the implementation in Quartus by the behavioral method, in contrast to the classical method.

关键词： operational transformation of state codes finite state machines FSM hardware description language VHDL temporal automata field programmable gate array FPGA graph scheme of algorithm GSA

来源：评论

学校读者我要写书评

暂无评论

Temperature Characterisation of the DSP Delay Line 7

Temperature Characterisation of the DSP Delay Line

引用

7th International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP)

作者： Tancock, Scott Rarity, John Dahnoun, Naim Univ Bristol Sch Comp Sci Elect Engn & Engn Math Bristol Avon England Univ Bristol Ctr Quantum Photon Bristol Avon England

ISBN: (纸本)9781665436977

Time-to-Digital Converters (TDCs) are important measurement devices for fields such as quantum computing and range-finding. To implement these devices, FPGAs are an attractive option due to their low cost relative to ASICs, reconfigurability, updatability and off-the-shelf availability. However, these devices are often sensitive to changes in temperature due to temperature-dependent changes in electrical characteristics (Process-Voltage-Temperature, PVT variations), and thus must be characterised to avoid erroneous measurements. In our past papers, we demonstrated the implementation of Tapped Delay Line (TDL) TDCs using the DSP blocks available on Xilinx FPGAs. In this paper, we characterise the variability of the TDC core with respect to temperature in terms of Single-Shot Precision (SSP), resolution, Integral Non-Linearity (INL) and Differential Non-Linearity (DNL). Over a temperature range of 68.3 degrees C, we demonstrate an 8.23 ps difference in SSP, a 3.89 ps difference in cubic-mean resolution, a 247 ps difference in INL and a 19.4 ps difference in DNL.

关键词： field programmable gate array Time to Digital Converter DSP Xilinx Temperature Characterisation Time Measurement

来源：评论

学校读者我要写书评

暂无评论

Developments in Time-to-Digital Converters during 2020 7

Developments in Time-to-Digital Converters during 2020

引用

7th International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP)

作者： Tancock, Scott Rarity, John Dahnoun, Naim Univ Bristol Sch Comp Sci Elect Engn & Engn Math Bristol Avon England Univ Bristol Ctr Quantum Photon Bristol Avon England

ISBN: (纸本)9781665436977

Time-to-Digital Converters (TDCs) are important devices in many systems, such as Time-of-Flight, frequency locking, nuclear experiments and metrology, and quantum versions of all these. Therefore, research into TDCs is important to bring these technologies to wider audiences. There was plenty of TDC innovation in 2020 despite the global pandemic, and in this review paper we summarise the research related to TDC architectures. We show four review and analysis papers, eight papers on application-specific integrated circuits, five papers on field-programmable gate arrays, one paper on discrete TDCs, and four papers on novel applications of the TDC core. This trend of excellent research looks set to continue into 2021, with 21 papers already mentioning TDC despite major conferences such as NoMeTDC and I2MTC not having occurred as of writing.

关键词： Time to Digital Converter Review field programmable gate array Application Specific Integrated Circuit Time Measurement

来源：评论

学校读者我要写书评

暂无评论

A Multimode FPGA-based Modem with Embedded Σ-Δ Analog-to-Digital Converter for Software Defined Radio 20

A Multimode FPGA-based Modem with Embedded Σ-Δ Analog-to-D...

引用

12th Annual Wireless Telecommunications Symposium (WTS)

作者： Duarte-Junior, J. G. Brito-Filho, E. A. Univ Fed Rio Grande do Norte Natal RN Brazil Fed Univ Semiarid Reg Mossoro Brazil

ISBN: (纸本)9781728184807

field programmable gate arrays (FPGAs) have been widely used in applications involving hard signal processing with reconfiguration capabilities. One promising application that requires those capabilities is Software Defined Radio (SDR). In this work a novel design of SDR modem based on FPGA is proposed. Using an experimental setup with an embedded sigma-delta A/D converter and a multimode (ASK, FSK and PSK) modem as proof of concept and with most of the tasks running in FPGA. The modem was tested and proved to be efficient using just about 1 % of available logic blocks of the adopted FPGA with a maximum operating frequency as high as 148 MHz for low cost devices, being possible the implementation in several models of FPGAs available in the market.

关键词： Software Defined Radio field programmable gate array Analog-to-Digital Converters Sigma-Delta Modem Hardware Description Language

来源：评论

学校读者我要写书评

暂无评论

Lossless Compression of Bitstream Configuration Files: Towards FPGA Cloud 19

Lossless Compression of Bitstream Configuration Files: Towar...

引用

19th IEEE International Symposium on Parallel and Distributed Processing with Applications (IEEE ISPA)

作者： Wang, Jinyu Kang, Yifei Feng, Yaqi Li, Yiwen Wu, Weiguo Xing, Guoliang Xi An Jiao Tong Univ Sch Comp Sci & Technol Xian Peoples R China Chinese Univ Hong Kong Dept Informat Engn Hong Kong Peoples R China

ISBN: (纸本)9781665435741

With the development of integrated circuit technology, the scale of field programmable gate array (FPGA) devices and the quantity of on-chip resources have been increased dramatically, as well as the size of configuration files, rendering the configuration process time-consuming. Especially, in the cloud-based multiple FPGAs co-designs, the transmission of large scale bitstream configuration files in public networks may suffer unpredictable delay, which causes circuits with high real-time requirements failed to be timely executed. To address this challenge, we divide a configuration file into three portions which have different data structures, and different compression methods are proposed to fit the data structure of each part to obtain a lower compression rate. For the portion which describes the FPGA on-chip resources, an LSTM and ID-CNN based arithmetic coding compression method is introduced. In this way, the compression problem is converted to an estimation of a conditional probability distribution problem. Finally, to improve the prediction efficiency of the neural network, a cache based neural network inference acceleration method is proposed. Our approach is validated on the standard benchmark data sets and the average compression rate is 28.89%. Compared with seven different compression methods, our approach improves the compression rate by up to 39.45%.

关键词： bitstream configuration file field programmable gate array arithmetic coding neural network inference acceleration

来源：评论

学校读者我要写书评

暂无评论

Resource and Energy Efficient Implementation of ECG Classifier using Binarized CNN for Edge AI Devices 53

Resource and Energy Efficient Implementation of ECG Classifi...

引用

IEEE International Symposium on Circuits and Systems (IEEE ISCAS)

作者： Wong, David Liang Tai Li, Yongfu John, Deepu Ho, Weng Khuen Heng, Chun Huat Natl Univ Singapore Elect & Comp Engn Singapore Singapore Shanghai Jiao Tong Univ Dept Micronano Elect Shanghai Peoples R China Shanghai Jiao Tong Univ MoE Key Lab Artificial Intelligence Shanghai Peoples R China Univ Coll Dublin Sch Elect & Elect Engn Dublin Ireland

ISBN: (纸本)9781728192017

Wearable Artificial Intelligence-of-Things (AIoT) devices demand smart gadgets that are both resource and energy-efficient. In this paper, we explore efficient implementation of binary convolutional neural network employing function merging and block reuse techniques. The hardware implemented in field programmable gate array (FPGA) platform can classify ventricular beat in electrocardiogram achieving accuracy of 97.5%, sensitivity of 85.7%, specificity of 99.0%, precision of 92.3%, and F1-score of 88.9% while consuming only 10.5-mu W of dynamic power dissipation.

关键词： Artificial Intelligence-of-Things low-power design wearable field programmable gate array ECG co-design convolutional neural network inference fusion state machine

来源：评论

学校读者我要写书评

暂无评论

Real-time Performance Evaluation of Single Phase 7 Level Z-Source Boost Inverter 7

Real-time Performance Evaluation of Single Phase 7 Level Z-S...

引用

7th International Conference on Electrical Energy Systems (ICEES)

作者： Prasad, Hanuman Bhadane, Kishor V. Kumar, Parveen Model Inst Engn & Technol Dept Elect Engn Jammu India Amrutvahini Coll Engn Dept Elect Engn Sangamner Maharashtra India

ISBN: (纸本)9781728176123

Multilevel inverter has been familiarized as a popular topology for DC-AC power conversion. This paper illustrates the real-time performance evolution of seven level z-source diode clamp multilevel inverter. The field programmable gate array (FPGA) integrated real time simulators consists of multiprocessor and computer clusters are the main hardware platforms for real-time simulations. The real time (RT) lab software enables the parallel simulation of an electrical circuit on clusters of personal computer running at sampling time 10 mu s. The integration of multilevel inverter and z-source energy conversion are used for DC-AC converter for high power applications with low total harmonics distortion. An impedance network has two passive elements such as two inductors and two capacitors connected between DC power source and multilevel inverter circuit. It provides a unique feature such as the boost the inverter output voltage and reduces the harmonic content in the output voltage as compared to the classic multilevel inverter. The real time results are verified the proposed system with a specified time step 10 mu s andfrequency is 10 KHz.

关键词： Real-time digital simulators field programmable gate array Software in the loop multilevel inverter hardware in the loop etc

来源：评论

学校读者我要写书评

暂无评论

FPGA Implementation of Interleaved Modular Multiplier with Improved Area-time Efficiency 11

FPGA Implementation of Interleaved Modular Multiplier with I...

引用

11th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems - Technology and Applications (IDAACS)

作者： Coliban, Radu-Mihai Transilvania Univ Dept Elect & Comp Bd Eroilor 29 Brasov 500036 Romania

ISBN: (纸本)9781665426053

Modular multiplication is the fundamental operation in Elliptic Curve Cryptography (ECC) and a multitude of hardware implementations have been developed so far. In this paper, a series of modifications to a high performance radix-2 interleaved modular multiplication architecture are proposed. The design was implemented on a Virtex-7 FPGA for five prime fields recommended for ECC by the National Institute of Standards and Technology (NIST), showing a significant improvement in area-time efficiency in comparison to the original architecture.

关键词： modular multiplication interleaved multiplication field programmable gate array elliptic curve cryptography

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共134页 << < 28 29 30 31 32 33 34 35 36 37 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：