Digital Pulse Processing offers multiple advantages over traditional analogue processing chains. As a disadvantage, produce gigabytes of data every second. Storing and processing such data rates in real-time still rem...
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Digital Pulse Processing offers multiple advantages over traditional analogue processing chains. As a disadvantage, produce gigabytes of data every second. Storing and processing such data rates in real-time still remains a challenge. Analogue solutions are not riddled with this issue, however, they offer limited flexibility and modifiability. This work highlights the advantages of Digital Pulse Processing over Analogue Pulse Processing and describes a successful implementation of a digital pulse detection and acquisition system based on field programmable gate arrays. The system is tasked with processing pulses generated by a Photo Multiplier Tube nuclear detector. Incoming signals are sampled at a 1 GS/s rate, so to enable full acquisition resolution, throughput is reduced with digital detection filters and leading-edge triggering or with a derivative zero-crossing detector. Three different fast timing filters are adapted to high-speed real-time acquisition and compared in a simulated scenario. A trapezoidal filter is implemented in firmware alongside the detection channel for pulse height analysis. Thanks to the use of reprogrammable devices, the system remains versatile and can be remotely adapted to different needs with no additional hardware costs.
Modern deep learning schemes have shown human-level performance in the area of medical science. However, the implementation of deep learning algorithms on dedicated hardware remains a challenging task because modern a...
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Modern deep learning schemes have shown human-level performance in the area of medical science. However, the implementation of deep learning algorithms on dedicated hardware remains a challenging task because modern algorithms and neuronal activation functions are generally not hardware-friendly and require a lot of resources. Recently, researchers have come up with some hardware-friendly activation functions that can yield high throughput and high accuracy at the same time. In this context, we propose a hardware-based neural network that can predict the presence of cancer in humans with 98.23% accuracy. This is done by making use of cost-efficient, highly accurate activation functions, Sqish and LogSQNL. Due to its inherently parallel components, the system can classify a given sample in just one clock cycle, i.e., 15.75 nanoseconds. Though this system is dedicated to cancer diagnosis, it can predict the presence of many other diseases such as those of the heart. This is because the system is reconfigurable and can be programmed to classify any sample into one of two classes. The proposed hardware system requires about 983 slice registers, 2,655 slice lookup tables, and only 1.1 kilobits of on-chip memory. The system can predict about 63.5 million cancer samples in a second and can perform about 20 giga-operations per second. The proposed system is about 5-16 times cheaper and at least four times speedier than other dedicated hardware systems using neural networks for classification tasks.
Clouds play an important role in weather and climate-related investigations. However, they often influence the quality of images and waste resources of storage and bandwidth in remote sensing. So, it is critical to de...
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ISBN:
(纸本)9781510650060;9781510650053
Clouds play an important role in weather and climate-related investigations. However, they often influence the quality of images and waste resources of storage and bandwidth in remote sensing. So, it is critical to detect clouds for less cost of payload. In this paper, the design of a real-time cloud detection camera for small satellite platforms is proposed based on field programmable gate array (FPGA). Two MicroBlaze Soft Cores are embedded in the FPGA to accomplish the task without other chips assist. By using this way, the system is highly programmable and integrated, the weight of which also becomes lighter. We implemented the system on a Xilinx Virtex-4 FPGA. The test results show that the signal-to-noise ratio (SNR) is 128.1 at 80% of the saturated exposure. We select Arabian Peninsula-Pakistan-West India area to evaluate the cloud judgment accuracy. Compare with moderate resolution imaging spectroradiometer (MODIS) cloud mask products, the false alarm rate (FAR) is less than 3%. The application of the proposed approach in a simulation and engineering system indicates its effectiveness and practicability.
This paper presents a new approach for the modeling and real-time simulation of an embedded hybrid power source comprised of a fuel cell (FC) and a battery. The proposed modeling is based on a state-space-like represe...
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ISBN:
(纸本)9781665448642
This paper presents a new approach for the modeling and real-time simulation of an embedded hybrid power source comprised of a fuel cell (FC) and a battery. The proposed modeling is based on a state-space-like representation of the system equations obtained from the modified-augmented nodal analysis. Systematic formulation of system equations is presented and the solution to the non-linear equations are discussed. The proposed model was implemented on an entry level field programmable gate array (FPGA), and demonstrates sub-microsecond simulation time-step capability. The real-time solution is obtained by precomputing the system equations for all switch state combinations, and using the backward Euler integration scheme for solving differential equations. A fixed point number representation is utilized for speed and reduced configurable resource utilization. Our results show a high fidelity of the proposed model over a wide range of simulation time-steps and switching frequencies.
The availability of OpenCL for FPGAs along with High-Level Synthesis tools have made them an attractive platform for implementing compute-intensive massively parallel applications. FPGAs with their customizable data-p...
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The availability of OpenCL for FPGAs along with High-Level Synthesis tools have made them an attractive platform for implementing compute-intensive massively parallel applications. FPGAs with their customizable data-path, deep pipelining abilities and enhanced power efficiency features offer the most viable solutions for programming and integrating them with heterogeneous platforms. However, OpenCL for FPGAs raise many design challenges which require an in-depth understanding to better utilize their enormous capabilities. Inefficient routing of data, high number of memory stalls exposed to execution and under-utilization of FPGA resources are significant execution bottlenecks that overshadow the advantages of data-path customization. Furthermore, leveraging OpenCL parallelism abilities and throughput oriented principles is paramount to the success of FPGAs in the high performance computing environment. In this research, we identify, analyze and categorize the architectural differences between the OpenCL parallel programming model and FPGA execution semantic. We propose a generic taxonomy for classifying FPGA parallelism potential to the fullest. To benefit massive thread-level parallelism, we introduce a unique LLVM based automation tool to decouple memory access from computation, thereby hiding memory stalls from the execution path. We further present a novel parallelism granularity that separates kernels to split them into data-path and memory-path (memory read/write) that work concurrently to overlap the computation of current threads with the memory access of future threads. We validate these principles on the Xilinx based AWS Cloud FPGA platform. We then conduct a thorough investigation into the scalability of OpenCL coarse-grain parallelism, as well as an examination of Compute Unit(CU) replication, Double Data Rate (DDR) and Burst Transfer (BT) optimizations on Cloud FPGAs. To address the issue of programming challenges, we present generic template(s) and a f
This paper introduces our autonomous driving system equipped with recognition processing units from a camera image for hazard object / human-doll detection and drive lane detection. In particular, this paper focuses o...
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ISBN:
(纸本)9781665420105
This paper introduces our autonomous driving system equipped with recognition processing units from a camera image for hazard object / human-doll detection and drive lane detection. In particular, this paper focuses on a dataset generation method for neural networks and a generation tool "FPGA Oriented Easy Synthesizer Tool (FOrEST)" for ROS2-FPGA nodes. The results show that mAP of a neural network trained by the generated dataset is 94 %, and a overhead of ROS2-FPGA communication by the FOrEST is 2-3 ms.
The control performance of converter directly affects the drive efficiency of electric vehicle (EV). This paper studies on the model predictive control (MPC) based controller design of battery integrated modular multi...
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ISBN:
(纸本)9789881563804
The control performance of converter directly affects the drive efficiency of electric vehicle (EV). This paper studies on the model predictive control (MPC) based controller design of battery integrated modular multilevel converter (B-MMC). Aiming at the goal of three-phase current tracking and battery balancing control of B-MMC, three-layer controllers are designed. The first controller is the finite control set model predictive control (FCS-MPC), which realizes the motor drive by tracking the phase current. The second controller is the circulation controller for the active balance control of battery. It is composed of multiple proportional controllers to realize the battery balance between the bridge arms. The third controller is the battery sorting algorithm to achieve the passive balance control of the battery in the same bridge arm. At the same time, field programmable gate array (FPGA) is used to accelerate the controller to meet the real-time requirements of B-MMC. Finally, the simulation results of the B-MMC control system validates the effectiveness of the control algorithm.
To realize Society 5.0, edge AI techniques have attracted attention. On the other hand, security issues of edge AI have been reported. In addition, in the field of hardware security, the threat of hardware Trojan (HT)...
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To realize Society 5.0, edge AI techniques have attracted attention. On the other hand, security issues of edge AI have been reported. In addition, in the field of hardware security, the threat of hardware Trojan (HT) is emphasized. To defend the AI device from malicious attacks, it is important to check the vulnerability against various attacks. Therefore, this study proposes a new HT for AI inference devices. The proposed HT falsifies the inference result with respect to an arbitrary trigger input. The proposed HT concentrates on the Lookup Table (LUT) structure, and can be achieved by rewriting the LUT table information. As a result, the proposed HT does not need additional trojan trigger and payload circuits, that is, it can be implemented without the circuit overhead. Experiments by field programable gatearray show the validity of the proposed HT.
Despite the merits of Renewable Energy Sources (RES) as clean and reliable alternatives for electrical energy generation, there are some problems related to their highly cost and low efficient operation with non - lin...
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Despite the merits of Renewable Energy Sources (RES) as clean and reliable alternatives for electrical energy generation, there are some problems related to their highly cost and low efficient operation with non - linear loads. As one of the most vital methodologies to improve the operational quality of RES within the electrical network, the integration of RES in a one hybrid system can effectively contribute to overcome the obstacles of the randomness and inability to accurately predict the daily generation of each individual RES. In this research, Fuel Cells (FCs) are practically integrated with two renewable sources (wave energy and solar energy) utilizing the field programmable gate array (FPGA) as a new innovative digital controller technique. FPGAs are chosen in this study for its ultra - fast processing speed that is expected to reach to almost 100 MHz and its higher response than other microcontrollers for RES integration. Although the merits of FPGAs like fast response, having no processors and behaving in a parallel manner, there are some obstacles in controlling the energy level of RES during the integration process. To overcome the problems of FPGAs, Moth Flame Optimization (MFO) algorithm is utilized with Artificial Neural Network (ANN) to enhance its operational accuracy for providing an effective and precise forecasting control scenario for the proposed hybrid system. In this paper, FCs are provided as an effective Battery Energy Storage Systems (ESS) to overcome the sudden operational outage of any RES to ensure the reliability of the proposed hybrid system within the electrical network. This research provides the hybrid combination between the Buck - Boost converter and FPGA as a vital approach to adjust the voltage level of the proposed RES integration within a reasonable value. In this research, all the obtained results are assessed based on the available previous simulation and empirical data to confirm the validity and high response of the FPGA
With the enhancement of technology, data security has become incredibly significant. Nowadays, images and vital information are used in real-time, and high throughput architecture is required for internet of things an...
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With the enhancement of technology, data security has become incredibly significant. Nowadays, images and vital information are used in real-time, and high throughput architecture is required for internet of things and real-time applications. We mainly focus on the high throughput architecture of PRINT cipher. PRINT cipher is a lightweight block cipher with a block size of 48-bit and 96-bit. Loop-unrolled, 48-bit pipelined, and 96-bit pipelined architectures are designed and implemented on different field programmable gate array and application-specific integrated circuit platforms. The maximum operating frequency obtained for 48-bit pipelined is 259.67 MHz on Virtex-4 and 310.67 MHz for 96-bit pipelined on Virtex-5. Finally, with the help of a controller, 48-bit high throughput pipelined architecture was utilized for image encryption of both grayscale and color images. The security analysis of encrypted images for color and grayscale images using PRINT cipher shows better performance and more robust protection against statistical, entropy, and differential attacks. (c) 2022 SPIE and IS&T
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