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A fast neural-network algorithm for VLSI cell placement

NEURAL NETWORKS 1998年第9期11卷 1671-1684页

作者： Aykanat, C Bultan, T Haritaoglu, I Bilkent Univ Dept Comp Engn TR-06533 Ankara Turkey Univ Maryland Dept Comp Sci College Pk MD 20742 USA

Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gate array, and field programmable gate array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) were successful in solving this problem, they are known to be slow. In this paper, a neural network algorithm is proposed that produces solutions as good as SA in substantially less time. This algorithm is based on Mean field Annealing (MFA) technique, which was successfully applied to various combinatorial optimization problems. A MFA formulation for the cell placement problem is derived which can easily be applied to all VLSI design styles. To demonstrate that the proposed algorithm is applicable in practice, a detailed formulation for the FPGA design style is derived, and the layouts of several benchmark circuits are generated. The performance of the proposed cell placement algorithm is evaluated in comparison with commercial automated circuit design software Xilinx Automatic Place and Route (APR) which uses SA technique. Performance evaluation is conducted using ACM/SIGDA Design Automation benchmark circuits. Experimental results indicate that the proposed MFA algorithm produces comparable results with APR. However, MFA is almost 20 times faster than APR on the average. (C) 1998 Elsevier Science Ltd. All rights reserved.

关键词： VLSI circuit design cell placement problem field programmable gate array mean field annealing neural-network algorithms

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Rebuttal to "Comments on 'A PUF-FSM Binding Scheme for FPGA IP Protection and Pay-Per-Device Licensing'"

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IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY 2016年第11期11卷 2626-2627页

作者： Zhang, Jiliang Qu, Gang Northeastern Univ Software Coll Shenyang 110169 Peoples R China Univ Maryland Dept Elect & Comp Engn College Pk MD 20742 USA

Concerns have been raised about our recently published article on a PUF-FSM binding scheme for FPGA IP protection and Pay-per-Device licensing. In a comment, the authors first analyzed the simple 4-bit license example we used in the article and claimed that the low overhead configuration of the FSM binding does not provide sufficiently high level of security. Then they analyzed the FSM binding structure and claimed that when a 128-bit long license is used to provide high security, the PUF-FSM scheme will incur unacceptable overhead. Both the analyses seem correct. However, they focus on some illustrative examples of our proposed binding scheme, not the main contribution which is a non-encryption based binding mechanism and its application to FPGA IP protection and pay-per-device licensing. The first claim on the low security of the 4-bit license example is true, but it is just a simple example, in reality, the key/license will be much longer. For the second claim, the balance of overhead and security can be addressed by some simple tricks such as adding few black holes used in FSM binding and the augment of number of inputs of STG. In this rebuttal, we will elaborate these.

关键词： field programmable gate array IP protection IC metering pay-per-device licensing hardware security binding

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An FPGA Based Energy-Efficient Read Mapper With Parallel Filtering and In-Situ Verification

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IEEE-ACM TRANSACTIONS ON COMPUTATIONAL BIOLOGY AND BIOINFORMATICS 2022年第5期19卷 2697-2711页

作者： Gudur, Venkateshwarlu Yellaswamy Maheshwari, Sidharth Acharyya, Amit Shafik, Rishad Indian Inst Technol Hyderabad Dept Elect Engn Kandi 502285 Telangana India Newcastle Univ Sch Engn Newcastle Upon Tyne NE1 7RU Tyne & Wear England

In the assembly pipeline of Whole Genome Sequencing (WGS), read mapping is a widely used method to re-assemble the genome. It employs approximate string matching and dynamic programming-based algorithms on a large volume of data and associated structures, making it a computationally intensive process. Currently, the state-of-the-art data centers for genome sequencing incur substantial setup and energy costs for maintaining hardware, data storage and cooling systems. To enable low-cost genomics, we propose an energy-efficient architectural methodology for read mapping using a single system-on-chip (SoC) platform. The proposed methodology is based on the q-gram lemma and designed using a novel architecture for filtering and verification. The filtering algorithm is designed using a parallel sorted q-gram lemma based method for the first time, and it is complemented by an in-situ verification routine using parallel Myers bit-vector algorithm. We have implemented our design on the Zynq Ultrascale+ XCZU9EG MPSoC platform. It is then extensively validated using real genomic data to demonstrate up to 7.8x energy reduction and up to 13.3x less resource utilization when compared with the state-of-the-art software and hardware approaches.

关键词： Bioinformatics Genomics Filtering field programmable gate arrays Hardware Sequential analysis Software field programmable gate array genome sequencing filtering low-cost low-energy read mapping verification

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Partitioned security processor architecture on FPGA platform

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IET COMPUTERS AND DIGITAL TECHNIQUES 2018年第5期12卷 216-226页

作者： Paul, Rourab Shukla, Sandeep Indian Inst Technol Kanpur Comp Sci Engn Dept Kanpur Uttar Pradesh India

Internet protocol security (IPSec), secure sockets layer (SSL)/transport layer security (TLS) and other security protocols necessitate high throughput hardware implementation of cryptographic functions. In recent literature, cryptographic functions implemented in software, application specific integrated circuit (ASIC) and field programmable gate array (FPGA). They are not necessarily optimized for throughput. Due to the various side-channel based attacks on cache and memory, and various malware based exfiltration of security keys and other sensitive information, cryptographic enclave processors are implemented which isolates the cryptographically sensitive information like keys. We propose a partitioned enclave architecture targeting IPSec, TLS and SSL where the partitioned area ensures that the processor data-path is completely isolated from the secret-key memory. The security processor consists of a Trivium random number generator, Rivest-Shamir-Adleman (RSA), advanced encryption standard (AES) and KECCAK cryptos. We implement three different optimized KECCAK architectures. The processing element (PE) handles all communication interfaces, data paths, and control hazards of network security processor. The memory of KECCAK and AES communication is done via a direct memory access controller to reduce the PE overhead. The whole system is demonstrated by FPGA implementation using Vivado 2015.2 on Artix-7 (XC7A100T, CSG324). The performances of the implemented KECCAKs are better in terms of security, throughput and resource than the existing literature.

关键词： field programmable gate arrays cryptographic protocols reconfigurable architectures coprocessors application specific integrated circuits cache storage invasive software partitioned security processor architecture FPGA platform Internet protocol security IPsec secure sockets layer transport layer security TLS network security protocols cryptographic functions application specific integrated circuit ASIC field programmable gate array FPGA side channel based attacks malware based exfiltration sensitive information security keys cryptographic enclave processors processor data-path partitioned enclave architecture SSL security protocols processor data path secret key memory Trivium random number generator RSA advanced encryption standard KECCAK crypto blocks optimised architectures KECCAK coprocessor processing element communication interfaces control signal hazards AES core communication direct memory access controller PE overhead reduction Vivado 2015 2 Artix-7 FPGA platform

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Iterative-Gradient Based Complex Divider FPGA Core with Dynamic Configurability of Accuracy and Throughput

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2011年第3期62卷 319-324页

作者： Javier Lopez-Martinez, F. del Castillo-Sanchez, Eduardo Tomas Entrambasaguas, Jose Martos-Naya, Eduardo Univ Malaga Dept Ingn Comunicac E-29071 Malaga Spain

A field programmable gate array (FPGA) implementation of a highly configurable complex divider is presented, based on an iterative gradient algorithm. The proposed architecture allows to configure both the accuracy and the throughput of the division operation, which makes it suitable for diverse applications with different requirements. Results show how various throughputs can be achieved under different maximum error and iteration limit configurations. Besides, the resource occupation is considerably small, compared with previous solutions.

关键词： field programmable gate array Digital signal processing Complex division Fixed point

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Design, implementation, and estimation of MFCV for 4-different position of human body using FPGA

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MICROELECTRONICS JOURNAL 2020年 105卷 104890-104890页

作者： Sudharsan, R. Raja Deny, J. Muthukumaran, E. Selvi, S. Chitra Kalasalingam Acad Res & Educ Dept Elect & Commun Engn Krishnan Koil Virudhunagar Dt India Dr BR Ambedkar Inst Technol Dept Elect & Commun Engn Port Blair Andaman & Nicob India Univ Coll Engn Dept Elect & Elect Engn Thirukuvalai Nagappattinam India

The motivation behind this article is to demonstrate the precision and dependability of a field programmable gate array-based implementation of muscle fibre conduction velocity (MFCV) in customary unique constrictions. The framework, leveraging the DSP unit, acquires the bio signals from four different positions of the human body, including Radial Nerve, Ulnar nerve, Auxiliary Nerve, Median nerve. The information derived through Surface Electromyogram (EMG) Electrodes is depicted as a dynamic bitstreams of the signal. The latest bitstreams are subjected to an algorithm. The subjection corresponds to the correlation of the signals from similar muscle nerves, obtained through the EMG electrodes. The whole calculation framework completely works progressively on the Altera Cyclone-V FPGA. This method is better than finding the signal dependence using a silicon resonator due to its cost and tedious design of the sensors. The myoelectric (Electromyographic) signal is recorded by the electrodes set on the four different locations associated with 1550 unique contractions. The in-vivo estimations illustrate that below the equivalent trial states, in 10 test days, the framework uncovers an MFCV mean estimation of 6.60 (+/-) 0.42 m/s for Median nerve Position, 6.43 (+/-) 0.33 m/s for Ulnar Nerve Position, 6.54 (+/-) 0.41 m/s for Radial nerve Position and 7.21 (+/-) 0.49 m/s for Auxiliary Nerve Position. The values evidence decent dependability of the estimations in an eternal application. The core part of the device being MFCV estimation, upon empirical evaluations with clinical values, shows an accuracy of 97%.

关键词： Muscle fibre conduction velocity (MFCV) Electromyogram (EMG) electrodes field programmable gate array Silicon resonator

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Implementation and performance of parallellised turbo decoders

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IET COMMUNICATIONS 2011年第1期5卷 39-50页

作者： Erdin, E. Kilcioglu, C. Yilmaz, A. O. TUBITAK Def Ind Res & Dev Inst Digital Elect Design Div Ankara Turkey ASELSAN Elect Ind Inc Commun Div Ankara Turkey Middle E Tech Univ Dept Elect & Elect Engn TR-06531 Ankara Turkey

In this study, the authors discuss the implementation of a low latency decoding algorithm for turbo codes and repeat accumulate codes and compare the implementation results in terms of maximum available clock speed, resource consumption, error correction performance and the data (information bit) rate. In order to decrease the latency a parallellised decoder structure is introduced for these mentioned codes and the results are obtained by implementing the decoders on a field programmable gate array. The memory collision problem is avoided by using collision-free interleavers. Through a proposed quantisation scheme and normalisation in forward/backward recursions, computational issues are handled for overcoming the overflow and underflow issues in a fixed point arithmetic. Also, the effect of different implementation styles are observed.

关键词： error correction clocks parallellised turbo decoder field programmable gate array Logic circuits Codes fixed point arithmetic quantisation scheme resource consumption quantisation (signal) clock speed interleaved codes field programmable gate arrays memory collision problem collision-free interleaver repeat accumulate code turbo codes iterative decoding low latency decoding algorithm

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Digital Receiver-based Electronic Intelligence System Configuration for the Detection and Identification of Intrapulse Modulated Radar Signals

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DEFENCE SCIENCE JOURNAL 2014年第2期64卷 152-158页

作者： Singh, A. K. Rao, K. Subba Def Elect Res Lab Hyderabad 500005 Andhra Pradesh India Osmania Univ Hyderabad 500075 Andhra Pradesh India

An optimum electronic intelligence system configuration incorporating the state of the art technologies and achieving the highest parameter accuracies while processing the complex intrapulse modulated radar signals is presented in this paper. The system is based on the quad digital receiver, a state of the art single board solution for the detection and analysis of modern radar signals. The system consists of base line interferometry configuration for high accuracy direction finding measurement with sector selection based on amplitude direction finding technique. Advanced signal processing algorithms with time frequency analysis are implemented in real time in field programmable gate array to extract all the basic as well as advanced parameters of frequency and phase modulations such as chirp, barker, and poly-phase (Frank, P1-P4) codes in addition to the pulse and continuous wave signals. The intercepted intrapulse modulated signal parameters have been extracted with very high accuracy and sensitivity.

关键词： Electronic intelligence quad digital receiver analog to digital converter field programmable gate array electronic warfare fast Fourier transform intrapulse

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Sensor Non Uniformity Correction Algorithms and its Real Time Implementation for Infrared Focal Plane array-based Thermal Imaging System

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DEFENCE SCIENCE JOURNAL 2013年第6期63卷 589-598页

作者： Kumar, Ajay Instruments Res & Dev Estab Dehra Dun 248008 Uttar Pradesh India

The advancement in infrared (IR) detector technologies from 1st to 3rd generation and beyond has resulted in the improvement of infrared imaging systems due to availability of IR detectors with large number of pixels, smaller pitch, higher sensitivity and large F-number. However, it also results in several problems and most serious of them is sensor non-uniformities, which are mainly attributed to the difference in the photo-response of each detector in the infrared focal plane array. These spatial and temporal non-uniformities result in a slowly varying pattern on the image usually called as fixed pattern noise and results in the degradation the temperature resolving capabilities of thermal imaging system considerably. This paper describes two types of non uniformity correction methodologies. First type of algorithms deals with correction of sensor non-uniformities based upon the calibration method. Second type of algorithm deals with correction of sensor non uniformities using scene information present in the acquired images. The proposed algorithms correct both additive and multiplicative non uniformities. These algorithms are evaluated using the simulated & actual infrared data and results of implementations are presented. Furthermore, proposed algorithms are implemented in field programmable gate array based embedded hardware.

关键词： Infrared focal plane array infrared imaging field programmable gate array non uniformities

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Novel CNN Accelerator Design With Dual Benes Network Architecture

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IEEE ACCESS 2023年 11卷 59524-59529页

作者： Lo, Chun Yan Sham, Chiu-Wing Fu, Chong Univ Auckland Sch Comp Sci Auckland 1010 New Zealand Northeastern Univ Sch Comp Sci & Engn Shenyang 110819 Peoples R China

We presented a novel hardware architecture that uses dual Benes networks to accelerate Convolutional Neural Network (CNN) algorithms. This architecture can reduce the need for high-speed buses and maintain a high-speed connection between execution units and memories. Also, this design can work with multiple neural network models by changing the Benes network configuration only due to the reorderability of the non-blocking networks. The proposed architecture can save the time of re-implementing the hardware design. Thus, this architecture can act as a general CNN accelerator. We successfully implemented our CNN accelerator on the Xilinx Virtex UltraScale+ VU19P and evaluated it by running the CNN model LeNet-5.

关键词： Convolutional neural networks field programmable gate array hardware acceleration

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