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检索条件"主题词=Field Programmable Gate array"
1339 条 记 录,以下是331-340 订阅
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A fast neural-network algorithm for VLSI cell placement
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NEURAL NETWORKS 1998年 第9期11卷 1671-1684页
作者: Aykanat, C Bultan, T Haritaoglu, I Bilkent Univ Dept Comp Engn TR-06533 Ankara Turkey Univ Maryland Dept Comp Sci College Pk MD 20742 USA
Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gate array, and field programmable gate array (FPGA). Although nondeterministic algorithms such as Simulated Annealing ... 详细信息
来源: 评论
Rebuttal to "Comments on 'A PUF-FSM Binding Scheme for FPGA IP Protection and Pay-Per-Device Licensing'"
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IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY 2016年 第11期11卷 2626-2627页
作者: Zhang, Jiliang Qu, Gang Northeastern Univ Software Coll Shenyang 110169 Peoples R China Univ Maryland Dept Elect & Comp Engn College Pk MD 20742 USA
Concerns have been raised about our recently published article on a PUF-FSM binding scheme for FPGA IP protection and Pay-per-Device licensing. In a comment, the authors first analyzed the simple 4-bit license example... 详细信息
来源: 评论
An FPGA Based Energy-Efficient Read Mapper With Parallel Filtering and In-Situ Verification
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IEEE-ACM TRANSACTIONS ON COMPUTATIONAL BIOLOGY AND BIOINFORMATICS 2022年 第5期19卷 2697-2711页
作者: Gudur, Venkateshwarlu Yellaswamy Maheshwari, Sidharth Acharyya, Amit Shafik, Rishad Indian Inst Technol Hyderabad Dept Elect Engn Kandi 502285 Telangana India Newcastle Univ Sch Engn Newcastle Upon Tyne NE1 7RU Tyne & Wear England
In the assembly pipeline of Whole Genome Sequencing (WGS), read mapping is a widely used method to re-assemble the genome. It employs approximate string matching and dynamic programming-based algorithms on a large vol... 详细信息
来源: 评论
Partitioned security processor architecture on FPGA platform
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IET COMPUTERS AND DIGITAL TECHNIQUES 2018年 第5期12卷 216-226页
作者: Paul, Rourab Shukla, Sandeep Indian Inst Technol Kanpur Comp Sci Engn Dept Kanpur Uttar Pradesh India
Internet protocol security (IPSec), secure sockets layer (SSL)/transport layer security (TLS) and other security protocols necessitate high throughput hardware implementation of cryptographic functions. In recent lite... 详细信息
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Iterative-Gradient Based Complex Divider FPGA Core with Dynamic Configurability of Accuracy and Throughput
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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2011年 第3期62卷 319-324页
作者: Javier Lopez-Martinez, F. del Castillo-Sanchez, Eduardo Tomas Entrambasaguas, Jose Martos-Naya, Eduardo Univ Malaga Dept Ingn Comunicac E-29071 Malaga Spain
A field programmable gate array (FPGA) implementation of a highly configurable complex divider is presented, based on an iterative gradient algorithm. The proposed architecture allows to configure both the accuracy an... 详细信息
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Design, implementation, and estimation of MFCV for 4-different position of human body using FPGA
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MICROELECTRONICS JOURNAL 2020年 105卷 104890-104890页
作者: Sudharsan, R. Raja Deny, J. Muthukumaran, E. Selvi, S. Chitra Kalasalingam Acad Res & Educ Dept Elect & Commun Engn Krishnan Koil Virudhunagar Dt India Dr BR Ambedkar Inst Technol Dept Elect & Commun Engn Port Blair Andaman & Nicob India Univ Coll Engn Dept Elect & Elect Engn Thirukuvalai Nagappattinam India
The motivation behind this article is to demonstrate the precision and dependability of a field programmable gate array-based implementation of muscle fibre conduction velocity (MFCV) in customary unique constrictions... 详细信息
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Implementation and performance of parallellised turbo decoders
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IET COMMUNICATIONS 2011年 第1期5卷 39-50页
作者: Erdin, E. Kilcioglu, C. Yilmaz, A. O. TUBITAK Def Ind Res & Dev Inst Digital Elect Design Div Ankara Turkey ASELSAN Elect Ind Inc Commun Div Ankara Turkey Middle E Tech Univ Dept Elect & Elect Engn TR-06531 Ankara Turkey
In this study, the authors discuss the implementation of a low latency decoding algorithm for turbo codes and repeat accumulate codes and compare the implementation results in terms of maximum available clock speed, r... 详细信息
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Digital Receiver-based Electronic Intelligence System Configuration for the Detection and Identification of Intrapulse Modulated Radar Signals
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DEFENCE SCIENCE JOURNAL 2014年 第2期64卷 152-158页
作者: Singh, A. K. Rao, K. Subba Def Elect Res Lab Hyderabad 500005 Andhra Pradesh India Osmania Univ Hyderabad 500075 Andhra Pradesh India
An optimum electronic intelligence system configuration incorporating the state of the art technologies and achieving the highest parameter accuracies while processing the complex intrapulse modulated radar signals is... 详细信息
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Sensor Non Uniformity Correction Algorithms and its Real Time Implementation for Infrared Focal Plane array-based Thermal Imaging System
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DEFENCE SCIENCE JOURNAL 2013年 第6期63卷 589-598页
作者: Kumar, Ajay Instruments Res & Dev Estab Dehra Dun 248008 Uttar Pradesh India
The advancement in infrared (IR) detector technologies from 1st to 3rd generation and beyond has resulted in the improvement of infrared imaging systems due to availability of IR detectors with large number of pixels,... 详细信息
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Novel CNN Accelerator Design With Dual Benes Network Architecture
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IEEE ACCESS 2023年 11卷 59524-59529页
作者: Lo, Chun Yan Sham, Chiu-Wing Fu, Chong Univ Auckland Sch Comp Sci Auckland 1010 New Zealand Northeastern Univ Sch Comp Sci & Engn Shenyang 110819 Peoples R China
We presented a novel hardware architecture that uses dual Benes networks to accelerate Convolutional Neural Network (CNN) algorithms. This architecture can reduce the need for high-speed buses and maintain a high-spee... 详细信息
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