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作者： Purkayastha, Arnab A. The University of North Carolina at Charlotte

学位级别：Ph.D., Doctor of Philosophy

The availability of OpenCL for FPGAs along with High-Level Synthesis tools have made them an attractive platform for implementing compute-intensive massively parallel applications. FPGAs with their customizable data-path, deep pipelining abilities and enhanced power efficiency features offer the most viable solutions for programming and integrating them with heterogeneous platforms. However, OpenCL for FPGAs raise many design challenges which require an in-depth understanding to better utilize their enormous capabilities. Inefficient routing of data, high number of memory stalls exposed to execution and under-utilization of FPGA resources are significant execution bottlenecks that overshadow the advantages of data-path customization. Furthermore, leveraging OpenCL parallelism abilities and throughput oriented principles is paramount to the success of FPGAs in the high performance computing environment. In this research, we identify, analyze and categorize the architectural differences between the OpenCL parallel programming model and FPGA execution semantic. We propose a generic taxonomy for classifying FPGA parallelism potential to the fullest. To benefit massive thread-level parallelism, we introduce a unique LLVM based automation tool to decouple memory access from computation, thereby hiding memory stalls from the execution path. We further present a novel parallelism granularity that separates kernels to split them into data-path and memory-path (memory read/write) that work concurrently to overlap the computation of current threads with the memory access of future threads. We validate these principles on the Xilinx based AWS Cloud FPGA platform. We then conduct a thorough investigation into the scalability of OpenCL coarse-grain parallelism, as well as an examination of Compute Unit(CU) replication, Double Data Rate (DDR) and Burst Transfer (BT) optimizations on Cloud FPGAs. To address the issue of programming challenges, we present generic template(s) and a f

关键词： Cloud FPGA field programmable gate array High level synthesis Low level virtual machine OpenCL Parallelism Open computing language Architecture

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A Dataset Generation for Object Recognition and a Tool for Generating ROS2 FPGA Node 20

A Dataset Generation for Object Recognition and a Tool for G...

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20th International Conference on field-programmable Technology (ICFPT)

作者： Amano, Hayato Mori, Hayato Mizutani, Akinobu Ono, Tomohiro Yoshimoto, Yuma Ohkawa, Takeshi Tamukoh, Hakaru Kyushu Inst Technol Grad Sch Life Sci & Syst Engn Kitakyushu Fukuoka Japan Tokai Univ Dept Embedded Technol Minato Ku Tokyo Japan Japan Soc Promot Sci Chiyoda Ku Tokyo Japan Kyushu Inst Technol Res Ctr Neuromorph AI Hardware Kitakyushu Fukuoka Japan

ISBN: (纸本)9781665420105

This paper introduces our autonomous driving system equipped with recognition processing units from a camera image for hazard object / human-doll detection and drive lane detection. In particular, this paper focuses on a dataset generation method for neural networks and a generation tool "FPGA Oriented Easy Synthesizer Tool (FOrEST)" for ROS2-FPGA nodes. The results show that mAP of a neural network trained by the generated dataset is 94 %, and a overhead of ROS2-FPGA communication by the FOrEST is 2-3 ms.

关键词： field programmable gate array Robot Operating System Dataset Generation Robot Car

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MPC based Controller Design of Battery Integrated Modular Multilevel Converter 40

MPC based Controller Design of Battery Integrated Modular Mu...

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40th Chinese Control Conference (CCC)

作者： Xu, Fang Guo, Zhongyi Liu, Qifang Chen, Hong Qu, Yali Jilin Univ State Key Lab Automot Simulat & Control Changchun 130025 Peoples R China Jilin Univ Coll Commun Engn Changchun 130025 Peoples R China Tongji Univ Dept Control Sci & Engn Shanghai 201804 Peoples R China Huawei Technol Co Ltd Beijing 100022 Peoples R China

ISBN: (纸本)9789881563804

The control performance of converter directly affects the drive efficiency of electric vehicle (EV). This paper studies on the model predictive control (MPC) based controller design of battery integrated modular multilevel converter (B-MMC). Aiming at the goal of three-phase current tracking and battery balancing control of B-MMC, three-layer controllers are designed. The first controller is the finite control set model predictive control (FCS-MPC), which realizes the motor drive by tracking the phase current. The second controller is the circulation controller for the active balance control of battery. It is composed of multiple proportional controllers to realize the battery balance between the bridge arms. The third controller is the battery sorting algorithm to achieve the passive balance control of the battery in the same bridge arm. At the same time, field programmable gate array (FPGA) is used to accelerate the controller to meet the real-time requirements of B-MMC. Finally, the simulation results of the B-MMC control system validates the effectiveness of the control algorithm.

关键词： Electric Vehicle Battery Integrated Modular Multilevel Converter Finite Control Set Model Predictive Control field programmable gate array

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Hierarchical hardware trojan for LUT-based AI devices and its evaluation

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ELECTRONICS AND COMMUNICATIONS IN JAPAN 2022年第1期105卷

作者： Nozaki, Yusuke Takemoto, Shu Ikezaki, Yoshiya Yoshikawa, Masaya Meijo Univ Fac Sci & Technol Tenpaku Ku Nagoya Aichi 4688502 Japan Meijo Univ Grad Sch Sci & Technol Tempaku Ku Nagoya Aichi Japan

To realize Society 5.0, edge AI techniques have attracted attention. On the other hand, security issues of edge AI have been reported. In addition, in the field of hardware security, the threat of hardware Trojan (HT) is emphasized. To defend the AI device from malicious attacks, it is important to check the vulnerability against various attacks. Therefore, this study proposes a new HT for AI inference devices. The proposed HT falsifies the inference result with respect to an arbitrary trigger input. The proposed HT concentrates on the Lookup Table (LUT) structure, and can be achieved by rewriting the LUT table information. As a result, the proposed HT does not need additional trojan trigger and payload circuits, that is, it can be implemented without the circuit overhead. Experiments by field programable gate array show the validity of the proposed HT.

关键词： AI security field programmable gate array hardware security hardware Trojan

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FPGA control system technology for integrating the PV/wave/FC hybrid system using ANN optimized by MFO techniques

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SUSTAINABLE CITIES AND SOCIETY 2022年第0期80卷 103825-103825页

作者： Talaat, M. Alblawi, Adel Tayseer, M. Elkholy, M. H. Zagazig Univ Fac Engn Elect Power & Machines Dept PO Zagazig 44519 Egypt Shaqra Univ Coll Engn Mech Engn Dept PO Ar Riyadh 11911 Saudi Arabia Egyptian Chinese Univ Fac Engn & Technol PO Cairo 11787 Egypt

Despite the merits of Renewable Energy Sources (RES) as clean and reliable alternatives for electrical energy generation, there are some problems related to their highly cost and low efficient operation with non - linear loads. As one of the most vital methodologies to improve the operational quality of RES within the electrical network, the integration of RES in a one hybrid system can effectively contribute to overcome the obstacles of the randomness and inability to accurately predict the daily generation of each individual RES. In this research, Fuel Cells (FCs) are practically integrated with two renewable sources (wave energy and solar energy) utilizing the field programmable gate array (FPGA) as a new innovative digital controller technique. FPGAs are chosen in this study for its ultra - fast processing speed that is expected to reach to almost 100 MHz and its higher response than other microcontrollers for RES integration. Although the merits of FPGAs like fast response, having no processors and behaving in a parallel manner, there are some obstacles in controlling the energy level of RES during the integration process. To overcome the problems of FPGAs, Moth Flame Optimization (MFO) algorithm is utilized with Artificial Neural Network (ANN) to enhance its operational accuracy for providing an effective and precise forecasting control scenario for the proposed hybrid system. In this paper, FCs are provided as an effective Battery Energy Storage Systems (ESS) to overcome the sudden operational outage of any RES to ensure the reliability of the proposed hybrid system within the electrical network. This research provides the hybrid combination between the Buck - Boost converter and FPGA as a vital approach to adjust the voltage level of the proposed RES integration within a reasonable value. In this research, all the obtained results are assessed based on the available previous simulation and empirical data to confirm the validity and high response of the FPGA

关键词： field programmable gate array Fuel Cells Wave Energy Solar Energy Buck Boost Artificial Neural Network Moth Flame Optimization Algorithm

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Secure image encryption using high throughput architectures of PRINT cipher for radio frequency identification applications

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JOURNAL OF ELECTRONIC IMAGING 2022年第6期31卷 063036-063036页

作者： Kumari, Manisha Singh, Pulkit Acharya, Bibhudendra Natl Inst Technol Raipur Dept Elect & Commun Engn Raipur Chhattisgarh India MLR Inst Technol Dept Elect & Commun Engn Hyderabad India

With the enhancement of technology, data security has become incredibly significant. Nowadays, images and vital information are used in real-time, and high throughput architecture is required for internet of things and real-time applications. We mainly focus on the high throughput architecture of PRINT cipher. PRINT cipher is a lightweight block cipher with a block size of 48-bit and 96-bit. Loop-unrolled, 48-bit pipelined, and 96-bit pipelined architectures are designed and implemented on different field programmable gate array and application-specific integrated circuit platforms. The maximum operating frequency obtained for 48-bit pipelined is 259.67 MHz on Virtex-4 and 310.67 MHz for 96-bit pipelined on Virtex-5. Finally, with the help of a controller, 48-bit high throughput pipelined architecture was utilized for image encryption of both grayscale and color images. The security analysis of encrypted images for color and grayscale images using PRINT cipher shows better performance and more robust protection against statistical, entropy, and differential attacks. (c) 2022 SPIE and IS&T

关键词： lightweight cryptography internet of things PRINT cipher image encryption radio frequency identification field programmable gate array application-specific integrated circuit

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Flexible Matrix of Controllers for Real Time Parallel Control

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ENERGIES 2022年第5期15卷 1833-1833页

作者： Chaber, Patryk Wojtulewicz, Andrzej Warsaw Univ Technol Fac Elect & Informat Technol Inst Control & Computat Engn Ul Nowowiejska 15-19 PL-00665 Warsaw Poland

This work aims to develop a novel system, including software and hardware, to perform independent control tasks in a genuine parallel manner. Currently, to control processes with various sampling periods, distributed control systems are most commonly utilized. The main goal of this system is to propose an alternative solution, which allows simultaneous control of both fast and slow processes. The presented approach utilizes FPGA (field programmable gate array) with Nios II processor (Intel Soft Processor Series) to implement and maintain instances of independent controllers. Instances can implement FDMC (Fast Dynamic Matrix Control) and PID (Proportional-Integral-Derivative) control algorithms with various sampling times. The FPGA-based design allows for true independence of controllers' execution both from one another and the managing processor. Also, pure parallel execution allows for implementing slow and fast controllers in the same device. The complete flexible system with a matrix of controllers working in parallel in real-time was tested with both simulated and actual control processes (servomotor), yielding the same results as fully simulated experiments.

关键词： Model Predictive Control Fast Dynamic Matrix Controller field programmable gate array servomotor matrix of controllers

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Software and hardware co-design and implementation of intelligent optimization algorithms

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APPLIED SOFT COMPUTING 2022年第0期129卷

作者： Fu, Zonglin Chu, Shu-Chuan Watada, Junzo Huc, Chia-Cheng Pan, Jeng-Shyang Shandong Univ Sci & Technol Coll Comp Sci & Engn Qingdao 266590 Peoples R China Waseda Univ Grad Sch Informat Prod & Syst Kitakyushu Fukuoka 8080135 Japan Yango Univ Coll Artificial Intelligence Fuzhou 330015 Peoples R China Chaoyang Univ Technol Dept Informat Management Taichung Taiwan

In order to improve the operating efficiency of the algorithm, some intelligent optimization algorithms are considered to be implemented on hardware. However, the existing design scheme has the problem of poor versatility. Therefore, this paper proposes a general software-hardware co-design scheme of intelligent optimization algorithms. In the design scheme, the initialization module and fitness module of the algorithm are deployed on the Advanced RISC Machines (ARM) for execution to increase the flexibility of the program. The update module of the algorithm is deployed on the field programmable gate array (FPGA) for execution to realize the hardware acceleration. The data between ARM and FPGA is transferred through Advanced eXtensible Interface (AXI) bus. In this paper, the PSO, BA, WOA, GWO, CMAES and EO algorithms are implemented with the proposed design scheme. And the six algorithms are tested on thirteen benchmark functions of different types. The experimental results prove the feasibility of the design scheme. In addition, by comparing with software and other implementation methods in execution time, resource occupancy and convergence, the effectiveness and superiority of the proposed scheme are proved. (c) 2022 Elsevier B.V. All rights reserved.

关键词： Intelligent optimization algorithm Advanced RISC machines field programmable gate array Advanced eXtensible interface

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Low Power Transposed Form 4-Tap Finite Impulse Response Filter Using Power Efficient Multiply Accumulate Unit

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2022年第1期31卷 2250016-2250016页

作者： Rakesh, S. Grace, K. S. Vijula Noorul Islam Ctr Higher Educ Dept Elect & Commun Engn Thuckalay 629180 Tamil Nadu India

Finite impulse response (FIR) filters find wide application in signal processing applications on account of the stability and linear phase response of the filter. These digital filters are used in applications, like biomedical engineering, wireless communication, image processing, speech processing, digital audio and video processing. Low power design of FIR filter is one of the major constraints that researchers are trying hard to achieve. This paper presents the implementation of a novel power efficient design of a 4-tap 16-bit FIR filter using a modified Vedic multiplier (MVM) and a modified Han Carlson adder (MHCA). The units are coded using Verilog hardware description language and simulated using Xilinx Vivado Design Suite 2015.2. The filter is synthesized for the 7-series Artix field programmable gate array with xc7a100tcsg324-1 as the target device. The proposed filter design showed an improvement of a maximum of 57.44% and a minimum of 2.44% in the power consumption compared to the existing models.

关键词： Finite impulse response filter field programmable gate array modified Han Carlson adder modified Vedic multiplier multiply accumulate unit Xilinx Vivado design suite

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Novel Record Replacement Algorithm and Architecture for QoS Management over Local Area Networks

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MICROMACHINES 2022年第4期13卷 594-594页

作者： Tung, Yi-Chih Law, Yuk-Wing Hwang, Wen-Jyi Tai, Tsung-Ming Ho, Chih-Hsiang Chen, Cheng-Chang Ming Chi Univ Technol Dept Elect Engn New Taipei 243 Taiwan Natl Taiwan Normal Univ Dept Comp Sci & Informat Engn Taipei 116 Taiwan NVIDIA AI Technol Ctr Taipei 114 Taiwan Inst Informat Ind Taipei 106 Taiwan Bur Stand Metrol & Inspect MOEA Taipei 100 Taiwan

An effective System-on-Chip (SoC) for smart Quality-of-Service (QoS) management over a virtual local area network (LAN) is presented in this study. The SoC is implemented by field programmable gate array (FPGA) for accelerating the delivery quality prediction for a service. The quality prediction is carried out by the general regression neural network (GRNN) algorithm based on a time-varying profile consisting of the past delivery records of the service. A novel record replacement algorithm is presented to update the profile, so that the bandwidth usage of the service can be effectively tracked by GRNN. Experimental results show that the SoC provides self-aware QoS management with low computation costs for applications over virtual LAN.

关键词： System-on-Chip Quality-of-Service field programmable gate array local area network general regression neural network network function virtualization

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