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A high throughput hardware architecture for deblocking filter in HEVC

SIGNAL PROCESSING-IMAGE COMMUNICATION 2022年 100卷 116517-116517页

作者： Kopperundevi, P. Prakash, Matcha Surya Ahamed, Shaik Rafi Natl Inst Technol Calicut Calicut Kerala India Indian Inst Technol Guwahati Gauhati India

This paper presents a high throughput hardware architecture for deblocking filter in high efficiency video coding (H.265/HEVC) standard. The architecture uses an efficient hybrid pipelining and parallel processing techniques for intra encoder. A single edge filter is designed to process both horizontal and vertical filtering of pixels one after the other respectively. In our proposed architecture, the video frame is divided into 32 x 32 blocks and each block is processed by splitting them into blocks of 8 x 32 pixels in a pipelined manner. Parallel processing is employed for filtering the edges which helped in improving the throughput by decreasing the processing clock cycles. It has been observed that the largest coding tree unit block that the hardware architecture can process is 64 x 64 pixels and can be achieved in 64 clock cycles. Synthesis results of the Verilog design for the proposed architecture using application specific integrated circuit 180 nm standard cell library shows that it consumes 102k 2-input NAND gates and can work at a maximum clock frequency of 250 MHz. The proposed design is capable of supporting 8k ultra high definition video sequences at 322 Frames Per Second (fps) which is the best among the existing present-day architectures.

关键词： Deblocking filter H.265/HEVC Pipelining Parallel processing Application specific integrated circuit field programmable gate array

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A Disturbance Suppression Zeroing Neural Network for Robust Synchronization of Chaotic Systems and Its FPGA Implementation

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INTERNATIONAL JOURNAL OF BIFURCATION AND CHAOS 2022年第14期32卷 2250210-2250210页

作者： Chen, Weijie Jin, Jie Chen, Chaoyang Yu, Fei Wang, Chunhua Hunan Univ Sci & Technol Sch Informat & Elect Engn Xiangtan 411201 Peoples R China Changsha Univ Sci & Technol Sch Comp & Commun Engn Changsha 410114 Peoples R China Hunan Univ Sch Comp Sci & Elect Engn Changsha 410082 Peoples R China

The synchronization of chaotic systems plays an extremely imperative and fundamental role in the fields of science and engineering. Notably, various external noise disturbances have a great impact on the synchronization of chaotic systems because chaotic systems are quite sensitive to the change of their initial values. Consequently, the robustness of chaotic system synchronization must be considered in practical applications. From this viewpoint, the present paper proposes a disturbance suppression zeroing neural network (DSZNN) for robust synchronization of chaotic and hyperchaotic systems, and the DSZNN is implemented on field programmable gate array (FPGA) for further hardware validation. The distinctive features of the proposed DSZNN controller have the ability to suppress disturbance with faster convergent speed and higher accuracy compared with super-exponential zeroing neural network (SEZNN) and conventional zeroing neural network (CZNN). Moreover, theoretical analysis, comparative numerical simulations and hardware validations for the synchronization of a hyperchaotic system are presented to demonstrate the superior performance of the proposed DSZNN.

关键词： Zeroing neural network chaotic system synchronization field programmable gate array noise disturbances

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Performance comparison of CNN, QNN and BNN deep neural networks for real-time object detection using ZYNQ FPGA node

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MICROELECTRONICS JOURNAL 2022年 119卷 105319-105319页

作者： Mani, V. R. S. Saravanaselvan, A. Arumugam, N. Natl Engn Coll Dept Elect & Commun Engn Kovilpatti Tamil Nadu India

In this manuscript, previously trained Convolutional neural network (CNN), Quantum Neural Network (QNN), and Binarized Neural Network (BNN) models performed employing Tensor Flow's Application Programming Interface (API) for real-time object detection and implemented on FPGA. Then, the proposed real time objects detection based on CNN, QNN and BNN Deep Neural Networks classifier mode activated on python, and then the dataset taken from PASCAL VOC. For an accuracy analysis of real time objection detection, this real time objects detection based on CNN Deep Neural Networks classifier provide 3.458% and 1.600% higher accuracy value than proposed real time objects detection. Then, the proposed real time objects detection based on CNN, QNN and BNN Deep Neural Networks classifier model verified by using the Verilog programming language in the Xilinx ISE 14.5 design tools in the ZYNQ FPGA development team. These results show the FPGA implementation of this real time objects detection based on CNN Deep Neural Networks classifier model meets the objective efficiently.

关键词： Deep neural networks Real-time object detection field programmable gate array Convolutional neural network Binarized neural network Quantum neural network

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Scalable Control System Based on Matrix of Controllers – Preliminary Results

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IFAC-PapersOnLine 2022年第4期55卷 183-188页

作者： Chaber Patryk Wojtulewicz Andrzej Warsaw University of Technology Institute of Control and Computation Engineering ul. Nowowiejska 15/19 00-665 Warsaw Poland

The work aims to develop an original software and hardware structure for the regulation of fast dynamic processes. The structure will allow simultaneous predictive regulation of many processes with independent dynamics. Designing the matrix of regulators managed by a specialized subsystem allows the user to use advanced regulation algorithms within a single embedded system, which will improve the design and development processes of an industrial regulation system. The presented innovative approach will allow the reproduction of many control scenarios such as parallel regulation of several processes or securing the regulation of a critical process by a redundancy of controllers.

关键词： field programmable gate array Model Predictive Control Matrix of Controllers

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FPGA implementation of adaptive p-norm filter for non-stationary power signal parameter estimation

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IET SCIENCE MEASUREMENT & TECHNOLOGY 2020年第2期14卷 206-219页

作者： Nanda, Sarita Pattnaik, Ansuman Dash, Pradipta Kishore KIIT Univ Sch Elect Engn Bhubaneswar Odisha India Siksha O Anusandhan Univ Multidisciplinary Res Cell Bhubaneswar Odisha India

A p-norm extreme learning machine (ELM) based on sparsity constraint is presented in this study for tracking of fundamental frequency, harmonic and dc in current power signals which finds application in phasor measurement units for wide area power network in smart grid environment. Real-time power applications typically are furnished with on-board controller and hence have constraints to stock a complex architecture. Moreover, the data from online practices are polluted by noises of diverse statistical features obtained on a sample-by-sample basis. Hence, approaches with improved learning paradigm and close model dealing with noises of varied statistical characteristics are essential. The proposed approach formulates a cost function with recursive p-norm error criterion and sparsity penalty that updates the output weights in succession besides adjusting some coefficients of the output weights to zeros that promotes quicker convergence and higher accuracy results. Exhaustive computer simulations have been carried out with synthetic signals and real-time signals to track the dynamic changes in the power signal amplitude, phase and frequency that demonstrate the accuracy, efficiency and robustness of the proposed p-norm ELM. Additionally, the new ELM network also is validated on a field programmable gate array (FPGA) hardware to prove its practicability towards current developments on phasor measurement units.

关键词： parameter estimation field programmable gate arrays power engineering computing phase measurement learning (artificial intelligence) smart power grids synthetic signals real-time signals power signal amplitude p-norm ELM ELM network field programmable gate array hardware phasor measurement units FPGA implementation p-norm filter nonstationary power signal parameter estimation p-norm extreme learning machine sparsity constraint fundamental frequency harmonic dc current power signals wide area power network smart grid environment real-time power applications on-board controller complex architecture online practices diverse statistical features sample-by-sample basis improved learning paradigm varied statistical characteristics p-norm error criterion sparsity penalty higher accuracy results recursive p-norm error criterion field programmable gate array

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FPGAN: An FPGA Accelerator for Graph Attention Networks With Software and Hardware Co-Optimization

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IEEE ACCESS 2020年 8卷 171608-171620页

作者： Yan, Weian Tong, Weiqin Zhi, Xiaoli Shanghai Univ Sch Comp Engn & Sci Shanghai 200444 Peoples R China Shanghai Univ Shanghai Inst Adv Commun & Data Sci Shanghai 200444 Peoples R China

The Graph Attention Networks (GATs) exhibit outstanding performance in multiple authoritative node classification benchmark tests (including transductive and inductive). The purpose of this research is to implement an FPGA-based accelerator called FPGAN for graph attention networks that achieves significant improvement on performance and energy efficiency without losing accuracy compared with PyTorch baseline. It eliminates the dependence on digital signal processors (DSPs) and large amounts of on-chip memory and can even work well on low-end FPGA devices. We design FPGAN with software and hardware co-optimization across the full stack from algorithm through architecture. Specifically, we compress model to reduce the model size, quantify features to perform fixed-point calculation, replace multiplication addition cell (MAC) with shift addition units (SAUs) to eliminate the dependence on DSPs, and design an efficient algorithm to approximate SoftMax function. We also adjust the activation functions and fuse operations to further reduce the computation requirement. Moreover, all data is vectorized and aligned for scalable vector computation and efficient memory access. All the above optimizations are integrated into a universal hardware pipeline for various structures of GATs. We evaluate our design on an Inspur F10A board with an Intel Arria 10 GX1150 and 16 GB DDR3 memory. Experimental results show that FPGAN can achieve 7.34 times speedup over Nvidia Tesla V100 and 593 times over Xeon CPU Gold 5115 while maintaining accuracy, and 48 times and 2400 times on energy efficiency respectively.

关键词： field programmable gate arrays Acceleration Computational modeling Computer architecture Optimization Hardware Energy efficiency Graph attention networks model optimization inference accelerating field programmable gate array heterogeneous computing parallel computing energy efficiency shift operation

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HopliteRT*: Real-Time NoC for FPGA

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2020年第11期39卷 3650-3661页

作者： Gonzalez, Yilian Ribot Nelissen, Geoffrey Polytech Inst Porto ISEP CISTER Res Ctr P-4200465 Porto Portugal Eindhoven Univ Technol Dept Math & Comp Sci NL-5612 AZ Eindhoven Netherlands

With the increasing number of computation nodes integrated in multi and many-core platforms, network-on-chips (NoCs) emerged as a new communication medium in systems-on-chips (SoCs). HopliteRT is a new NoC design that was recently proposed to address the needs of real-time systems whilst respecting the constraints of field-programmable gate array (FPGA) platforms. In this article, we: 1) introduce priority-based routing in HopliteRT;2) change the network topology in order to improve the packets' worst-case traversal time (WCTT);3) identify a flaw in the existing timing analysis of HopliteRT;and 4) develop a new timing analysis that is proven correct. We also show by means of experiments that the modifications of HopliteRT proposed in this article allows for at least 2x improvement on the worst and average case traversal time of high priority packets, without impacting the quality of service of low-priority packets. The timing properties of high priority flows are greatly improved for negligible additional hardware costs. The proposed NoC has been implemented in Verilog and synthesized for a Xilinx Virtex-7 FPGA platform.

关键词： field programmable gate array network-onchips real-time embedded systems systems-on-chips timing analysis

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FPGA implementation of NN based LMS-LMF control algorithm in DSTATCOM for power quality improvement

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CONTROL ENGINEERING PRACTICE 2020年 98卷 104378-000页

作者： Malathi, S. Jayachandran, J. SASTRA Deemed Univ Dept Elect & Elect Engn Thanjavur 613401 Tamil Nadu India

Neural Network (NN) based Least Mean Square (LMS)-Least Mean Fourth (LMF) control technique is developed and implemented in field programmable gate array (FPGA) for Shunt Active Power Filter (SAPF) to enhance Power Quality (PQ) in three-phase four wire distribution system. The PQ enhancement comprises the improvement of power factor, mitigation of harmonics and compensation of reactive power. The proposed control strategy is simulated in MATLAB/Simulink to determine the reference source currents and weights of active and reactive components. The simulation results of LMS-LMF control are compared with the other three control strategies. The NN control is developed as individual modules in FPGA. Thus it can be configured to any other research area which has identical requirements. The FPGA implementation overcomes the drawback of conventional controllers with a fast and accurate response. The FPGA based proposed control strategy for SAPF is developed as a laboratory prototype and the results obtained are analyzed. The results attained adhere to power quality standards.

关键词： Neural network Shunt active power filter Total harmonic distortion field programmable gate array Power quality

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An energy efficient FPGA partial reconfiguration based micro-architectural technique for IoT applications

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MICROPROCESSORS AND MICROSYSTEMS 2020年第0期73卷 102966-000页

作者： Kiat, Wei-Pau Mok, Kai-Ming Lee, Wai-Kong Goh, Hock-Guan Achar, Ramachandra Univ Tunku Abdul Rahman Fac Informat & Commun Technol Kampar Perak Malaysia Carleton Univ Dept Elect Ottawa ON K1S 5B6 Canada

Low power consumption and high computational performance are two important processor design goals for IoT applications. Achieving both design goals in one processor architecture is challenging due to their conflicting requirements. This paper introduces a reconfigurable micro-architectural level technique that allows a Reduced Instruction Set Computing (RISC) processor to support IoT applications with different performance and energy trade-off requirements. The processor can be reconfigured into either multi-cycle execution mode (low computational speed with low dynamic power consumption) or pipeline execution mode (high computational speed at the expense of high dynamic power), based on dynamic workload characteristics in IoT applications. Switching between modes is accomplished by exploiting the partial reconfiguration (PR) feature offered by the recent advancements in modern FPGAs. A RISC processor was designed based on the proposed micro-architectural level technique and implemented on FPGA as IoT sensor node. Experimental results demonstrate that the proposed technique with reconfigurable microarchitecture is able to significantly reduce the dynamic energy consumption, compared to conventional multi-cycle and pipeline only micro-architectures, while allowing better performance-energy trade-off in IoT applications. (C) 2019 Elsevier B.V. All rights reserved.

关键词： field programmable gate array Internet-of-Things Low power Partial reconfiguration Multi-cycle execution (ME) Pipeline execution (PE) RISC Sensor node (SN)

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Real-time emulation of a three-phase Vienna rectifier with DC voltage control and power factor correction

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ELECTRICAL ENGINEERING 2020年第1期102卷 97-106页

作者： Aiello, G. Cacciato, M. Scarcella, G. Scelba, G. Gennaro, F. Aiello, N. DIEEI Univ Catania Catania Italy STMicroelectronics Syst Res & Applicat Catania Italy

The paper deals with the accomplishment of a FPGA-based dynamic model of a three-phase Vienna rectifier controlled in order to feature unity power factor operations. Such a model has been developed for the Hardware In the Loop (HIL) implementation of a test rig in which the power converter is replaced with an embedded system using a FPGA board. The proposed approach has been fostered mainly to test different converter control algorithms in a fast and safe way. Such solution is based on a software platform environment with a high-level abstraction that ensures a good trade-off between accuracy and hardware resources, also allowing a fast prototyping procedure. The results obtained by the HIL implementation have been compared with those of a fully hardware experimental rig, confirming a very good agreement in terms of accuracy and dynamic behavior.

关键词： PWM rectifiers Grid-connected application field programmable gate array Hardware in the loop Power factor correction Power converters modeling

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