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检索条件"主题词=Field Programmable Gate array"
1339 条 记 录,以下是341-350 订阅
排序:
A high throughput hardware architecture for deblocking filter in HEVC
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SIGNAL PROCESSING-IMAGE COMMUNICATION 2022年 100卷 116517-116517页
作者: Kopperundevi, P. Prakash, Matcha Surya Ahamed, Shaik Rafi Natl Inst Technol Calicut Calicut Kerala India Indian Inst Technol Guwahati Gauhati India
This paper presents a high throughput hardware architecture for deblocking filter in high efficiency video coding (H.265/HEVC) standard. The architecture uses an efficient hybrid pipelining and parallel processing tec... 详细信息
来源: 评论
A Disturbance Suppression Zeroing Neural Network for Robust Synchronization of Chaotic Systems and Its FPGA Implementation
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INTERNATIONAL JOURNAL OF BIFURCATION AND CHAOS 2022年 第14期32卷 2250210-2250210页
作者: Chen, Weijie Jin, Jie Chen, Chaoyang Yu, Fei Wang, Chunhua Hunan Univ Sci & Technol Sch Informat & Elect Engn Xiangtan 411201 Peoples R China Changsha Univ Sci & Technol Sch Comp & Commun Engn Changsha 410114 Peoples R China Hunan Univ Sch Comp Sci & Elect Engn Changsha 410082 Peoples R China
The synchronization of chaotic systems plays an extremely imperative and fundamental role in the fields of science and engineering. Notably, various external noise disturbances have a great impact on the synchronizati... 详细信息
来源: 评论
Performance comparison of CNN, QNN and BNN deep neural networks for real-time object detection using ZYNQ FPGA node
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MICROELECTRONICS JOURNAL 2022年 119卷 105319-105319页
作者: Mani, V. R. S. Saravanaselvan, A. Arumugam, N. Natl Engn Coll Dept Elect & Commun Engn Kovilpatti Tamil Nadu India
In this manuscript, previously trained Convolutional neural network (CNN), Quantum Neural Network (QNN), and Binarized Neural Network (BNN) models performed employing Tensor Flow's Application Programming Interfac... 详细信息
来源: 评论
Scalable Control System Based on Matrix of Controllers – Preliminary Results
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IFAC-PapersOnLine 2022年 第4期55卷 183-188页
作者: Chaber Patryk Wojtulewicz Andrzej Warsaw University of Technology Institute of Control and Computation Engineering ul. Nowowiejska 15/19 00-665 Warsaw Poland
The work aims to develop an original software and hardware structure for the regulation of fast dynamic processes. The structure will allow simultaneous predictive regulation of many processes with independent dynamic... 详细信息
来源: 评论
FPGA implementation of adaptive p-norm filter for non-stationary power signal parameter estimation
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IET SCIENCE MEASUREMENT & TECHNOLOGY 2020年 第2期14卷 206-219页
作者: Nanda, Sarita Pattnaik, Ansuman Dash, Pradipta Kishore KIIT Univ Sch Elect Engn Bhubaneswar Odisha India Siksha O Anusandhan Univ Multidisciplinary Res Cell Bhubaneswar Odisha India
A p-norm extreme learning machine (ELM) based on sparsity constraint is presented in this study for tracking of fundamental frequency, harmonic and dc in current power signals which finds application in phasor measure... 详细信息
来源: 评论
FPGAN: An FPGA Accelerator for Graph Attention Networks With Software and Hardware Co-Optimization
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IEEE ACCESS 2020年 8卷 171608-171620页
作者: Yan, Weian Tong, Weiqin Zhi, Xiaoli Shanghai Univ Sch Comp Engn & Sci Shanghai 200444 Peoples R China Shanghai Univ Shanghai Inst Adv Commun & Data Sci Shanghai 200444 Peoples R China
The Graph Attention Networks (GATs) exhibit outstanding performance in multiple authoritative node classification benchmark tests (including transductive and inductive). The purpose of this research is to implement an... 详细信息
来源: 评论
HopliteRT*: Real-Time NoC for FPGA
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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2020年 第11期39卷 3650-3661页
作者: Gonzalez, Yilian Ribot Nelissen, Geoffrey Polytech Inst Porto ISEP CISTER Res Ctr P-4200465 Porto Portugal Eindhoven Univ Technol Dept Math & Comp Sci NL-5612 AZ Eindhoven Netherlands
With the increasing number of computation nodes integrated in multi and many-core platforms, network-on-chips (NoCs) emerged as a new communication medium in systems-on-chips (SoCs). HopliteRT is a new NoC design that... 详细信息
来源: 评论
FPGA implementation of NN based LMS-LMF control algorithm in DSTATCOM for power quality improvement
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CONTROL ENGINEERING PRACTICE 2020年 98卷 104378-000页
作者: Malathi, S. Jayachandran, J. SASTRA Deemed Univ Dept Elect & Elect Engn Thanjavur 613401 Tamil Nadu India
Neural Network (NN) based Least Mean Square (LMS)-Least Mean Fourth (LMF) control technique is developed and implemented in field programmable gate array (FPGA) for Shunt Active Power Filter (SAPF) to enhance Power Qu... 详细信息
来源: 评论
An energy efficient FPGA partial reconfiguration based micro-architectural technique for IoT applications
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MICROPROCESSORS AND MICROSYSTEMS 2020年 第0期73卷 102966-000页
作者: Kiat, Wei-Pau Mok, Kai-Ming Lee, Wai-Kong Goh, Hock-Guan Achar, Ramachandra Univ Tunku Abdul Rahman Fac Informat & Commun Technol Kampar Perak Malaysia Carleton Univ Dept Elect Ottawa ON K1S 5B6 Canada
Low power consumption and high computational performance are two important processor design goals for IoT applications. Achieving both design goals in one processor architecture is challenging due to their conflicting... 详细信息
来源: 评论
Real-time emulation of a three-phase Vienna rectifier with DC voltage control and power factor correction
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ELECTRICAL ENGINEERING 2020年 第1期102卷 97-106页
作者: Aiello, G. Cacciato, M. Scarcella, G. Scelba, G. Gennaro, F. Aiello, N. DIEEI Univ Catania Catania Italy STMicroelectronics Syst Res & Applicat Catania Italy
The paper deals with the accomplishment of a FPGA-based dynamic model of a three-phase Vienna rectifier controlled in order to feature unity power factor operations. Such a model has been developed for the Hardware In... 详细信息
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