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An FPGA Implementation of Chaotic and Edge Enhanced Error Diffusion

IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2010年第3期56卷 1755-1762页

作者： Su, Chung-Yen Sie, You-Lin Natl Taiwan Normal Univ Dept Appl Elect Technol Taipei 10612 Taiwan

Digital halftoning plays a central role in getting more observable grey-levels for either the innovative electronic paper or other less level devices. The hardware implementation of digital halftoning is, however, seldom fully explored. In this paper, we propose a novel implementation of digital halftoning by means of error diffusion. The proposed scheme not only can perform a new method called chaotic and edge enhanced error diffusion, but also can be reduced to perform the conventional Floyd-Steinberg error diffusion. Best of all, our new scheme can produce halftone images with lower worm-like artifacts and sharper image edges. This scheme is mainly composed of four components: gradient-based edge detection, chaotic threshold generation, edge enhanced quantization, and error diffusion. Each circuit design of the four components is illustrated for the first time. Besides, we demonstrate the hardware performance of our scheme by using a field programmable gate array (FPGA) chip to offer possibly further applications(1).

关键词： Error diffusion digital halftoning edge enhancement field programmable gate array electronic paper

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Deep Convolutional Stack Autoencoder of Process Adaptive VMD Data With Robust Multikernel RVFLN for Power Quality Events Recognition

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2021年 70卷 1-12页

作者： Sahani, Mrutyunjaya Dash, Pradipta Kishore Siksha O Anusandhan Deemed To Be Univ Multidisciplinary Res Cell Bhubaneswar 751030 Odisha India

In this article, an improved particle swarm optimization (PSO)-based variational mode decomposition (VMD) is proposed to compute the most informative band-limited intrinsic mode function (BLIMF) of highly nonstationary single as well as combined power quality events (PQEs). A novel reduced deep convolutional neural network (RDCNN) embedded with stack autoencoder, that is, RDCSAE structure is introduced to extract the most discriminative unsupervised feature data by importing the selected BLIMF of parameter-adaptive VMD (PAVMD) algorithm. A supervised robust multikernel random vector functional link network (RMRVFLN) method is proposed to further train the unsupervised features combined with the deep convoluted Fourier privileged data for the recognition of complex PQEs accurately. Automatic computation of minimum overlapped descriptive features, unified complex feature learning framework, outstanding recognition accuracy, robust antinoise performance, and quick PQEs recognition time prove the superiority of the proposed PAVMD-RDCSAE-RMRVFLN method over RDCNN, PAVMD-RDCNN, PAVMD-RDCSAE, PAVMD-RDCNN-RMRVFLN, and PAVMD-RDCSAE-MRVFLN methods. Finally, the architecture of the proposed method is designed, implemented, and tested in a fast digital field-programmable gate array (FPGA) embedded processor to validate the feasibility, practicability, and performances for the online PQEs monitoring.

关键词： Autoencoder deep convolutional neural network (DCNN) field programmable gate array parameter adaptive variational mode decomposition (PAVMD) power quality analysis random vector functional link network

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Ripple-reduced model predictive direct power control for active front-end power converters with extended switching vectors and time-optimised control

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IET POWER ELECTRONICS 2016年第9期9卷 1914-1923页

作者： Fang, Hui Zhang, Zhenbin Feng, Xiaoyun Kennel, Ralph Southwest Jiaotong Univ Sch Elect Engn Chengdu Sichuan Peoples R China Tech Univ Munich Sch Elect Engn & Informat Munich Germany

Model predictive control (MPC) is an attractive technique for power electronics and drives. It requires no extra modulators and considers the non-linear nature of the power converter, so remarkable control performance can be achieved. However, since the conventional MPC scheme uses only one switching state during the whole control interval, ripples of the control variables are more evident than that of the classical modulator based techniques. This study proposed a ripple-reduced model predictive direct power control (RR-MPDPC) scheme for the grid-tied active front end using a fully field programmable gate array-based platform. The novelty of the proposed RR-MPDPC is that through extended switching vectors and time-optimised control, more freedoms and precise tracking possibility are realised in the predictive controller. The proposed control scheme is compared with the conventional MPDPC and the recently reported duty optimal MPDPC scheme (DutyOpt-MPDPC) through experimental data. Experimental results confirm that better performance is achieved using the proposed RR-MPDPC scheme.

关键词： predictive control power control power convertors power electronics electric drives field programmable gate arrays optimal control modulators ripple-reduced model predictive direct power control RR-MPDPC active front-end power converters extended switching vectors time-optimised control power electronics power drives switching state control variables classical modulator grid-tied active front end field programmable gate array predictive controller duty optimal MPDPC scheme DutyOpt-MPDPC

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Predictive current control of distribution static compensator for load compensation in distribution system

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IET GENERATION TRANSMISSION & DISTRIBUTION 2016年第10期10卷 2410-2423页

作者： Venkatraman, Kandadai Selvan, Manickavasagam Parvathy Moorthi, Sridharan Natl Inst Technol Dept Elect & Elect Engn Power Converters Res Lab Tiruchirappalli 620015 Tamil Nadu India Natl Inst Technol Dept Elect & Elect Engn VLSI Syst Res Lab Tiruchirappalli 620015 Tamil Nadu India

Predictive control is an emerging alternative in the control of power converters because of its potential for achieving fast transient response and increased control accuracy. Research on this topic has increased in recent years owing to the availability of high speed digital controllers that can be used for the control of power electronic systems. This study proposes a predictive current control scheme for an improved topology of distribution static compensator (DSTATCOM) intended for load compensation. The proposed strategy derives the converter switching pulses using a cost function that defines the desired system behaviour. An improved DSTATCOM topology employing predictive current control algorithm tracks reference current effectively and makes source current sinusoidal and also in-phase with voltage at the point of common coupling in both steady state and transient conditions. In addition, this scheme does not require any modulation technique. The control scheme has been implemented using field programmable gate array. Simulation and experimentation have been carried out to verify and validate the performance of the proposed scheme and the results are reported in this study.

关键词： predictive control electric current control power distribution control static VAr compensators power convertors field programmable gate arrays predictive current control distribution static compensator load compensation distribution system DSTATCOM converter switching pulses point of common coupling field programmable gate array

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Analysis of THD and output voltage performance for cascaded multilevel inverter using carrier pulse width modulation techniques

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IET POWER ELECTRONICS 2011年第8期4卷 951-958页

作者： Palanivel, P. Dash, S. S. SRM Univ EEE Madras 603203 Tamil Nadu India

Multilevel inverter is used in applications that need high voltage and high current. The topologies of multilevel inverter have several advantages such as lower total harmonic distortion (THD), lower electro magnetic interference (EMI) generation, high output voltage. The main feature of multilevel inverter is the ability to reduce the voltage stress on each power device due to the utilisation of multilevel on the DC bus. The advent of multilevel inverter topologies has caused variety of pulse width modulation strategies. In this paper, various carrier pulse width modulation techniques are proposed, which can minimise the total harmonic distortion and enhances the output voltages from five level inverter. Three methodologies adopting the constant switching frequency (CSF), variable switching frequency (VSF), and phase shifted pulse width modulation (PSPWM) concepts are proposed in this paper. The above methodologies divided into two techniques like subharmonic pulse width modulation which minimises total harmonic distortion and switching frequency optimal pulse width modulation which enhances the output voltages. field programmable gate array (FPGA) has been chosen to implement the pulse width modulation due its fast proto typing, simple hardware and software design. The simulation and experimental results are presented.

关键词： Electromagnetic compatibility and interference field programmable gate array FPGA output voltage performance Logic and switching circuits Logic circuits switching convertors carrier pulse width modulation electromagnetic interference harmonic distortion PWM invertors variable switching frequency field programmable gate arrays constant switching frequency cascaded multilevel inverter subharmonic pulse width modulation total harmonic distortion voltage stress electromagnetic interference generation Power electronics, supply and supervisory circuits

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Hybrid statistical and recurrent neural network architecture implementation in FPGA device used for severe acute respiratory syndrome coronavirus detector

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JOURNAL OF INTELLIGENT & FUZZY SYSTEMS 2023年第6期44卷 8803-8816页

作者： Senthilkumar, V. M. Thenmozhi, S. Kumudavalli, M. V. Yedukondalu, U. Vivekanandha Coll Engn Women Autonomous Dept ECE Namakkal Tamilnadu India Dayananda Sagar Coll Engn Dept ECE Bangalore Karnataka India Dayananda Sagar Coll Arts Sci & Commerce Dept Comp Applicat Bangalore Karnataka India MVR Coll Engn Technol Autonomous Dept ECE Paritala Andhra Pradesh India

The Severe Acute Respiratory Syndrome (SARS) are caused by the strain of the corona virus causes cold and influenza. In recent years, the covid pandemic spread throughout the world killing millions of people. The fatality rate has increased and it also leads to pneumonia for breathing problems. Several methods like wavelet filter banks, time series methods, Neural networkswas developed for the diagnosis of severe acute respiratory syndrome coronavirus, still the accuracy can be improved. Less works is carried out for hardware implementation for syndrome detectors. This proposed work represents the FPGA (field programmable gate array) implementation of the hybrid method using Convolutional Recurrent neural network and Independent Components Analysis (ICA). The architecture extracts the ccomplex features from ECG (Electrocardiogram) samples. The hybrid Statistical and Recurrent Neural Network (RNN) Architecture implementation in a real time hardware detects the Severe Acute Respiratory Syndrome presented. The proposed method can be implemented in MATLAB, Embedded and DSP (Digital Signal Processor). But, the FPGAs consume less power computationally efficient. Since, ICA is an efficient method due to its blind source separation property accumulate the extraction of features accurate described. The mathematical model for the analysis of ECG signal using RNN is analyzed and based on that the proposed model is selected. On investigation the hybrid method using the statistical and neural network model is efficient in the analysis of biomedical signal especially ECG. The proposed ICA based RNN model is mathematically evaluated and tested with real time data. For implementation, Quartus software is used for effectiveness of the proposed model.

关键词： field programmable gate array recurrent neural network independent component analysis electrocardiogram severe acute respiratory syndrome

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FPGA-PLC-based multi-channel position measurement system

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ISA TRANSACTIONS 2021年 115卷 234-249页

作者： Patel, Dhruv M. Shah, Ankit K. Gujarat Technol Univ Instrumentat & Control Engn Ahmadabad Gujarat India Gujarat Technol Univ LD Coll Engn Instrumentat & Control Engn Dept Ahmadabad 380015 Gujarat India Gujarat Technol Univ Instrumentat & Control Engn Ahmadabad Gujarat India Sardar Vallabhbhai Patel Inst Technol SVIT Instrumentat & Control Engn Dept Vasad 388306 Gujarat India

The existing programmable Logic Controller (PLC) based on microprocessors (mu p) or micro-controllers (mu c) are commonly used in the industry for various instrumentation and control applications. PLC exhibits limitations such as less flexibility, poor scanning time, slower speed, and degraded response for high-speed industrial applications due to its fixed hardware and serial execution mechanism. A new field programmable gate array (FPGA) based PLC multi-channel High Speed Counter (HSC) module has been proposed, enhancing performance and flexibility compared to the existing PLC-HSC module. The proposed FPGA-PLC-HSC module has a 2-phase 2-Input counter with resolutions of 1X, 2X, and 4X which improve performance in terms of accuracy for position speed, and direction measurement applications. The FPGA-PLC-HSC module is implemented with the feedback node method and the shift register method inside LabVIEW FPGA along with device utilization. The simulation results show that the FPGA-PLC-HSC module has faster scanning time, good linearity, better resolution, maximum supporting input frequency, and counting frequency. For experimental purposes, an optical encoder M110960 (E8P 512 118 S D M B) with a signal conditioning circuit is connected to the NI-myRIO-1900 FPGA platform. The experimental results point out that the proposed FPGA-PLC-HSC module offers faster scanning time, better accuracy and linearity in 1X, 2X, and 4X resolution. (C) 2021 ISA. Published by Elsevier Ltd. All rights reserved.

关键词： programmable Logic Controller High speed phase counters field programmable gate array Position measurement

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Center Frequency Tracking Scheme to Optimize Pulse-Echo Response of Ultrasonic A-mode Scanner Circuit System

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IEEE ACCESS 2023年 11卷 14524-14532页

作者： Ko, Doo-Hyeon Lee, Young-Chan Um, Ji-Yong Kumoh Natl Inst Technol Dept Med IT Convergence Engn Gumi 39253 South Korea

This paper proposes a center frequency tracking scheme to optimize a pulse-echo response of ultrasonic A-mode scanner. A pulse-echo response of A-mode scanner represents an overall energy conversion characteristic from an actuation to an acquisition. A center frequency for optimized pulse-echo response can be varied depending on an actuation voltage, an acoustic medium, etc. Most of previous frequency tracking methods have focused on high-power continuous actuation applications, and have relied on a monitoring of phase difference between actuating voltage and current with auxiliary sensors. This work focuses on a monitoring of a peak envelope of echo without additional sensors. We employ a momentum based gradient ascent algorithm along with a finite state machine to track an optimum center frequency so that a peak envelope of echo becomes the maximum value. The proposed frequency tracking scheme was implemented on a field programmable gate array for real-time operation. We performed repetitive measurements to verify consistent frequency tracking performances for different acoustic mediums. The A-mode scanner adaptively tracked corresponding center frequencies for each of mediums within an average error of 61.7 kHz. When the A-mode scanner was in a steady state, an increment of signal-to-noise ratio (SNR) of echo was 7.4 dB, and an axial resolution was improved by 32.5 %.

关键词： Acoustics Transducers Frequency response field programmable gate arrays Ultrasonic imaging Monitoring Automata Center frequency tracking A-mode ultrasound gradient-ascent algorithm momentum optimization finite state machine field programmable gate array A-mode scanner circuit system

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Novel intelligent real-time position tracking system using FPGA and fuzzy logic

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ISA TRANSACTIONS 2014年第2期53卷 402-414页

作者： Soares dos Santos, Marco P. Ferreira, J. A. F. Univ Aveiro Dept Mech Engn Ctr Mech Technol & Automat TEMA P-3810193 Aveiro Portugal

The main aim of this paper is to test if FPGAs are able to achieve better position tracking performance than software-based soft real-time platforms. For comparison purposes, the same controller design was implemented in these architectures. A Multi-state Fuzzy Logic controller (FLC) was implemented both in a Xilinx (R) Virtex-II FPGA (XC2v1000) and in a soft real-time platform NI CompactRIO (R)-9002. The same sampling time was used. The comparative tests were conducted using a servo-pneumatic actuation system. Steady-state errors lower than 4 mu m were reached for an arbitrary vertical positioning of a 6.2 kg mass when the controller was embedded into the FPGA platform. Performance gains up to 16 times in the steady-state error, up to 27 times in the overshoot and up to 19.5 times in the settling time were achieved by using the FPGA-based controller over the software-based FLC controller. (C) 2013 ISA. Published by Elsevier Ltd. All rights reserved.

关键词： Automation field programmable gate array Fuzzy logic Real-time control systems Pneumatics Position tracking Control

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Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips

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IEEE ACCESS 2019年 7卷 103938-103947页

作者： Guerrieri, Andrea Kashani-Akhavan, Sahand Asiatic, Mikhail Ienne, Paolo Ecole Polytech Fed Lausanne Architecture Lab CH-1015 Lausanne Switzerland Ecole Polytech Fed Lausanne Very Large Scale Comp Lab VLSC CH-1015 Lausanne Switzerland Ecole Polytech Fed Lausanne Sch Comp & Commun Sci CH-1015 Lausanne Switzerland

Due to increased embedded processing requirements, modern SoCs are becoming heterogeneous computing platforms by combining traditional processing units with custom reconfigurable hardware accelerators (HAs) on an FPGA fabric. However, efficiently managing such HAs in an embedded Linux environment involves handling Linux kernel source code and creating custom device drivers specific to a target platform, therefore negatively impacting development costs, portability and time-to-market. To address this issue, we present LEOSoC, a snap-on user-space manager for dynamically reconfigurable SoCs. Using LEOSoC does not require any specific version of the Linux kernel, nor to rebuild a custom driver for each new kernel *** consists of a base hardware system and a software layer which run on SoCs from various vendors. The system identifies the SoC on which it is running and auto-adapts its communication channels to the HAs accordingly. Furthermore, LEOSoC allows applications to partially or completely change the structure of the HAs at runtime without rebooting the system by leveraging the underlying SoC support for dynamic full/partial FPGA reconfiguration. The system has been tested on multiple commercial off the shelf (COTS) boards from different vendors, each one running different versions of Linux, therefore proving the real portability and usability of LEOSoC in a custom industrial design. Finally, we use a cloud detection algorithm for multispectral image processing as a showcase for LEOSoC's capabilities and performance.

关键词： Adaptive systems field programmable gate array multithreading reconfigurable architectures system-on-chip

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