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Jitter-Quantizing-Based TRNG Robust Against PVT Variations

IEEE ACCESS 2020年 8卷 108482-108490页

作者： Lu, Yingchun Liang, Huaguo Yao, Liang Wang, Xinyu Qi, Haochen Yi, Maoxiang Jiang, Cuiyun Huang, Zhengfeng Hefei Univ Technol Sch Elect Sci & Appl Phys Hefei 230009 Peoples R China Hefei Univ Technol Sch Math Hefei 230009 Peoples R China

Security is critical to the growing popularity of the Internet of Things(IoT), and true random number generator (TRNG) plays an increasingly important role in information security systems. Conventional TRNGs use natural physical stochastic processes including thermal noise, chaos-based circuit, and so on to generate random numbers. These analog circuits based TRNG structures often consume excessive hardware resources. Meanwhile, it is difficult to incorporate them into digital system. In this paper, a novel all-digital true random number generator in SRAM-based FPGAs is proposed by using Vernier technique that precisely quantize random edge jitter. The proposed TRNG design is implemented on Xilinx Virtex-6 XC6VLX240T-1FF1156 FPGA and shows a high quality of randomness which has passed the NIST test suite with relatively high p-values, achieves a high throughput of 127 Mbps with occupying 32 slices. Experimental results show a good tolerance to bias phenomenon induced by process, voltage, and temperature variations.

关键词： True random number generator Vernier technique field programmable gate array high throughput

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Speed optimal FPGA implementation of the encryption algorithms for telecom applications

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MICROPROCESSORS AND MICROSYSTEMS 2020年 79卷 103324-103324页

作者： Sikka, Prateek Asati, Abhijit R. Shekhar, Chandra Birla Inst Technol & Sci Dept EEE Pilani Rajasthan India Birla Inst Technol & Sci Dept EEE Vidya Vihar Campus Pilani Rajasthan India

The last two decades have seen a revolution in telecom technology with the evolution of three wireless mobile communication standards, namely, GPRS to 3G, 3G to 4G, and 4G to 5G. 5G offers faster download speeds and enables high connectivity between devices such as mobile phones, displays, smart homes, and smart cars because of its high reliability and high bandwidths (up to 10 Gbps). However, at the same time, data and personal information are also more susceptible to theft because of the high connectivity. Such threats can be addressed using electronic data encryption using the advanced encryption standard (AES). Because of their reconfigurable and parallel architectures, field-programmable gate arrays (FPGAs) are getting popular in VLSI design flows to enable the pre-silicon validation of designs faster data rates in real-time. FPGAs also serve as platforms for software development in the pre-silicon environment owing to their faster speeds. The design community is also heavily relying on High-Level Synthesis (HLS) tools in VLSI design flows. HLS platforms enable the new designs to improve the process with sustained authentication between two analytical selections from conventional functional specifications. We propose a high-throughput FPGA implementation based on high-level Synthesis for the AES algorithm. The implementation uses a 128-bit key and is highly suited for telecom applications such as 5G. Researchers have developed and tested the setup and then used the Vivado HLS tool to evaluate various HLS guidelines as per the implementation. The generated Verilog RTL was verified and implemented on Xilinx Kintex 7 and Virtex 6 FPGAs. Since using the same resources, we have seen significant results than existing methods achieved by individual investigators. We have also verified the design for functionality by checking the ciphertext output from our design against a reference design output for the same input plaintext.

关键词： Advanced encryption standard field programmable gate array Register transfer level Telecom Xilinx high-level synthesis

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MsBV: A Memory Compression Scheme for Bit-Vector-Based Classification Lookup Tables

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IEEE ACCESS 2020年 8卷 38673-38681页

作者： Shi, Zilin Yang, Hui Li, Junnan Li, Chenglong Li, Tao Wang, Baosheng Natl Univ Def Technol Coll Comp Sci & Technol Changsha 410072 Peoples R China

Packet classification is widely used in Software-Defined Networking (SDN). At present, packet classification is mainly implemented by software, such as OpenvSwitch, which has the disadvantage of low performance. On the field programmable gate array (FPGA) platform, FPGA has the advantages of reconfigurability and high processing performance. The current work proposes the FPGA-based Bit-Vector algorithms in packet classification, which has the advantages of determining latency and high throughput. In the Bit-Vector-based algorithms, stringent memory resources in FPGA are wasted to store relatively useless wildcards because there are plenty of wildcards in the rules. A bit-vector-based memory compression scheme named Memory-shared Bit-Vector (MsBV) is proposed. MsBV adopts a memory-shared homogeneous two-dimensional pipeline architecture, and it can reduce memory consumption and ensure the correctness of packet classification. In MsBV, we reduce memory consumption better by rearranging the bit matrix. The experimental results show that MsBV saves about 43.69& x0025;memory resources, 57.53& x0025;the number of ALUTs, and 37.59& x0025;the number of Registers compared to StrideBV of 100K OpenFlow rules.

关键词： Pipelines Memory management field programmable gate arrays Heuristic algorithms Decision trees Engines Standards Bit-vector packet classification memory compression shared memory field programmable gate array

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MoniThor: A complete monitoring tool for machining data acquisition based on FPGA programming

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SOFTWAREX 2020年 11卷

作者： Urbikain, G. de Lacalle, L. N. Lopez Univ Basque Country Dept Mech Engn High Performance Mfg Grp Plaza Europa 1 Donostia San Sebastian 20018 Basque Country Spain Univ Basque Country Dept Mech Engn High Performance Mfg Grp Plaza Ingn Torres Quevedo 1 Bilbao 48013 Basque Country Spain

Today requirements by machine-tool users point towards knowing more about the machining processes. In a globalized and competitive market as manufacturing is, future engineers will be urged to develop transversal skills on diverse science domains such as Mechanics, Mechatronics or Electrics. Monitoring of machining processes allows determining possible errors and deviations from the desirable conditions (aged machine-tools, bad machining conditions, most energetically / cost-effective conditions) as well as saving historical data of the workpieces manufactured by the same machine. In order to strengthen students' skills, the Department of Mechanical Engineering of the University of the Basque Country (UPV/EHU) developed a monitoring tool using Labview (c) programming. The application, built from the combination of reconfigurable Input/Output (I/O) architecture and field programmable gate arrays (FPGA), was applied to practical classes in the machine shop to improve students' skills. (C) 2019 The Authors. Published by Elsevier B.V.

关键词： Monitoring tool Machining data field programmable gate array

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Design, implementation, and estimation of MFCV for 4-different position of human body using FPGA

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MICROELECTRONICS JOURNAL 2020年 105卷 104890-104890页

作者： Sudharsan, R. Raja Deny, J. Muthukumaran, E. Selvi, S. Chitra Kalasalingam Acad Res & Educ Dept Elect & Commun Engn Krishnan Koil Virudhunagar Dt India Dr BR Ambedkar Inst Technol Dept Elect & Commun Engn Port Blair Andaman & Nicob India Univ Coll Engn Dept Elect & Elect Engn Thirukuvalai Nagappattinam India

The motivation behind this article is to demonstrate the precision and dependability of a field programmable gate array-based implementation of muscle fibre conduction velocity (MFCV) in customary unique constrictions. The framework, leveraging the DSP unit, acquires the bio signals from four different positions of the human body, including Radial Nerve, Ulnar nerve, Auxiliary Nerve, Median nerve. The information derived through Surface Electromyogram (EMG) Electrodes is depicted as a dynamic bitstreams of the signal. The latest bitstreams are subjected to an algorithm. The subjection corresponds to the correlation of the signals from similar muscle nerves, obtained through the EMG electrodes. The whole calculation framework completely works progressively on the Altera Cyclone-V FPGA. This method is better than finding the signal dependence using a silicon resonator due to its cost and tedious design of the sensors. The myoelectric (Electromyographic) signal is recorded by the electrodes set on the four different locations associated with 1550 unique contractions. The in-vivo estimations illustrate that below the equivalent trial states, in 10 test days, the framework uncovers an MFCV mean estimation of 6.60 (+/-) 0.42 m/s for Median nerve Position, 6.43 (+/-) 0.33 m/s for Ulnar Nerve Position, 6.54 (+/-) 0.41 m/s for Radial nerve Position and 7.21 (+/-) 0.49 m/s for Auxiliary Nerve Position. The values evidence decent dependability of the estimations in an eternal application. The core part of the device being MFCV estimation, upon empirical evaluations with clinical values, shows an accuracy of 97%.

关键词： Muscle fibre conduction velocity (MFCV) Electromyogram (EMG) electrodes field programmable gate array Silicon resonator

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An Area Efficient and Low Power Consumption of Run Time Digital System Based on Dynamic Partial Reconfiguration

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INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING 2020年第3期48卷 431-446页

作者： Ram, R. Saravana Saminathan, A. Gopi Prakash, S. Arun Anna Univ Univ Coll Engn Dindigul Dept Elect & Commun Engn Dindigul Tamil Nadu India NPR Coll Engn & Technol Dept Elect & Commun Engn Natham Tamil Nadu India Anna Univ Dept Elect & Commun Engn Univ Coll Engn Ramanathapuram Ramanathapuram Tamil Nadu India

Digital signal processing besides multimedia applications needs plenty of data, real-time processing capacity, and high computational power. Thus, adaptable architectures with run-time reconfiguration abilities have gotten expanded consideration. Basically, Reconfiguration computing is going towards advancing the application adaptability at runtime. A reconfigurable structure can be attained by working up the strategy aimed at configuring an array of programmable logic reprogramming. field programmable gate arrays (FPGAs) is made with the intention of reconfiguring the array system with interconnects as well as the configuration of logic blocks. To implement a high-performance FPGA device and also to enhance, the given paper proposes a proficient design strategy. The proposed strategy count upon the employment of dynamic partial reconfiguration (DPR) to drive from one mode then onto the next utilizing time-multiplexing on the same chip region. Furthermore, reconfigure modules to spare considerable area and enable the low-cost FPGAs usage. In the given work, reconfigurations of the modules accompanied by the memory are finished. The DPR is implemented betwixt these modes to shift from one mode then onto the next. The proposed method helps in diverse applications with various demands and also attains high performance, power consumption together with throughput. The proposed work gives improved performance with fewer powers and less area utilization which is illustrated by the Experimental outcomes.

关键词： Digital signal processing Reconfiguration computing field programmable gate array Dynamic partial reconfiguration

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Investigating hardware acceleration for simulation of CFD quantum circuits

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FRONTIERS IN MECHANICAL ENGINEERING-SWITZERLAND 2022年 8卷

作者： Moawad, Youssef Vanderbauwhede, Wim Steijl, Rene Univ Glasgow Glasgow Scotland

Among the many computational models for quantum computing, the Quantum Circuit Model is the most well-known and used model for interacting with current quantum hardware. The practical implementation of quantum computers is a very active research field. Despite this progress, access to physical quantum computers remains relatively limited. Furthermore, the existing machines are susceptible to random errors due to quantum decoherence, as well as being limited in number of qubits, connectivity and built-in error correction. Simulation on classical hardware is therefore essential to allow quantum algorithm researchers to test and validate new algorithms in a simulated-error environment. Computing systems are becoming increasingly heterogeneous, using a variety of hardware accelerators to speed up computational tasks. One such type of accelerators, field programmable gate arrays (FPGAs), are reconfigurable circuits that can be programmed using standardized high-level programming models such as OpenCL and SYCL. FPGAs allow to create specialized highly-parallel circuits capable of mimicking the quantum parallelism properties of quantum gates, in particular for the class of quantum algorithms where many different computations can be performed concurrently or as part of a deep pipeline. They also benefit from very high internal memory bandwidth. This paper focuses on the analysis of quantum algorithms for applications in computational fluid dynamics. In this work we introduce novel quantum-circuit implementations of model lattice-based formulations for fluid dynamics, specifically the D1Q3 model using quantum computational basis encoding, as well as, efficient simulation of the circuits using FPGAs. This work forms a step toward quantum circuit formulation of the Lattice Boltzmann Method (LBM). For the quantum circuits implementing the nonlinear equilibrium distribution function in the D1Q3 lattice model, it is shown how circuit transformations can be introduced that facilit

关键词： quantum circuit simulation Lattice Boltzmann Method (LBM) FPGA field programmable gate array quantum circuit transformation hardware acceleration

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Low-Overhead Compressibility Prediction for High-Performance Lossless Data Compression

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IEEE ACCESS 2020年 8卷 37105-37123页

作者： Kim, Youngil Choi, Seungdo Lee, Daeyong Jeong, Joonyong Kwak, Jaewook Lee, Jungkeol Lee, Gyeongyong Lee, Sangjin Park, Kibin Jeong, Jinwoo Kexin, Wang Song, Yong Ho Hanyang Univ Dept Elect & Comp Engn Seoul 15588 South Korea Samsung Elect Co Ltd Hwaseong 18448 South Korea

As big data has evolved over the past few years, a lack of storage space and I/O bandwidth has become one of the most important challenges to overcome. To mitigate these problems, data compression schemes reduce the amount of data to be stored and transmitted at the cost of additional CPU overhead. Many researchers have attempted to reduce the computational load imposed on the CPU by data compression using specialized hardware. However, space savings through data compression often comes from only a small portion of data. Therefore, compressing all data, regardless of data compressibility, can waste computational resources. Our work aims to decrease the cost of data compression by introducing a selective data compression scheme based on data compressibility prediction. The proposed compressibility prediction method provides more fine-grained selectivity for combinational compression. Additionally, our method reduces the amount of resources consumed by the compressibility predictor, enabling selective compression at a low cost. To verify the proposed scheme, we implemented a DEFLATE compression system on a field-programmable gate array platform. Experimental results demonstrate that the proposed scheme improves compression throughput by 34.15% with a negligible decrease in compression ratio.

关键词： Data compression Huffman coding LZ77 encoding accelerator architecture field programmable gate array estimation compressibility

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A Primer on Software Defined Radios

INFOCOMMUNICATIONS JOURNAL

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INFOCOMMUNICATIONS JOURNAL 2022年第3期14卷 16-27页

作者： Popescu, Dimitrie C. Vida, Rolland Old Dominion Univ Dept Elect & Comp Engn Norfolk VA 23529 USA Budapest Univ Technol & Econ Fac Elect Engn & Informat Dept Telecommun & Media Informat Magyar Tudosok Korutja 2 H-1117 Budapest Hungary

The commercial success of cellular phone systems during the late 1980s and early 1990 years heralded the wireless revolution that became apparent at the turn of the 21st century and has led the modern society to a highly interconnected world where ubiquitous connectivity and mobility are enabled by powerful wireless terminals. Software defined radio (SDR) technology has played a major role in accelerating the pace at which wireless capabilities have advanced, in particular over the past 15 years, and SDRs are now at the core of modern wireless communication systems. In this paper we give an overview of SDRs that includes a discussion of drivers and technologies that have contributed to their continuous advancement, and presents the theory needed to understand the architecture and operation of current SDRs. We also review the choices for SDR platforms and the programming options that are currently available for SDR research, development, and teaching, and present case studies illustrating SDR use. Our hope is that the paper will be useful as a reference to wireless researchers and developers working in the industry or in academic settings on further advancing and refining the capabilities of wireless systems.

关键词： Software defined radio field programmable gate array digital signal processing wireless communication networks

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Design and FPGA implementation of lattice wave digital notch filter with minimal transient duration

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IET SIGNAL PROCESSING 2020年第7期14卷 440-447页

作者： Sharma, Abhay Kumar Rawat, Tarun Agrawal, Anjali Univ Delhi Fac Technol New Delhi India

In this study, the design and field-programmable gate array (FPGA) implementation of the digital notch filter with the lattice wave digital filter (LWDF) structure is presented. For reducing the initial signal transient, the variable notch bandwidth filter is designed. During the initial samples, the notch filter has a wide bandwidth in order to diminish signal transient. As time moves forward, the notch bandwidth reduces to attain the possible minimum width. This results in minimised transient duration notch filter with a sufficiently high-quality factor. Previously, the IIR structure has been used for implementing the time varying bandwidth notch filter. Such a filter requires two variable coefficients for varying the notch width with time. The advantage of using a LWDF structure is that only one coefficient has variable values to vary the notch width with time. Therefore, the number of memory locations required to implement the proposed design is reduced by half. Moreover, the LWDF is less sensitive to the word-length effects. Thus, the proposed lattice wave digital notch filter (LWDNF) produces better results compared to the existing literature in terms of error analysis. The suggested LWDNF is then implemented on a field-programmable gate array using a Xilinx system generator for the DSP design suite.

关键词： wave digital filters error analysis notch filters field programmable gate arrays logic design Q-factor minimal transient duration field-programmable gate array lattice wave digital filter structure signal transient variable notch bandwidth filter time-varying bandwidth notch filter notch width lattice wave digital notch filter FPGA quality factor infinite impulse response structure minimised transient duration error analysis field programmable gate array Xilinx system generator DSP design suite

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