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A digital direction of arrival estimator based on fast on-line sequential random vector functional link network

AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS 2021年 142卷 153986-153986页

作者： Raiguru, Priyadarshini Sahani, Mrutyunjaya Rout, Susanta Kumar Panda, Dhruba Charan Mishra, Rabindra Kishore Siksha O Anusandhan Deemed Univ Bhubaneswar Odisha India Berhampur Univ Elect Sci & Technol Berhampur Odisha India

This article develops a fast online sequential random vector functional network. In this network, input nodes are connected to both hidden nodes and output nodes. This architecture results in high-speed learning and testing. The network estimates the direction of arrival from signals received by the sparse array in real-time. Neither noisy signal nor effect of mutual coupling among array elements affect the estimation appreciably using the network. The network shows competitive performance in terms of learning speed, accuracy, short event regression time, simplicity, and robustness in comparison to other state-of-the-art methods such as support vector regression, extreme learning machine, and online sequential extreme learning machine. Finally, validation of the network translation into a hardware platform using a fast digital high-speed reconfigurable Xilinx Virtex-5 field-programmable gate array embedded processor for single-source detection completes the work. Comparison with reported measurement shows results with good accuracy and low root mean square error both by the network and its hardware-implemented platform. The direction of arrival estimation is thus possible using the network either through a computer or dedicated hardware as per necessity.

关键词： Fast online sequential random vector functional network Direction of arrival Support vector regression Extreme learning machine Online sequential extreme learning machine field programmable gate array

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Machine Learning for Congestion Management and Routability Prediction within FPGA Placement

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ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2020年第5期25卷 1–25页

作者： Szentimrey, Hannah Al-Hyari, Abeer Foxcroft, Jeremy Martin, Timothy Noel, David Grewal, Gary Areibi, Shawki Univ Guelph 50 Stone Rd E Guelph ON N1G 2W1 Canada

Placement for field programmable gate arrays (FPGAs) is one of the most important but time-consuming steps for achieving design closure. This article proposes the integration of three unique machine learning models into the state-of-the-art analytic placement tool GPlace3.0 with the aim of significantly reducing placement runtimes. The first model, MLCong, is based on linear regression and replaces the computationally expensive global router currently used in GPlace3.0 to estimate switch-level congestion. The second model, DLManage, is a convolutional encoder-decoder that uses heat maps based on the switch-level congestion estimates produced by MLCong to dynamically determine the amount of inflation to apply to each switch to resolve congestion. The third model, DLRoute, is a convolutional neural network that uses the previous heat maps to predict whether or not a placement solution is routable. Once a placement solution is determined to be routable, further optimization may be avoided, leading to improved runtimes. Experimental results obtained using 372 benchmarks provided by Xilinx Inc. show that when all three models are integrated into GPlace3.0, placement runtimes decrease by an average of 48%.

关键词： Placement field programmable gate array congestion routing-aware heterogeneous UltraScale architecture

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Research on virtual simulation of basketball technology 3D animation based on FPGA and motion capture system

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MICROPROCESSORS AND MICROSYSTEMS 2021年 81卷 103679-103679页

作者： Dou, Zi Northwest Minzu Univ Phys Educ Inst Lanzhou 720030 Gansu Peoples R China

A stable structure and group information for measuring the driving dynamic binding character information processing, network control and operation when ready. Created with Unity, Tensol Stream and PyTorch. This method can be done bipedal and quadruped movement in the past occupied the complex and rational activity. The study will help researchers select the appropriate exercise programs and motion capture framework to test their gadgets. The rose to select and added to the open network arena, improve audit in their investigation. Framework has instructed sub conventional and highly accurate three-dimensional movement. Article screening to determine the motion capture framework research study of distributed source in one hundred academic studies used in the report of human activity. The proposed use of support to field programmable gate array (FPGA) virtual computing innovation replay basketball to move the ball from the foundation and other projects, such as the distinction between players and referees. The two-dimensional position of the ball results are calibrated to identify the real position of the ball. Reality from the position of the ball, shoot the scene from every angle camera, and further ground plane. True development continue to see the ball from the top. Tests showed that the proposed calculation obstacles can be handled quickly and less difficult ball, the ball slightly different size and shape.

关键词： 3D Basket Sports Human Motion Capture Systems Ball Movement field programmable gate array

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Neural Networks and FPGA Hardware Accelerators for Millimeter-Wave Radio-over-Fiber Systems 22

Neural Networks and FPGA Hardware Accelerators for Millimete...

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22nd International Conference on Transparent Optical Networks (ICTON)

作者： Lee, Jeonghun He, Jiayuan Wang, Ke Royal Melbourne Inst Technol RMIT Univ Sch Engn Melbourne Vic 3000 Australia Univ Melbourne Sch Comp & Informat Syst Melbourne Vic 3010 Australia

ISBN: (纸本)9781728184234

High speed data streaming has been highly demanded by mobile end users and millimetre-wave (mm-wave) radio-over-fiber (RoF) optical communications have been studied to satisfy the users' demands. To solve various impairments existing in mm-wave RoF systems, neural networks have been proposed and studied due to their capability in solving nonlinear effects and multiple impairments simultaneously. However, previous studies mainly focused on the fully-connected neural network (FC-NN), which has relatively complicated architecture and a large number of parameters to be learnt. To solve this issue, we have proposed the convolutional neural network (CNN) and binary convolutional neural network (BCNN) based decision schemes. In addition, the neural networks in previous studies are typically implemented offline using high-end CPUs or GPUs, which are not practical for optical communication applications. To solve this issue, we have proposed the field-programmable gate array (FPGA) based hardware accelerators, which have the key advantages of reconfigurability, low power consumption, and parallel computation capability. A novel inner parallel optimization method has also proposed to improve the latency with minimal additional power consumption. Results show that the CNN/BCNN implemented with GPU and with the FPGA-based hardware accelerator achieves similar BER performance within the forward-error-correction (FEC) limit, while the FPGA-based hardware accelerators reduce the power consumption significantly.

关键词： millimeter-wave radio-over-fiber system convolutional neural network binary convolutional neural network field programmable gate array neural network hardware accelerator

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FPGA accelerator for CNN: an exploration of the kernel structured sparsity and hybrid arithmetic computation

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JOURNAL OF ELECTRONIC IMAGING 2021年第3期30卷 033034-033034页

作者： Zhang, Guanwen Zhou, Song Duan, Zhemin Zhou, Wei Northwestern Polytech Univ Xian Peoples R China Shandong Prov Res Inst Coal Geol Planning & Explo Jinan Peoples R China

The deployment of large-scale deep neural networks on field programmable gate array (FPGA) platforms is severely hindered by the high requirements on computational resources and off-chip data bandwidth. Traditional nonstructured sparsity algorithms can efficiently reduce the nonzero weights of neural network models. However, the nonstructured sparse connections across channels also degrade the degree of computational parallelism and consequently seriously deteriorate the performance of the FPGA accelerator. We propose an FPGA accelerator by exploring the kernel structured sparsity and hybrid arithmetic computation for the convolutional neural network (CNN). On the one hand, we introduce a hardware-friendly kernel pruning method to reduce the number of arithmetic operations of the CNN model. Our proposed method maintains high accuracy (achieving a less than 0.32% accuracy loss) and achieves a high degree of parallelism. On the other hand, we design a specific hybrid arithmetic computation for the FPGA accelerator to speed up the performance of the pruned CNN model. The FPGA accelerator consists of only 64 sets of hybrid 8-bit and 16-bit floating-point units for the convolution operation. Experiments on VGGNet16 demonstrate that the proposed FPGA accelerator achieves a state-of-the-art 5x convolution operation reduction and a 3x parameter compression. The proposed FPGA accelerator is able to perform at 13.2 FPS, and the corresponding energy efficiency can be boosted up to 1.9 image/J. (C) 2021 SPIE and IS&T

关键词： field programmable gate array convolutional neural network kernel structured sparsity hybrid arithmetic computation

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Mixed-signal data acquisition system for optically detected magnetic resonance of solid-state spins

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REVIEW OF SCIENTIFIC INSTRUMENTS 2021年第11期92卷 114702-114702页

作者： Zhou, Feifei Song, Shupei Deng, Yuxuan Zhang, Ting Chen, Bing Xu, Nanyang Hefei Univ Technol Sch Phys Hefei 230009 Anhui Peoples R China

We report a mixed-signal data acquisition (DAQ) system for optically detected magnetic resonance (ODMR) of solid-state spins. This system is designed and implemented based on a field-programmable-gate-array chip assisted with high-speed peripherals. The ODMR experiments often require high-speed mixed-signal data acquisition and processing for general and specific tasks. To this end, we realized a mixed-signal DAQ system that can acquire both analog and digital signals with precise hardware synchronization. The system consisting of four analog channels (two inputs and two outputs) and 16 optional digital channels works at up to 125 MHz clock rate. With this system, we performed general-purpose ODMR and advanced lock-in detection experiments of nitrogen-vacancy (NV) centers, and the reported DAQ system shows excellent performance in both single and ensemble spin cases. This work provides a uniform DAQ solution for the NV center quantum control system and could be easily extended to other spin-based systems. Published under an exclusive license by AIP Publishing.

关键词： Collections Editor's Pick Topics Quantum information field programmable gate array Digital signal processing Data acquisition Mixed-signal oscilloscopes Optically detected magnetic resonance

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Unavailability analysis of a digital hybrid platform for reactor protection systems

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ANNALS OF NUCLEAR ENERGY 2021年 160卷 108351-108351页

作者： Jeong, Jiye Son, Kibeom Heo, Gyunyoung Kyung Hee Univ 1732 Deogyeong Daero Yongin Gyeonggi Do South Korea Doosan Heavy Ind & Construct Co Ltd 37 Samsung 1 Ro 5 Gil Hwaseong Si Gyeonggi Do South Korea

Transition from conventional analog technology to advanced digital technology is a global trend, and commercial and research reactors are increasingly using digital instrumentation and control (I&C) systems. However, common cause failures (CCFs) of the digital platform are significant issues. In this paper, we proposed a potential solution for such CCFs by implementing a digital hybrid model that combines two different platforms, programmable logic controller (PLC) and field programmable gate array (FPGA). PLCs have been used for decades, while FPGAs are comparatively new in nuclear safety-grade I&C systems. The digital hybrid model was compared with an analog model and individual digital models for each platform in terms of the results using fault tree analysis and generic failure rate database. The quantitative improvements of the proposed digital hybrid model were demonstrated for a reactor protection system. (C) 2021 Elsevier Ltd. All rights reserved.

关键词： Unavailability analysis Reactor protection system programmable logic controller field programmable gate array Fault tree Common cause failure

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DoubleQExt: Hardware and Memory Efficient CNN Through Two Levels of Quantization

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IEEE ACCESS 2021年 9卷 169082-169091页

作者： See, Jin-Chuan Ng, Hui-Fuang Tan, Hung-Khoon Chang, Jing-Jing Lee, Wai-Kong Hwang, Seong Oun Univ Tunku Abdul Rahman Fac Informat & Commun Technol FICT Kampar 31900 Petaling Jaya Malaysia Gachon Univ Dept Comp Engn Seongnam 13120 South Korea

To fulfil the tight area and memory constraints in IoT applications, the design of efficient Convolutional Neural Network (CNN) hardware becomes crucial. Quantization of CNN is one of the promising approach that allows the compression of large CNN into a much smaller one, which is very suitable for IoT applications. Among various proposed quantization schemes, Power-of-two (PoT) quantization enables efficient hardware implementation and small memory consumption for CNN accelerators, but requires retraining of CNN to retain its accuracy. This paper proposes a two-level post-training static quantization technique (DoubleQ) that combines the 8-bit and PoT weight quantization. The CNN weight is first quantized to 8-bit (level one), then further quantized to PoT (level two). This allows multiplication to be carried out using shifters, by expressing the weights in their PoT exponent form. DoubleQ also reduces the memory storage requirement for CNN, as only the exponent of the weights is needed for storage. However, DoubleQ trades the accuracy of the network for reduced memory storage. To recover the accuracy, a selection process (DoubleQExt) was proposed to strategically select some of the less informative layers in the network to be quantized with PoT at the second level. On ResNet-20, the proposed DoubleQ can reduce the memory consumption by 37.50% with 7.28% accuracy degradation compared to 8-bit quantization. By applying DoubleQExt, the accuracy is only degraded by 1.19% compared to 8-bit version while achieving a memory reduction of 23.05%. This result is also 1% more accurate than the state-of-the-art work (SegLog). The proposed DoubleQExt also allows flexible configuration to trade off the memory consumption with better accuracy, which is not found in the other state-of-the-art works. With the proposed two-level weight quantization, one can achieve a more efficient hardware architecture for CNN with minimal impact to the accuracy, which is crucial for IoT applicati

关键词： Quantization (signal) Convolutional neural networks Hardware Memory management field programmable gate arrays Internet of Things Degradation Convolutional neural network quantization Internet of Things deep learning field programmable gate array

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An Embedded FPGA Architecture for Real-Time Model Predictive Control 21st

An Embedded FPGA Architecture for Real-Time Model Predictive...

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21st IFAC World Congress on Automatic Control - Meeting Societal Challenges

作者： Khajanchi, Hussain, I Bruno, Joseph N. Adegbege, Ambrose A. Coll New Jersey Dept Elect & Comp Engn 2000 Pennington Rd Ewing NJ 08628 USA

We develop a custom hardware architecture for real-time implementation of embedded Model Predictive Control (MPC) on a field programmable gate array (FPGA). We propose a novel modular framework that allows for easy and rapid prototyping of control with capability for analog-to-digital conversion, numerical scaling, and digital-to-analog conversion. We demonstrate the effectiveness of the proposed framework for real-time control on a quadruple water tank system. Copyright (C) 2020 The Authors.

关键词： Embedded Model Predictive Control Primal-Dual algorithm Real-Time Control field programmable gate array Quadruple Tank System

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Radar Pulse on Pulse Identification Parallel FFT and Power Envelope Algorithm 11

Radar Pulse on Pulse Identification Parallel FFT and Power E...

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11th IEEE Annual Ubiquitous Computing, Electronics and Mobile Communication Conference (UEMCON)

作者： Juliano, Jordan Lin, Jaron Erdogan, Alex George, Kiran Calif State Univ Fullerton Comp Engn Fullerton CA 92634 USA

ISBN: (纸本)9781728196565

Identification of pulse radar signals is a crucial component in radar receiver processing. Extracting RF radar pulse information in wideband receivers in a dense and noisy environment without prior knowledge of the signal is challenging in high-risk real-time scenarios. Overlapping radar pulses can create complications in identification by creating interference between the signals, causing loss or hidden information. This paper presents a deinterleaving overlapping radar pulse train process by correlating the pulse descriptor words (PDW) of a power envelope based deinterleaving algorithm with a parallel fast Fourier transform (FFT) based deinterleaving algorithm implemented on an MPSoC FPGA.

关键词： Pulse Descriptor Word field programmable gate array Deinterleaving Digital Signal Processing Receivers

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