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ACM International Symposium on Physical Design (ISPD)

作者： Liou, Sin-Hong Liu, Sean Sun, Richard Chen, Hung-Ming Natl Chiao Tung Univ Inst Elect Hsinchu Taiwan Synopsys Inc Hsinchu Taiwan Synopsys Inc Mountain View CA USA

ISBN: (纸本)9781450370912

Multi-FPGA system is a popular approach to achieve hardware acceleration with the scalability to accommodate large designs. To overcome the connectivity constraint between each pair of FPGAs, Time-division multiplexing (TDM) is adopted with the expense of additional delay that dominates the performance on multi-FPGA system based emulator. To the best of our knowledge, there is no prior work on partitioning for multi-FPGA system considering hardware configuration and the impact of TDM. This work proposes a partition methodology to improve timing performance for multi-FPGA system. Delay introduced by TDM is estimated and optimized using look-up table for better efficiency. Our experimental result shows 43% improvement in maximum delay while considering both hardware configuration and impact of TDM compared with cut driven partition approach.

关键词： field programmable gate array Partitioning Physical Design Time-Division-Multiplexing

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Silicon-Photonic Matrix Switches and Control Technologies to Accelerate Switching Speed 4

Silicon-Photonic Matrix Switches and Control Technologies to...

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4th International Conference on Photonics Solutions (ICPS)

作者： Matsuura, Hiroyuki Suzuki, Keijiro Konoike, Ryotaro Ikeda, Kazuhiro Kawashima, Hitoshi Namiki, Shu Natl Inst Adv Ind Sci & Technol 1-1-1 Umezono Tsukuba Ibaraki Japan

ISBN: (数字)9781510634305

ISBN: (纸本)9781510634305

Optical devices based on silicon photonic technology are very important as supporting current and future communication systems in terms of their scale of integration and productivity. Although various devices have been proposed and realized using silicon photonics technology, this paper describes an optical path switch combining a large number of 2x2-unitswitches loaded with electrical heaters on a Mach-Zehnder interferometer (MZI). We have been developed 8x8 and 32x32 optical matrix switches, which employ a path-independent-insertion-loss (PILOSS) configuration that has a feature of the same device count on the any path of the connection. The PILOSS structure has a feature of Strictly-non-blocking, which can connect any input port to any output port without changing existing connections when making a new connection. Each heater of the optical switch is driven by pulse-width-modulation (PWM) generated by a field programmable gate array (FPGA). The calibration of the pulse width according to the 2x2-unit switch state (Cross or Bar) is performed on all of the MZIs in advance, and the values are stored in a table of the FPGA. Separately, Cross / Bar state tables corresponding to the connection pattern of the optical input port and output port are prepared, and the pulse width switching according to the state table is simultaneously performed based on a switching command from the upper layer controller. It takes a certain amount of time to change the heater temperature of the MZI arm for switching. However, it is possible to shorten the switching time by applying a signal named "Turbo pulse" for a short term at the transition. When the temperature is raised by the heater, the switching can be speeded-up by applying a continuous high-level voltage to the heater temporarily. Even in the case of the temperature drops, the switching time can be accelerated by applying a continuous high-level voltage to the heater on the other arm of the MZI. The switching time, which was ac

关键词： Optical matrix switch Silicon photonics Strictly-non-blocking switch Mach-Zehnder interferometer Heater controlled Pulse-width modulation field programmable gate array Switching-time acceleration

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A CNN Accelerator on FPGA with a Flexible Structure 5

A CNN Accelerator on FPGA with a Flexible Structure

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5th International Conference on Computational Intelligence and Applications (ICCIA)

作者： Shan, Dan Cong, Guotao Lu, Wei Dalian Neusoft Univ Informat Dept Elect Engn Dalian Peoples R China Dalian Univ Technol Sch Control Sci & Engn Dalian Peoples R China

ISBN: (纸本)9781728160429

Most of the existing convolutional neural networks (CNNs) are based on PC software, which cannot meet the real-time, low power and miniaturization requirements of the systems. In this paper, a CNN accelerator with flexible structure based on field-programmable gate array (FPGA) is proposed to achieve recognition of MNIST handwritten numeric characters. The system adopts deep pipeline processing and optimizes inter-layer and intra-layer parallelism from two levels of coarse and fine granularity. In view of the similarity of convolution structure, this design adopts structured circuit, which can easily expand the number of layers and neurons. The classification throughput and inter-layer data throughput capability can be improved by rationally organizing the internal memory resources of the FPGA. Compared with the general CPU, it achieves 3 times acceleration at 50MHz frequency, while the power consumption is only 2% of the CPU. Finally performance and power consumption are compared with other accelerators by VGG16.

关键词： convolutional neural networks low power acceleration field programmable gate array parallelism

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HDecoder: A Hardware LDPC Decoder Using High Level Synthesis for Phase Modulated Collinear Holographic Storage

HDecoder: A Hardware LDPC Decoder Using High Level Synthesis...

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International Conference on Optoelectronic and Microelectronic Technology and Application

作者： Zhang, Yifan Cao, Qiang Sun, Lei Yao, Jie Xie, Changsheng Huazhong Univ Sci & Technol Wuhan Natl Lab Optoelect Wuhan Peoples R China Huazhong Univ Sci & Technol Sch Comp Sci & Technol Key Lab Informat Storage Syst Educ Minist Wuhan Peoples R China

ISBN: (纸本)9781510640702

Phase-modulated collinear holographic storage is promising high storage density at cost of high raw bit error rate. We first performed a simulation to analyze the bit-error-rate characteristics of phase-modulated collinear holographic storage under different noise intensity. To ensure high storage capacity with acceptable user biterror-rate, LDPC (Low Density Parity Check Code) is introduced to ensure data reliability. We further analyze the LDPC code error correction performance under different factors and determine the appropriate hardware parameters for the LDPC decoder. Finally, we use High Level Synthesis to fast implement and optimize an LDPC FPGA-based hardware decoder, named as HDecoder. HDecoder achieves 204Mbps decoding throughput, 150x and 4850x higher than CPU-based software decoder and the HLS-based vanilla hardware decoder. Compare to HLS-based vanilla LDPC decoder, HDecoder consumes 55x lower hardware resource per Mbps.

关键词： Collinear Holographic Storage Phase Modulation Low Density Parity Check Code field programmable gate array High Level Synthesis

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Modeling and Implementation of Smart Home and Self-control Window using FPGA and Petri Net 7

Modeling and Implementation of Smart Home and Self-control W...

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7th Annual IEEE PES/IAS PowerAfrica Conference (PAC) - Sustainable and Smart Energy Revolutions for Powering Africa

作者： Ajao, Lukman Adewale Agajo, James Umar, Buhari Ugbede Agboade, Tope Tobi Adegboye, Mutiu Adesina Fed Univ Technol Dept Comp Engn Minna Nigeria Fed Univ Oye Ekiti Dept Comp Engn Ekiti Nigeria

ISBN: (纸本)9781728167466

The function of the window is to provide comfort for the householders by regulating the indoor environment. However, most of the residence windows are still controlled manually. Although, a quite number of automated windows based on the Internet of Things (IoT) has been proposed in the literature, yet a smart windows control with multi-objectives functions related to the environmental factors remain open gap. This paper aims to contribute to this area by developing a cyber-physical system (CPS) for smart room and windows automation control (SRWAC) using set of rules generated from the Petri Net simulator for determining the system response to the inputs data sensed from the indoor and outdoor sensing units (temperature, dust, rain, and carbon monoxide sensors) in coding Atmega 328 controller. We also simulate the window controller using field programmable gate array (FPGA) in Xilinx ISE. The results of the system tested show that automated response of the indoor and outdoor conditions can be achieved spontaneously.

关键词： Cyber-physical system field programmable gate array Home automation system Internet of Things Smart room

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FPGA Implementation of a Novel Dual - BRAM Processor Architecture 43

FPGA Implementation of a Novel Dual - BRAM Processor Archite...

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43rd International Conference on Telecommunications and Signal Processing (TSP)

作者： Ignat, Cristian Farago, Paul Hintea, Sorin Tech Univ Cluj Napoca Bases Elect Dept Cluj Napoca Romania

ISBN: (纸本)9781728163765

Targeting the continuous demand for processing capabilities, field programmable gate arrays (FPGA) offer a facile platform for processor development. FPGAs answer the need for rapid processor prototyping and testing, while also providing hardware solutions for software engineers. In this context, this work proposes a novel high-speed processor architecture, developed around the traditional Harvard architecture with pipelining. The novelty of this work consists in having two block RAM (BRAM) modules implement the data memory, enabling to simultaneously read and write the instruction data and results respectively. Consequently, every pipeline microinstruction is executed in precisely one clock cycle. Besides the pipeline, a register in the accumulator and logical unit (ALU) allows the employment of execution results in successive instructions. These contributions operate towards high-speed operation of the processor, with an average of one instruction per clock cycle. The proposed processor architecture was implemented in VHDL, and the design was validated by simulation in Xilinx ISIM, as well as by practical tests carried out on an Artix7 35T and a Kintex Ultrascale+ FPGA respectively.

关键词： block RAM field programmable gate array Harvard processor pipeline processor

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S-GAT: Accelerating Graph Attention Networks Inference on FPGA Platform with Shift Operation 26

S-GAT: Accelerating Graph Attention Networks Inference on FP...

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26th IEEE International Conference on Parallel and Distributed Systems (IEEE ICPADS)

作者： Yan, Weian Tong, Weiqin Zhi, Xiaoli Shanghai Univ Sch Comp Engn & Sci Shanghai Peoples R China

ISBN: (纸本)9781728190747

Deep learning has been successful in many fields such as acoustics, image, and natural language processing. However, due to the unique characteristics of graphs, deep learning using universal graph data is not easy. The Graph Attention Networks (GATs) show the best performance in multiple authoritative node classification benchmark tests (including transductive and inductive). The purpose of this research is to design and implement an FPGA-based accelerator called S-GAT for graph attention networks that achieves excellent performance on acceleration and energy efficiency without losing accuracy, and does not rely on DSPs and large amounts of on-chip memory. We design S-GAT with software and hardware co-optimization. Specifically, we use model compression and feature quantization to reduce the model size, and use shift addition units (SAUs) to convert multiplication into shift operation to further reduce the computation requirements. We integrate the above optimizations into a universal hardware pipeline for various structures of GATs. At last, we evaluate our design on an Inspur F10A board with an Intel Arria 10 GX1150 and 16 GB DDR3 memory. Experimental results show that S-GAT can achieve 7.34 times speedup over Nvidia Tesla V100 and 593 times over Xeon CPU Gold 5115 while maintaining accuracy, and 48 times and 2400 times on energy efficiency respectively.

关键词： Graph Attention Networks Inference accelerating Heterogeneous computing field programmable gate array Parallel computing Energy efficiency Shift operation

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Architecture of zero-latency ultrafast amplitude detector for high-speed atomic force microscopy

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APPLIED PHYSICS LETTERS 2021年第18期119卷 181602-181602页

作者： Umeda, Kenichi Okamoto, Chihiro Shimizu, Masahiro Watanabe, Shinji Ando, Toshio Kodera, Noriyuki Kanazawa Univ Nano Life Sci Inst WPI NanoLSI Kanazawa Ishikawa 9201192 Japan PRESTO JST 4-1-8 Honcho Kawaguchi Saitama 3320012 Japan Kanazawa Univ Coll Sci & Engn Sch Math & Phys Kanazawa Ishikawa 9201192 Japan CREST JST 4-1-8 Honcho Kawaguchi Saitama 3320012 Japan

The advent of high-speed atomic force microscopy has revolutionized the field of biological science. However, there remains a myriad of phenomena that cannot be observed due to their near-instantaneous dynamics. Improving the temporal resolution is the first step toward observing these biofunctional dynamics. So far, the narrow bandwidth of the amplitude detector circuit has been a major obstacle to this objective. Here, we invent a differential-based ultrafast amplitude detection method with zero intrinsic latency based on the basic trigonometric theorem. We demonstrate that our method manifests superior performance over the conventional methods in respect of the bandwidth and noninvasiveness. This will be a breakthrough in the development of faster high-speed atomic force microscopy. (c) 2021 Author(s).

关键词： Topics: Surface science field programmable gate array Detectors Bioimaging Amplitude modulation Atomic force microscopy Scanning probe microscopy Biophysical techniques Analog circuits Proteins

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Embedded medical big data network and nursing intervention of aspiration pneumonia

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MICROPROCESSORS AND MICROSYSTEMS 2021年 80卷 103659-103659页

作者： Guo, Meiling Bian, Chao Meng, Lingcheng Wang, Yan Jining First Peoples Hosp Dept Radiol Jining 272111 Shandong Peoples R China Jining First Peoples Hosp Dept Acupuncture & Physiotherapy Jining 272111 Shandong Peoples R China

In this work, doctors can find useful tips to discover semantic similarities to diagnostic tasks, natural biomedical language, and writing to obtain effective simulations. It proposes a concrete analytical framework for a considerable collection. It does some preliminary analysis using datasets extracted from the entire graduate entrance exam library. It has developed a web front end to demonstrate this method's practicality in the real-world context. The quickly extending field of enormous information examination is starting to assume a basic function in creating clinical practice and exploration. It gives a device to amass and retain a lot of organized and unstructured information created by the board, investigation, and current medical services frameworks. As of late, big data information examination has been applied to measures that help clinical administrations and illness investigation. The appropriation and R and D in this space are hampered by some key issues intrinsic in the huge information worldview. Basic Analysis of Images, Signals, and Genomics: In this article focus on these key challenges and discusses some of the three promising medical research areas. It targets large amounts of medical data, and the use of multimodal data from different sources has also been discussed in recent studies. Research Areas with the potential and significant impact in providing medical services are also being considered.

关键词： Big data network Nursing intervention Pneumonia Classification field programmable gate array

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Load evaluation of campus football match based on microprocessor and IoT wearable equipment

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MICROPROCESSORS AND MICROSYSTEMS 2021年 81卷 103778-103778页

作者： Xu, Yetong Hu, Wenwu Tianshui Normal Univ Sch Sports & Hlth Tianshui 741000 Gansu Peoples R China Kunming Univ Phys Culture Inst Kunming 650000 Yunnan Peoples R China

Physiological and clinical and translation tools, the wearable device of semiconductor technology equipped with the convergence prediction of health analysis to advanced sports. Test and physical performance, physiological condition, biochemical composition, and subsequent application of indicators associated with mental warning players, development plans, as indicated by the physician or training teams, surrounding player?s performance, improve the protocol?s agreement, reduce the risk of injury. Provide an understanding of sports medicine wearable sensors. Commercial devices will include those described in the scientific literature. The primary purpose is to provide wearable technology to assess the biomechanical and physiological parameters of athletes. The second purpose of, the usefulness of this technology is, to a certain extent, it?s streaming players in various sports fields between the performances of the joint research, academic research groups, sports medicine clinic, and sports teams. It is to identify opportunities. Companion, the wisdom of monitoring biochemical indicators and the player of the wearable use.

关键词： Load evaluation Wearable electronic equipment field programmable gate array Football

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