A novel online dynamic mode decomposition (DMD) approach using a field-programmablegatearray (FPGA), which takes full advantage of the DMD to extract multiple unsteady events and the FPGA system for signal sampling ...
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A novel online dynamic mode decomposition (DMD) approach using a field-programmablegatearray (FPGA), which takes full advantage of the DMD to extract multiple unsteady events and the FPGA system for signal sampling and fast computation, was developed for phase-locking particle image velocimetry (PIV) measurements of unsteady flow behaviors. The turbulent separated and reattaching flow around a finite blunt plate with a length-to-height-ratio L/D = 6.0 was examined to demonstrate this novel approach. The wall-pressure field and the velocity field were measured using arrayed microphones and the conventional planar PIV setup, respectively. Offline DMD analysis of the wall-pressure fluctuation field was first used to identify the dominant modes corresponding to the energetically unsteady events. For each mode, the eigenmode and its mode coefficient reflected the spatial footprint pattern and temporal strength of the unsteady event, respectively. Next, trained machine learning of the mode coefficient was used to establish a phase prediction strategy. Finally, in the online analysis, the relevant eigenmode was cast into the FPGA device to serve as the reference mode for reconstruction with the sampled wall-pressure data, determining the phase signal to fire the PIV setup. High-resolution spatiotemporal evolutions of the dominant flow structures (i.e., the flapping separation bubble, the impinging leading-edge vortex, and the trailing-edge vortex street) were separately assembled. Further measurements demonstrated a clear panoramic view of the synchronous behavior of the enlarging separation bubble and the impinging leading-edge vortex. The proposed online FPGA-DMD approach can serve as a sophisticated strategy for phase-locking PIV measurements of unsteady flow behaviors. Published under license by AIP Publishing.
This paper describes implementation of the Dynamic Matrix Control (DMC) algorithm performed on an Altera field programmable gate array (FPGA) with the Cyclone IV chip. The DMC algorithm is implemented in its analytica...
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ISBN:
(纸本)9783319606996
This paper describes implementation of the Dynamic Matrix Control (DMC) algorithm performed on an Altera field programmable gate array (FPGA) with the Cyclone IV chip. The DMC algorithm is implemented in its analytical (explicit) version which requires computationally simple matrix and vector operations in real time, no on-line optimisation is necessary. The test-bench application is prepared for fast comparison between C and HDL versions of code. A large number of independent logic cells can provide multi-parallel operations to achieve very fast operations. As a result, the algorithm may be used for controlling very fast dynamic processes characterised by sampling periods of millisecond order. Preliminary results of real experiments are demonstrated. The discussed control structure provides possibility to fast change of algorithm.
This paper presents the design of a system that is aimed to provide a flexible, portable and low cost solution for optical fiber based sensor systems. The field programmable gate array (FPGA) provides the digital logi...
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ISBN:
(纸本)9781538604496
This paper presents the design of a system that is aimed to provide a flexible, portable and low cost solution for optical fiber based sensor systems. The field programmable gate array (FPGA) provides the digital logic to implement the system and ability to reconfigure the system operation. It aims to support different optical fiber sensing requirements by the ability to reconfigure the digital circuitry used. It is therefore a hardware configured alternative to a software programmed processor based approach. The work discussed in this paper focuses on the architecture of the FPGA based system with additional circuitry to implement the light source using a light emitting diode (LED), sensor signal sampling using a photodiode and the digital functions implemented using the Xilinx Artix-7 FPGA. The system also includes serial communications to an external computer that allows the system to be used as part of a larger sensor network. In this paper, system control and sensor data visualization on a personal computer (PC) is undertaken using the Python open source programming language.
field programmable gate array (FPGA)-based systems are thought to be a practical option to replace certain obsolete instrumentation and control systems in nuclear power plants. An FPGA is a type of integrated circuit,...
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field programmable gate array (FPGA)-based systems are thought to be a practical option to replace certain obsolete instrumentation and control systems in nuclear power plants. An FPGA is a type of integrated circuit, which is programmed after being manufactured. FPGAs have some advantages over other electronic technologies, such as analog circuits, microprocessors, and programmable Logic Controllers (PLCs), for nuclear instrumentation and control, and safety system applications. However, safety-related issues for FPGA-based systems remain to be verified. Owing to this, modeling FPGA-based systems for safety assessment has now become an important point of research. One potential methodology is the dynamic flowgraph methodology (DFM). It has been used for modeling software/hardware interactions in modern control systems. In this paper, FPGA logic was analyzed using DFM. Four aspects of FPGAs are investigated: the "IEEE 1164 standard," registers (D flip-flops), configurable logic blocks, and an FPGA-based signal compensator. The ModelSim simulations confirmed that DFM was able to accurately model those four FPGA properties, proving that DFM has the potential to be used in the modeling of FPGA-based systems. Furthermore, advantages of DFM over traditional reliability analysis methods and FPGA simulators are presented, along with a discussion of potential issues with using DFM for FPGA-based system modeling. Copyright (C) 2016, Published by Elsevier Korea LLC on behalf of Korean Nuclear Society.
The Internet of Things is becoming increasingly important in traffic, medical treatment, and other industry fields. With the development of the Internet of Things technology, lots of new "things'' need to...
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The Internet of Things is becoming increasingly important in traffic, medical treatment, and other industry fields. With the development of the Internet of Things technology, lots of new "things'' need to be accessed to the Internet of Things. Currently, Internet of Things applications adopt multiple methods to access the heterogeneous devices. How to provide unified access means for those "things'' is a fundamental issue. To solve this problem, a new method is proposed in this article to design a reconfigurable smart interface for multiple Internet of Things devices. The IEEE 1451 standard is adopted for this design, and it comprehensively specifies the smart transducer design and relevant interface protocol to implement the intelligent acquisition for common sensors and actuators. field programmable gate array is adopted for the implementation of this design to reduce consumption of resources and enable the reconfiguration of the whole system. Performance of the proposed system is evaluated, and good performance is achieved in practical application for office environment monitoring.
This article presents a hybrid sensorless speed controller for permanent magnet synchronous motor drives using field programmable gate array technology. The I-f startup strategy is applied to permanent magnet synchron...
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This article presents a hybrid sensorless speed controller for permanent magnet synchronous motor drives using field programmable gate array technology. The I-f startup strategy is applied to permanent magnet synchronous motor drives at the startup condition and then it will smoothly switch to extended Kalman filter-based sensorless field-oriented control at the adequate condition. The I-f startup is a simple strategy and suitable for the low-speed sensorless control without initial rotor position estimation and machine parameters estimation. Meanwhile, the extended Kalman filter-based sensorless field-oriented control is appropriate for the medium- and high-speed sensorless control. Therefore, combining two approaches, the sensorless permanent magnet synchronous motor can be smoothly operated from a standstill to a high-speed condition. In this article, first, the mathematical modeling of permanent magnet synchronous motor is introduced. Also, the I-f startup strategy is conducted, and the rotor position estimation algorithm by extended Kalman filter is derived. Second, a very high-speed integrated circuit hardware description language is presented to describe the behavior of the adopted estimation and control algorithm. This application codes have been confirmed using Simulink and ModelSim co-simulation. Finally, a field programmable gate array-based experimental system is utilized to verify the correctness and effectiveness of the proposed hybrid sensorless speed controller for a permanent magnet synchronous motor and a ceiling fan motor.
In this paper, an Ultra High Frequency (UHF) base band processor for a passive tag is presented. It proposes a Radio Frequency Identification (RFID) tag digital base band architecture which is compatible with the EPC ...
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In this paper, an Ultra High Frequency (UHF) base band processor for a passive tag is presented. It proposes a Radio Frequency Identification (RFID) tag digital base band architecture which is compatible with the EPC C C2/ISO18000-6B protocol. Several design approaches such as clock gating technique, clock strobe design and clock management are used. In order to reduce the area Decimal Matrix Code (DMC) technique is used. The digital base band processor has been simulated and implemented using Xilinx platform. The complete design is verified and tested on Spartan-6 field programmable gate array (FPGA) board. The performance of system is measured in terms of power. The synthesis result shows that, the power required for complete design of digital baseband processor is 5mW on a supply voltage of 1.2 V.
The binary coded decimal (BCD) system is suitable for digital communication, which can be designed by field programmable gate array (FPGA) technology, where look up table (LUT) is one of the major components of FPGA. ...
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The binary coded decimal (BCD) system is suitable for digital communication, which can be designed by field programmable gate array (FPGA) technology, where look up table (LUT) is one of the major components of FPGA. In this study, the authors proposed a low power and area efficient LUT-based BCD adder which is constructed basically in three steps: First, a new technique is introduced for the BCD addition to obtain the correct BCD digit. Second, a new controller circuit of LUT is presented which is designed to select and send Read/Write voltage to memory cell for performing Read or Write operation. Finally, a compact BCD adder is designed using the proposed LUT. Their proposed 2-input LUT outperforms the existing best one providing 65.8% improvement in terms of area, 44.1% for Read operation and 43.5% for Write operation in power consumption. The proposed BCD adder using FPGA gains a radical achievement compared with the existing best-known LUT-based BCD adder providing prominent better performance of 65.6% in area and 48.3% less power consumption.
This paper presents an analysis of the radiation tolerance of field-programmablegate-array-based space computers. The primary failure mechanism studied in this paper is single-event effects due to high-energy ionizin...
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This paper presents an analysis of the radiation tolerance of field-programmablegate-array-based space computers. The primary failure mechanism studied in this paper is single-event effects due to high-energy ionizing radiation. The analysis is performed on the most common architectures deployed on field-programmablegate-array-based systems including simplex, triple modular redundant, inclusion of spares, and configuration memory scrubbing. The reliability of each system is modeled using a Markov chain to predict its mean time to failure. Orbital dependencies are discussed in addition to a comparison of reliability across different process nodes.
Design engineering process for field programmable gate array (FPGA)-based reactor trip functions are developed in this work. The process discussed in this work is based on the systems engineering approach. The overall...
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Design engineering process for field programmable gate array (FPGA)-based reactor trip functions are developed in this work. The process discussed in this work is based on the systems engineering approach. The overall design process is effectively implemented by combining with design and implementation processes. It transforms its overall development process from traditional V-model to Y-model. This approach gives the benefit of concurrent engineering of design work with software implementation. As a result, it reduces development time and effort. The design engineering process consisted of five activities, which are performed and discussed: needs/systems analysis;requirement analysis;functional analysis;design synthesis;and design verification and validation. Those activities are used to develop FPGA-based reactor bistable trip functions that trigger reactor trip when the process input value exceeds the setpoint. To implement design synthesis effectively, a model-based design technique is implied. The finite-state machine with data path structural modeling technique together with very high speed integrated circuit hardware description language and the Aldec Active-HDL tool are used to design, model, and verify the reactor bistable trip functions for nuclear power plants. Copyright (C) 2016, Published by Elsevier Korea LLC on behalf of Korean Nuclear Society.
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